llvm.org GIT mirror llvm / cff7178
Add an ARM RSBrr instruction for disassembly only. Partial fix for PR7792. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110358 91177308-0d34-0410-b5e6-96231b3b80d8 Bob Wilson 10 years ago
2 changed file(s) with 13 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
16281628 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
16291629 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
16301630
1631 // These don't define reg/reg forms, because they are handled above.
16321631 def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
16331632 IIC_iALUi, "rsb", "\t$dst, $a, $b",
16341633 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]> {
16351634 let Inst{25} = 1;
1635 }
1636
1637 // The reg/reg form is only defined for the disassembler; for codegen it is
1638 // equivalent to SUBrr.
1639 def RSBrr : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
1640 IIC_iALUr, "rsb", "\t$dst, $a, $b",
1641 [/* For disassembly only; pattern left blank */]> {
1642 let Inst{25} = 0;
1643 let Inst{11-4} = 0b00000000;
16361644 }
16371645
16381646 def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
6060 # CHECK: rfedb r0!
6161 0x00 0x0a 0x30 0xf9
6262
63 # CHECK-NOT: rsbeq r0, r2, r0, lsl #0
64 # CHECK: rsbeq r0, r2, r0
65 0x00 0x00 0x62 0x00
66
6367 # CHECK: sbcs r0, pc, #1
6468 0x01 0x00 0xdf 0xe2
6569