llvm.org GIT mirror llvm / cfe09ed
[PATCH] PowerPC: Expand load extend vector operations This patch expands the SEXTLOAD, ZEXTLOAD, and EXTLOAD operations for vector types when altivec is enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167386 91177308-0d34-0410-b5e6-96231b3b80d8 Adhemerval Zanella 7 years ago
2 changed file(s) with 165 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
360360 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
361361 setOperationAction(ISD::CTTZ, VT, Expand);
362362 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
363 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
364
365 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
366 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
367 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
368 setTruncStoreAction(VT, InnerVT, Expand);
369 }
370 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
371 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
372 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
363373 }
364374
365375 for (unsigned i = (unsigned)MVT::FIRST_FP_VECTOR_VALUETYPE;
0 ; RUN: llc -mcpu=pwr6 -mattr=+altivec < %s | FileCheck %s
1
2 ; Check vector extend load expansion with altivec enabled.
3
4 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
5 target triple = "powerpc64-unknown-linux-gnu"
6
7 ; Altivec does not provides an sext intruction, so it expands
8 ; a set of vector stores (stvx), bytes load/sign expand/store
9 ; (lbz/stb), and a final vector load (lvx) to load the result
10 ; extended vector.
11 define <16 x i8> @v16si8_sext_in_reg(<16 x i8> %a) {
12 %b = trunc <16 x i8> %a to <16 x i4>
13 %c = sext <16 x i4> %b to <16 x i8>
14 ret <16 x i8> %c
15 }
16 ; CHECK: v16si8_sext_in_reg:
17 ; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
18 ; CHECK: lbz
19 ; CHECK: stb
20 ; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
21 ; CHECK: lbz
22 ; CHECK: stb
23 ; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
24 ; CHECK: lbz
25 ; CHECK: stb
26 ; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
27 ; CHECK: lbz
28 ; CHECK: stb
29 ; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
30 ; CHECK: lbz
31 ; CHECK: stb
32 ; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
33 ; CHECK: lbz
34 ; CHECK: stb
35 ; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
36 ; CHECK: lbz
37 ; CHECK: stb
38 ; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
39 ; CHECK: lbz
40 ; CHECK: stb
41 ; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
42 ; CHECK: lbz
43 ; CHECK: stb
44 ; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
45 ; CHECK: lbz
46 ; CHECK: stb
47 ; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
48 ; CHECK: lbz
49 ; CHECK: stb
50 ; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
51 ; CHECK: lbz
52 ; CHECK: stb
53 ; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
54 ; CHECK: lbz
55 ; CHECK: stb
56 ; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
57 ; CHECK: lbz
58 ; CHECK: stb
59 ; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
60 ; CHECK: lbz
61 ; CHECK: stb
62 ; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
63 ; CHECK: lbz
64 ; CHECK: stb
65 ; CHECK: lvx 2, {{[0-9]+}}, {{[0-9]+}}
66
67 ; The zero extend uses a more clever logic: a vector splat
68 ; and a logic and to set higher bits to 0.
69 define <16 x i8> @v16si8_zext_in_reg(<16 x i8> %a) {
70 %b = trunc <16 x i8> %a to <16 x i4>
71 %c = zext <16 x i4> %b to <16 x i8>
72 ret <16 x i8> %c
73 }
74 ; CHECK: v16si8_zext_in_reg:
75 ; CHECK: vspltisb [[VMASK:[0-9]+]], 15
76 ; CHECK-NEXT: vand 2, 2, [[VMASK]]
77
78 ; Same as v16si8_sext_in_reg, expands to load/store halfwords (lhz/sth).
79 define <8 x i16> @v8si16_sext_in_reg(<8 x i16> %a) {
80 %b = trunc <8 x i16> %a to <8 x i8>
81 %c = sext <8 x i8> %b to <8 x i16>
82 ret <8 x i16> %c
83 }
84 ; CHECK: v8si16_sext_in_reg:
85 ; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
86 ; CHECK: lhz
87 ; CHECK: sth
88 ; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
89 ; CHECK: lhz
90 ; CHECK: sth
91 ; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
92 ; CHECK: lhz
93 ; CHECK: sth
94 ; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
95 ; CHECK: lhz
96 ; CHECK: sth
97 ; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
98 ; CHECK: lhz
99 ; CHECK: sth
100 ; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
101 ; CHECK: lhz
102 ; CHECK: sth
103 ; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
104 ; CHECK: lhz
105 ; CHECK: sth
106 ; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
107 ; CHECK: lhz
108 ; CHECK: sth
109 ; CHECK: lvx 2, {{[0-9]+}}, {{[0-9]+}}
110
111 ; Same as v8si16_sext_in_reg, but instead of creating the mask
112 ; with a splat, loads it from memory.
113 define <8 x i16> @v8si16_zext_in_reg(<8 x i16> %a) {
114 %b = trunc <8 x i16> %a to <8 x i8>
115 %c = zext <8 x i8> %b to <8 x i16>
116 ret <8 x i16> %c
117 }
118 ; CHECK: v8si16_zext_in_reg:
119 ; CHECK: ld [[RMASKTOC:[0-9]+]], .LC{{[0-9]+}}@toc(2)
120 ; CHECK-NEXT: lvx [[VMASK:[0-9]+]], {{[0-9]+}}, [[RMASKTOC]]
121 ; CHECK-NEXT: vand 2, 2, [[VMASK]]
122
123 ; Same as v16si8_sext_in_reg, expands to load halfword (lha) and
124 ; store words (stw).
125 define <4 x i32> @v4si32_sext_in_reg(<4 x i32> %a) {
126 %b = trunc <4 x i32> %a to <4 x i16>
127 %c = sext <4 x i16> %b to <4 x i32>
128 ret <4 x i32> %c
129 }
130 ; CHECK: v4si32_sext_in_reg:
131 ; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
132 ; CHECK: lha
133 ; CHECK: stw
134 ; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
135 ; CHECK: lha
136 ; CHECK: stw
137 ; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
138 ; CHECK: lha
139 ; CHECK: stw
140 ; CHECK: stvx 2, {{[0-9]+}}, {{[0-9]+}}
141 ; CHECK: lha
142 ; CHECK: stw
143 ; CHECK: lvx 2, {{[0-9]+}}, {{[0-9]+}}
144
145 ; Same as v8si16_sext_in_reg.
146 define <4 x i32> @v4si32_zext_in_reg(<4 x i32> %a) {
147 %b = trunc <4 x i32> %a to <4 x i16>
148 %c = zext <4 x i16> %b to <4 x i32>
149 ret <4 x i32> %c
150 }
151 ; CHECK: v4si32_zext_in_reg:
152 ; CHECK: vspltisw [[VMASK:[0-9]+]], -16
153 ; CHECK-NEXT: vsrw [[VMASK]], [[VMASK]], [[VMASK]]
154 ; CHECK-NEXT: vand 2, 2, [[VMASK]]