llvm.org GIT mirror llvm / cf40c3d
[InstCombine] add vector test with undef elts; NFC git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330547 91177308-0d34-0410-b5e6-96231b3b80d8 Sanjay Patel 1 year, 6 months ago
1 changed file(s) with 13 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
478478 ret <4 x i32> %or
479479 }
480480
481 define <4 x i32> @vec_not_sel_consts_undef_elts(<4 x i32> %a, <4 x i32> %b) {
482 ; CHECK-LABEL: @vec_not_sel_consts_undef_elts(
483 ; CHECK-NEXT: [[AND1:%.*]] = and <4 x i32> [[A:%.*]],
484 ; CHECK-NEXT: [[AND2:%.*]] = and <4 x i32> [[B:%.*]],
485 ; CHECK-NEXT: [[OR:%.*]] = or <4 x i32> [[AND1]], [[AND2]]
486 ; CHECK-NEXT: ret <4 x i32> [[OR]]
487 ;
488 %and1 = and <4 x i32> %a,
489 %and2 = and <4 x i32> %b,
490 %or = or <4 x i32> %and1, %and2
491 ret <4 x i32> %or
492 }
493
481494 ; The inverted constants may be operands of xor instructions.
482495
483496 define <4 x i32> @vec_sel_xor(<4 x i32> %a, <4 x i32> %b, <4 x i1> %c) {