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Merging r329268: ------------------------------------------------------------------------ r329268 | sdardis | 2018-04-05 03:30:17 -0700 (Thu, 05 Apr 2018) | 2 lines [mips] Regenerate test before posting patch for constant multiplication (NFC) ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@332778 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 1 year, 4 months ago
1 changed file(s) with 749 addition(s) and 57 deletion(s). Raw diff Collapse all Expand all
None ; RUN: llc -march=mipsel < %s | FileCheck %s
1 ; RUN: llc -march=mips64el < %s | FileCheck %s -check-prefixes=CHECK,CHECK64
2
3 ; CHECK-LABEL: mul5_32:
4 ; CHECK: sll $[[R0:[0-9]+]], $4, 2
5 ; CHECK: addu ${{[0-9]+}}, $[[R0]], $4
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -mtriple=mipsel-mti-linux-gnu < %s | FileCheck %s -check-prefix=MIPS32
2 ; RUN: llc -mtriple=mips64el-mti-linux-gnu < %s | FileCheck %s -check-prefix=MIPS64
3
64
75 define i32 @mul5_32(i32 signext %a) {
6 ; MIPS32-LABEL: mul5_32:
7 ; MIPS32: # %bb.0: # %entry
8 ; MIPS32-NEXT: sll $1, $4, 2
9 ; MIPS32-NEXT: jr $ra
10 ; MIPS32-NEXT: addu $2, $1, $4
11 ;
12 ; MIPS64-LABEL: mul5_32:
13 ; MIPS64: # %bb.0: # %entry
14 ; MIPS64-NEXT: sll $1, $4, 2
15 ; MIPS64-NEXT: jr $ra
16 ; MIPS64-NEXT: addu $2, $1, $4
817 entry:
918 %mul = mul nsw i32 %a, 5
1019 ret i32 %mul
1120 }
1221
13 ; CHECK-LABEL: mul27_32:
14 ; CHECK-DAG: sll $[[R0:[0-9]+]], $4, 2
15 ; CHECK-DAG: addu $[[R1:[0-9]+]], $[[R0]], $4
16 ; CHECK-DAG: sll $[[R2:[0-9]+]], $4, 5
17 ; CHECK: subu ${{[0-9]+}}, $[[R2]], $[[R1]]
18
1922 define i32 @mul27_32(i32 signext %a) {
23 ; MIPS32-LABEL: mul27_32:
24 ; MIPS32: # %bb.0: # %entry
25 ; MIPS32-NEXT: sll $1, $4, 2
26 ; MIPS32-NEXT: addu $1, $1, $4
27 ; MIPS32-NEXT: sll $2, $4, 5
28 ; MIPS32-NEXT: jr $ra
29 ; MIPS32-NEXT: subu $2, $2, $1
30 ;
31 ; MIPS64-LABEL: mul27_32:
32 ; MIPS64: # %bb.0: # %entry
33 ; MIPS64-NEXT: sll $1, $4, 2
34 ; MIPS64-NEXT: addu $1, $1, $4
35 ; MIPS64-NEXT: sll $2, $4, 5
36 ; MIPS64-NEXT: jr $ra
37 ; MIPS64-NEXT: subu $2, $2, $1
2038 entry:
2139 %mul = mul nsw i32 %a, 27
2240 ret i32 %mul
2341 }
2442
25 ; CHECK-LABEL: muln2147483643_32:
26 ; CHECK-DAG: sll $[[R0:[0-9]+]], $4, 2
27 ; CHECK-DAG: addu $[[R1:[0-9]+]], $[[R0]], $4
28 ; CHECK-DAG: sll $[[R2:[0-9]+]], $4, 31
29 ; CHECK: addu ${{[0-9]+}}, $[[R2]], $[[R1]]
30
3143 define i32 @muln2147483643_32(i32 signext %a) {
44 ; MIPS32-LABEL: muln2147483643_32:
45 ; MIPS32: # %bb.0: # %entry
46 ; MIPS32-NEXT: sll $1, $4, 2
47 ; MIPS32-NEXT: addu $1, $1, $4
48 ; MIPS32-NEXT: sll $2, $4, 31
49 ; MIPS32-NEXT: jr $ra
50 ; MIPS32-NEXT: addu $2, $2, $1
51 ;
52 ; MIPS64-LABEL: muln2147483643_32:
53 ; MIPS64: # %bb.0: # %entry
54 ; MIPS64-NEXT: sll $1, $4, 2
55 ; MIPS64-NEXT: addu $1, $1, $4
56 ; MIPS64-NEXT: sll $2, $4, 31
57 ; MIPS64-NEXT: jr $ra
58 ; MIPS64-NEXT: addu $2, $2, $1
3259 entry:
3360 %mul = mul nsw i32 %a, -2147483643
3461 ret i32 %mul
3562 }
3663
37 ; CHECK64-LABEL: muln9223372036854775805_64:
38 ; CHECK64-DAG: dsll $[[R0:[0-9]+]], $4, 1
39 ; CHECK64-DAG: daddu $[[R1:[0-9]+]], $[[R0]], $4
40 ; CHECK64-DAG: dsll $[[R2:[0-9]+]], $4, 63
41 ; CHECK64: daddu ${{[0-9]+}}, $[[R2]], $[[R1]]
42
4364 define i64 @muln9223372036854775805_64(i64 signext %a) {
65 ; MIPS32-LABEL: muln9223372036854775805_64:
66 ; MIPS32: # %bb.0: # %entry
67 ; MIPS32-NEXT: sll $1, $4, 1
68 ; MIPS32-NEXT: addu $2, $1, $4
69 ; MIPS32-NEXT: sltu $1, $2, $1
70 ; MIPS32-NEXT: srl $3, $4, 31
71 ; MIPS32-NEXT: sll $6, $5, 1
72 ; MIPS32-NEXT: or $3, $6, $3
73 ; MIPS32-NEXT: addu $3, $3, $5
74 ; MIPS32-NEXT: addu $1, $3, $1
75 ; MIPS32-NEXT: sll $3, $4, 31
76 ; MIPS32-NEXT: jr $ra
77 ; MIPS32-NEXT: addu $3, $3, $1
78 ;
79 ; MIPS64-LABEL: muln9223372036854775805_64:
80 ; MIPS64: # %bb.0: # %entry
81 ; MIPS64-NEXT: dsll $1, $4, 1
82 ; MIPS64-NEXT: daddu $1, $1, $4
83 ; MIPS64-NEXT: dsll $2, $4, 63
84 ; MIPS64-NEXT: jr $ra
85 ; MIPS64-NEXT: daddu $2, $2, $1
4486 entry:
4587 %mul = mul nsw i64 %a, -9223372036854775805
4688 ret i64 %mul
4789 }
4890
49 ; CHECK64-LABEL: muln170141183460469231731687303715884105725_128:
50 ; CHECK64-DAG: dsrl $[[R0:[0-9]+]], $4, 63
51 ; CHECK64-DAG: dsll $[[R1:[0-9]+]], $5, 1
52 ; CHECK64-DAG: or $[[R2:[0-9]+]], $[[R1]], $[[R0]]
53 ; CHECK64-DAG: daddu $[[R3:[0-9]+]], $[[R2]], $5
54 ; CHECK64-DAG: dsll $[[R4:[0-9]+]], $4, 1
55 ; CHECK64-DAG: daddu $[[R5:[0-9]+]], $[[R4]], $4
56 ; CHECK64-DAG: sltu $[[R6:[0-9]+]], $[[R5]], $[[R4]]
57 ; CHECK64-DAG: dsll $[[R7:[0-9]+]], $[[R6]], 32
58 ; CHECK64-DAG: dsrl $[[R8:[0-9]+]], $[[R7]], 32
59 ; CHECK64-DAG: daddu $[[R9:[0-9]+]], $[[R3]], $[[R8]]
60 ; CHECK64-DAG: dsll $[[R10:[0-9]+]], $4, 63
61 ; CHECK64: daddu ${{[0-9]+}}, $[[R10]], $[[R9]]
62
6391 define i128 @muln170141183460469231731687303715884105725_128(i128 signext %a) {
92 ; MIPS32-LABEL: muln170141183460469231731687303715884105725_128:
93 ; MIPS32: # %bb.0: # %entry
94 ; MIPS32-NEXT: sll $1, $4, 1
95 ; MIPS32-NEXT: addu $2, $1, $4
96 ; MIPS32-NEXT: sltu $1, $2, $1
97 ; MIPS32-NEXT: srl $3, $4, 31
98 ; MIPS32-NEXT: sll $8, $5, 1
99 ; MIPS32-NEXT: or $8, $8, $3
100 ; MIPS32-NEXT: addu $3, $8, $5
101 ; MIPS32-NEXT: addu $3, $3, $1
102 ; MIPS32-NEXT: sltu $9, $3, $8
103 ; MIPS32-NEXT: xor $8, $3, $8
104 ; MIPS32-NEXT: movz $9, $1, $8
105 ; MIPS32-NEXT: srl $1, $5, 31
106 ; MIPS32-NEXT: sll $5, $6, 1
107 ; MIPS32-NEXT: or $5, $5, $1
108 ; MIPS32-NEXT: addu $8, $5, $6
109 ; MIPS32-NEXT: addu $1, $8, $9
110 ; MIPS32-NEXT: sltu $5, $8, $5
111 ; MIPS32-NEXT: srl $6, $6, 31
112 ; MIPS32-NEXT: sll $9, $7, 1
113 ; MIPS32-NEXT: or $6, $9, $6
114 ; MIPS32-NEXT: addu $6, $6, $7
115 ; MIPS32-NEXT: addu $5, $6, $5
116 ; MIPS32-NEXT: sll $4, $4, 31
117 ; MIPS32-NEXT: sltu $6, $1, $8
118 ; MIPS32-NEXT: addu $5, $5, $6
119 ; MIPS32-NEXT: addu $5, $4, $5
120 ; MIPS32-NEXT: jr $ra
121 ; MIPS32-NEXT: move $4, $1
122 ;
123 ; MIPS64-LABEL: muln170141183460469231731687303715884105725_128:
124 ; MIPS64: # %bb.0: # %entry
125 ; MIPS64-NEXT: dsrl $1, $4, 63
126 ; MIPS64-NEXT: dsll $2, $5, 1
127 ; MIPS64-NEXT: or $1, $2, $1
128 ; MIPS64-NEXT: daddu $1, $1, $5
129 ; MIPS64-NEXT: dsll $3, $4, 1
130 ; MIPS64-NEXT: daddu $2, $3, $4
131 ; MIPS64-NEXT: sltu $3, $2, $3
132 ; MIPS64-NEXT: dsll $3, $3, 32
133 ; MIPS64-NEXT: dsrl $3, $3, 32
134 ; MIPS64-NEXT: daddu $1, $1, $3
135 ; MIPS64-NEXT: dsll $3, $4, 63
136 ; MIPS64-NEXT: jr $ra
137 ; MIPS64-NEXT: daddu $3, $3, $1
64138 entry:
65139 %mul = mul nsw i128 %a, -170141183460469231731687303715884105725
66140 ret i128 %mul
67141 }
68142
69 ; CHECK64-LABEL: mul170141183460469231731687303715884105723_128:
70 ; CHECK64-DAG: dsrl $[[R0:[0-9]+]], $4, 62
71 ; CHECK64-DAG: dsll $[[R1:[0-9]+]], $5, 2
72 ; CHECK64-DAG: or $[[R2:[0-9]+]], $[[R1]], $[[R0]]
73 ; CHECK64-DAG: daddu $[[R3:[0-9]+]], $[[R2]], $5
74 ; CHECK64-DAG: dsll $[[R4:[0-9]+]], $4, 2
75 ; CHECK64-DAG: daddu $[[R5:[0-9]+]], $[[R4]], $4
76 ; CHECK64-DAG: sltu $[[R6:[0-9]+]], $[[R5]], $[[R4]]
77 ; CHECK64-DAG: dsll $[[R7:[0-9]+]], $[[R6]], 32
78 ; CHECK64-DAG: dsrl $[[R8:[0-9]+]], $[[R7]], 32
79 ; CHECK64-DAG: daddu $[[R9:[0-9]+]], $[[R3]], $[[R8]]
80 ; CHECK64-DAG: dsll $[[R10:[0-9]+]], $4, 63
81 ; CHECK64-DAG: dsubu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
82 ; CHECK64-DAG: sltu $[[R12:[0-9]+]], $zero, $[[R5]]
83 ; CHECK64-DAG: dsll $[[R13:[0-9]+]], $[[R12]], 32
84 ; CHECK64-DAG: dsrl $[[R14:[0-9]+]], $[[R13]], 32
85 ; CHECK64-DAG: dsubu $[[R15:[0-9]+]], $[[R11]], $[[R14]]
86 ; CHECK64: dnegu ${{[0-9]+}}, $[[R5]]
87
88143 define i128 @mul170141183460469231731687303715884105723_128(i128 signext %a) {
144 ; MIPS32-LABEL: mul170141183460469231731687303715884105723_128:
145 ; MIPS32: # %bb.0: # %entry
146 ; MIPS32-NEXT: sll $1, $4, 2
147 ; MIPS32-NEXT: addu $2, $1, $4
148 ; MIPS32-NEXT: sltu $1, $2, $1
149 ; MIPS32-NEXT: srl $3, $4, 30
150 ; MIPS32-NEXT: sll $8, $5, 2
151 ; MIPS32-NEXT: or $3, $8, $3
152 ; MIPS32-NEXT: addu $8, $3, $5
153 ; MIPS32-NEXT: addu $8, $8, $1
154 ; MIPS32-NEXT: sltu $9, $8, $3
155 ; MIPS32-NEXT: xor $3, $8, $3
156 ; MIPS32-NEXT: sltu $10, $zero, $8
157 ; MIPS32-NEXT: sltu $11, $zero, $2
158 ; MIPS32-NEXT: movz $10, $11, $8
159 ; MIPS32-NEXT: movz $9, $1, $3
160 ; MIPS32-NEXT: srl $1, $5, 30
161 ; MIPS32-NEXT: sll $3, $6, 2
162 ; MIPS32-NEXT: or $1, $3, $1
163 ; MIPS32-NEXT: addu $3, $1, $6
164 ; MIPS32-NEXT: addu $5, $3, $9
165 ; MIPS32-NEXT: sll $4, $4, 31
166 ; MIPS32-NEXT: negu $9, $5
167 ; MIPS32-NEXT: sltu $12, $9, $10
168 ; MIPS32-NEXT: sltu $13, $5, $3
169 ; MIPS32-NEXT: sltu $1, $3, $1
170 ; MIPS32-NEXT: srl $3, $6, 30
171 ; MIPS32-NEXT: sll $6, $7, 2
172 ; MIPS32-NEXT: or $3, $6, $3
173 ; MIPS32-NEXT: addu $3, $3, $7
174 ; MIPS32-NEXT: addu $1, $3, $1
175 ; MIPS32-NEXT: addu $1, $1, $13
176 ; MIPS32-NEXT: subu $1, $4, $1
177 ; MIPS32-NEXT: sltu $3, $zero, $5
178 ; MIPS32-NEXT: subu $1, $1, $3
179 ; MIPS32-NEXT: subu $5, $1, $12
180 ; MIPS32-NEXT: subu $4, $9, $10
181 ; MIPS32-NEXT: negu $1, $8
182 ; MIPS32-NEXT: subu $3, $1, $11
183 ; MIPS32-NEXT: jr $ra
184 ; MIPS32-NEXT: negu $2, $2
185 ;
186 ; MIPS64-LABEL: mul170141183460469231731687303715884105723_128:
187 ; MIPS64: # %bb.0: # %entry
188 ; MIPS64-NEXT: dsrl $1, $4, 62
189 ; MIPS64-NEXT: dsll $2, $5, 2
190 ; MIPS64-NEXT: or $1, $2, $1
191 ; MIPS64-NEXT: daddu $1, $1, $5
192 ; MIPS64-NEXT: dsll $2, $4, 2
193 ; MIPS64-NEXT: daddu $5, $2, $4
194 ; MIPS64-NEXT: sltu $2, $5, $2
195 ; MIPS64-NEXT: dsll $2, $2, 32
196 ; MIPS64-NEXT: dsrl $2, $2, 32
197 ; MIPS64-NEXT: daddu $1, $1, $2
198 ; MIPS64-NEXT: dsll $2, $4, 63
199 ; MIPS64-NEXT: dsubu $1, $2, $1
200 ; MIPS64-NEXT: sltu $2, $zero, $5
201 ; MIPS64-NEXT: dsll $2, $2, 32
202 ; MIPS64-NEXT: dsrl $2, $2, 32
203 ; MIPS64-NEXT: dsubu $3, $1, $2
204 ; MIPS64-NEXT: jr $ra
205 ; MIPS64-NEXT: dnegu $2, $5
89206 entry:
90207 %mul = mul nsw i128 %a, 170141183460469231731687303715884105723
91208 ret i128 %mul
92209 }
210
211 define i32 @mul42949673_32(i32 %a) {
212 ; MIPS32-LABEL: mul42949673_32:
213 ; MIPS32: # %bb.0:
214 ; MIPS32-NEXT: sll $1, $4, 3
215 ; MIPS32-NEXT: addu $1, $1, $4
216 ; MIPS32-NEXT: sll $2, $4, 5
217 ; MIPS32-NEXT: addu $1, $2, $1
218 ; MIPS32-NEXT: sll $2, $4, 10
219 ; MIPS32-NEXT: subu $1, $2, $1
220 ; MIPS32-NEXT: sll $2, $4, 13
221 ; MIPS32-NEXT: addu $1, $2, $1
222 ; MIPS32-NEXT: sll $2, $4, 15
223 ; MIPS32-NEXT: addu $1, $2, $1
224 ; MIPS32-NEXT: sll $2, $4, 20
225 ; MIPS32-NEXT: subu $1, $2, $1
226 ; MIPS32-NEXT: sll $2, $4, 25
227 ; MIPS32-NEXT: sll $3, $4, 23
228 ; MIPS32-NEXT: addu $1, $3, $1
229 ; MIPS32-NEXT: jr $ra
230 ; MIPS32-NEXT: addu $2, $2, $1
231 ;
232 ; MIPS64-LABEL: mul42949673_32:
233 ; MIPS64: # %bb.0:
234 ; MIPS64-NEXT: sll $1, $4, 0
235 ; MIPS64-NEXT: sll $2, $1, 3
236 ; MIPS64-NEXT: addu $2, $2, $1
237 ; MIPS64-NEXT: sll $3, $1, 5
238 ; MIPS64-NEXT: addu $2, $3, $2
239 ; MIPS64-NEXT: sll $3, $1, 10
240 ; MIPS64-NEXT: subu $2, $3, $2
241 ; MIPS64-NEXT: sll $3, $1, 13
242 ; MIPS64-NEXT: addu $2, $3, $2
243 ; MIPS64-NEXT: sll $3, $1, 15
244 ; MIPS64-NEXT: addu $2, $3, $2
245 ; MIPS64-NEXT: sll $3, $1, 20
246 ; MIPS64-NEXT: subu $2, $3, $2
247 ; MIPS64-NEXT: sll $3, $1, 25
248 ; MIPS64-NEXT: sll $1, $1, 23
249 ; MIPS64-NEXT: addu $1, $1, $2
250 ; MIPS64-NEXT: jr $ra
251 ; MIPS64-NEXT: addu $2, $3, $1
252 %b = mul i32 %a, 42949673
253 ret i32 %b
254 }
255
256 define i64 @mul42949673_64(i64 %a) {
257 ; MIPS32-LABEL: mul42949673_64:
258 ; MIPS32: # %bb.0: # %entry
259 ; MIPS32-NEXT: addiu $sp, $sp, -8
260 ; MIPS32-NEXT: .cfi_def_cfa_offset 8
261 ; MIPS32-NEXT: sw $16, 4($sp) # 4-byte Folded Spill
262 ; MIPS32-NEXT: .cfi_offset 16, -4
263 ; MIPS32-NEXT: sll $1, $4, 3
264 ; MIPS32-NEXT: addu $2, $1, $4
265 ; MIPS32-NEXT: sltu $1, $2, $1
266 ; MIPS32-NEXT: srl $3, $4, 29
267 ; MIPS32-NEXT: sll $6, $5, 3
268 ; MIPS32-NEXT: or $3, $6, $3
269 ; MIPS32-NEXT: addu $3, $3, $5
270 ; MIPS32-NEXT: addu $1, $3, $1
271 ; MIPS32-NEXT: srl $3, $4, 27
272 ; MIPS32-NEXT: sll $6, $5, 5
273 ; MIPS32-NEXT: or $3, $6, $3
274 ; MIPS32-NEXT: addu $1, $3, $1
275 ; MIPS32-NEXT: sll $3, $4, 5
276 ; MIPS32-NEXT: addu $2, $3, $2
277 ; MIPS32-NEXT: sll $6, $4, 10
278 ; MIPS32-NEXT: subu $7, $6, $2
279 ; MIPS32-NEXT: sltu $3, $2, $3
280 ; MIPS32-NEXT: sll $8, $4, 13
281 ; MIPS32-NEXT: addu $1, $1, $3
282 ; MIPS32-NEXT: addu $3, $8, $7
283 ; MIPS32-NEXT: sll $7, $4, 15
284 ; MIPS32-NEXT: addu $9, $7, $3
285 ; MIPS32-NEXT: srl $10, $4, 22
286 ; MIPS32-NEXT: sll $11, $5, 10
287 ; MIPS32-NEXT: or $10, $11, $10
288 ; MIPS32-NEXT: sll $11, $4, 20
289 ; MIPS32-NEXT: subu $1, $10, $1
290 ; MIPS32-NEXT: subu $10, $11, $9
291 ; MIPS32-NEXT: sltu $2, $6, $2
292 ; MIPS32-NEXT: srl $6, $4, 17
293 ; MIPS32-NEXT: sll $12, $5, 15
294 ; MIPS32-NEXT: srl $13, $4, 12
295 ; MIPS32-NEXT: sll $14, $5, 20
296 ; MIPS32-NEXT: srl $15, $4, 9
297 ; MIPS32-NEXT: sll $24, $5, 23
298 ; MIPS32-NEXT: sll $25, $4, 23
299 ; MIPS32-NEXT: srl $gp, $4, 7
300 ; MIPS32-NEXT: sll $16, $5, 25
301 ; MIPS32-NEXT: or $gp, $16, $gp
302 ; MIPS32-NEXT: sll $16, $4, 25
303 ; MIPS32-NEXT: subu $1, $1, $2
304 ; MIPS32-NEXT: addu $10, $25, $10
305 ; MIPS32-NEXT: or $2, $24, $15
306 ; MIPS32-NEXT: or $13, $14, $13
307 ; MIPS32-NEXT: or $6, $12, $6
308 ; MIPS32-NEXT: srl $4, $4, 19
309 ; MIPS32-NEXT: sll $5, $5, 13
310 ; MIPS32-NEXT: or $4, $5, $4
311 ; MIPS32-NEXT: addu $1, $4, $1
312 ; MIPS32-NEXT: sltu $3, $3, $8
313 ; MIPS32-NEXT: addu $1, $1, $3
314 ; MIPS32-NEXT: addu $1, $6, $1
315 ; MIPS32-NEXT: sltu $3, $9, $7
316 ; MIPS32-NEXT: addu $1, $1, $3
317 ; MIPS32-NEXT: subu $1, $13, $1
318 ; MIPS32-NEXT: sltu $3, $11, $9
319 ; MIPS32-NEXT: subu $1, $1, $3
320 ; MIPS32-NEXT: addu $1, $2, $1
321 ; MIPS32-NEXT: addu $2, $16, $10
322 ; MIPS32-NEXT: sltu $3, $10, $25
323 ; MIPS32-NEXT: addu $1, $1, $3
324 ; MIPS32-NEXT: sltu $3, $2, $16
325 ; MIPS32-NEXT: addu $1, $gp, $1
326 ; MIPS32-NEXT: addu $3, $1, $3
327 ; MIPS32-NEXT: lw $16, 4($sp) # 4-byte Folded Reload
328 ; MIPS32-NEXT: jr $ra
329 ; MIPS32-NEXT: addiu $sp, $sp, 8
330 ;
331 ; MIPS64-LABEL: mul42949673_64:
332 ; MIPS64: # %bb.0: # %entry
333 ; MIPS64-NEXT: dsll $1, $4, 3
334 ; MIPS64-NEXT: daddu $1, $1, $4
335 ; MIPS64-NEXT: dsll $2, $4, 5
336 ; MIPS64-NEXT: daddu $1, $2, $1
337 ; MIPS64-NEXT: dsll $2, $4, 10
338 ; MIPS64-NEXT: dsubu $1, $2, $1
339 ; MIPS64-NEXT: dsll $2, $4, 13
340 ; MIPS64-NEXT: daddu $1, $2, $1
341 ; MIPS64-NEXT: dsll $2, $4, 15
342 ; MIPS64-NEXT: daddu $1, $2, $1
343 ; MIPS64-NEXT: dsll $2, $4, 20
344 ; MIPS64-NEXT: dsubu $1, $2, $1
345 ; MIPS64-NEXT: dsll $2, $4, 25
346 ; MIPS64-NEXT: dsll $3, $4, 23
347 ; MIPS64-NEXT: daddu $1, $3, $1
348 ; MIPS64-NEXT: jr $ra
349 ; MIPS64-NEXT: daddu $2, $2, $1
350 entry:
351 %b = mul i64 %a, 42949673
352 ret i64 %b
353 }
354
355 define i32 @mul22224078_32(i32 %a) {
356 ; MIPS32-LABEL: mul22224078_32:
357 ; MIPS32: # %bb.0: # %entry
358 ; MIPS32-NEXT: sll $1, $4, 1
359 ; MIPS32-NEXT: sll $2, $4, 4
360 ; MIPS32-NEXT: subu $1, $2, $1
361 ; MIPS32-NEXT: sll $2, $4, 6
362 ; MIPS32-NEXT: subu $1, $2, $1
363 ; MIPS32-NEXT: sll $2, $4, 8
364 ; MIPS32-NEXT: subu $1, $2, $1
365 ; MIPS32-NEXT: sll $2, $4, 10
366 ; MIPS32-NEXT: subu $1, $2, $1
367 ; MIPS32-NEXT: sll $2, $4, 13
368 ; MIPS32-NEXT: subu $1, $2, $1
369 ; MIPS32-NEXT: sll $2, $4, 16
370 ; MIPS32-NEXT: subu $1, $2, $1
371 ; MIPS32-NEXT: sll $2, $4, 24
372 ; MIPS32-NEXT: sll $3, $4, 22
373 ; MIPS32-NEXT: sll $5, $4, 20
374 ; MIPS32-NEXT: sll $4, $4, 18
375 ; MIPS32-NEXT: subu $1, $4, $1
376 ; MIPS32-NEXT: addu $1, $5, $1
377 ; MIPS32-NEXT: addu $1, $3, $1
378 ; MIPS32-NEXT: jr $ra
379 ; MIPS32-NEXT: addu $2, $2, $1
380 ;
381 ; MIPS64-LABEL: mul22224078_32:
382 ; MIPS64: # %bb.0: # %entry
383 ; MIPS64-NEXT: sll $1, $4, 0
384 ; MIPS64-NEXT: sll $2, $1, 1
385 ; MIPS64-NEXT: sll $3, $1, 4
386 ; MIPS64-NEXT: subu $2, $3, $2
387 ; MIPS64-NEXT: sll $3, $1, 6
388 ; MIPS64-NEXT: subu $2, $3, $2
389 ; MIPS64-NEXT: sll $3, $1, 8
390 ; MIPS64-NEXT: subu $2, $3, $2
391 ; MIPS64-NEXT: sll $3, $1, 10
392 ; MIPS64-NEXT: subu $2, $3, $2
393 ; MIPS64-NEXT: sll $3, $1, 13
394 ; MIPS64-NEXT: subu $2, $3, $2
395 ; MIPS64-NEXT: sll $3, $1, 16
396 ; MIPS64-NEXT: subu $2, $3, $2
397 ; MIPS64-NEXT: sll $3, $1, 24
398 ; MIPS64-NEXT: sll $4, $1, 22
399 ; MIPS64-NEXT: sll $5, $1, 20
400 ; MIPS64-NEXT: sll $1, $1, 18
401 ; MIPS64-NEXT: subu $1, $1, $2
402 ; MIPS64-NEXT: addu $1, $5, $1
403 ; MIPS64-NEXT: addu $1, $4, $1
404 ; MIPS64-NEXT: jr $ra
405 ; MIPS64-NEXT: addu $2, $3, $1
406 entry:
407 %b = mul i32 %a, 22224078
408 ret i32 %b
409 }
410
411 define i64 @mul22224078_64(i64 %a) {
412 ; MIPS32-LABEL: mul22224078_64:
413 ; MIPS32: # %bb.0: # %entry
414 ; MIPS32-NEXT: addiu $sp, $sp, -32
415 ; MIPS32-NEXT: .cfi_def_cfa_offset 32
416 ; MIPS32-NEXT: sw $22, 28($sp) # 4-byte Folded Spill
417 ; MIPS32-NEXT: sw $21, 24($sp) # 4-byte Folded Spill
418 ; MIPS32-NEXT: sw $20, 20($sp) # 4-byte Folded Spill
419 ; MIPS32-NEXT: sw $19, 16($sp) # 4-byte Folded Spill
420 ; MIPS32-NEXT: sw $18, 12($sp) # 4-byte Folded Spill
421 ; MIPS32-NEXT: sw $17, 8($sp) # 4-byte Folded Spill
422 ; MIPS32-NEXT: sw $16, 4($sp) # 4-byte Folded Spill
423 ; MIPS32-NEXT: .cfi_offset 22, -4
424 ; MIPS32-NEXT: .cfi_offset 21, -8
425 ; MIPS32-NEXT: .cfi_offset 20, -12
426 ; MIPS32-NEXT: .cfi_offset 19, -16
427 ; MIPS32-NEXT: .cfi_offset 18, -20
428 ; MIPS32-NEXT: .cfi_offset 17, -24
429 ; MIPS32-NEXT: .cfi_offset 16, -28
430 ; MIPS32-NEXT: srl $1, $4, 31
431 ; MIPS32-NEXT: sll $2, $5, 1
432 ; MIPS32-NEXT: or $1, $2, $1
433 ; MIPS32-NEXT: srl $2, $4, 28
434 ; MIPS32-NEXT: sll $3, $5, 4
435 ; MIPS32-NEXT: or $2, $3, $2
436 ; MIPS32-NEXT: subu $1, $2, $1
437 ; MIPS32-NEXT: sll $2, $4, 1
438 ; MIPS32-NEXT: sll $3, $4, 4
439 ; MIPS32-NEXT: sltu $6, $3, $2
440 ; MIPS32-NEXT: subu $1, $1, $6
441 ; MIPS32-NEXT: subu $2, $3, $2
442 ; MIPS32-NEXT: sll $3, $4, 6
443 ; MIPS32-NEXT: subu $6, $3, $2
444 ; MIPS32-NEXT: srl $7, $4, 26
445 ; MIPS32-NEXT: sll $8, $5, 6
446 ; MIPS32-NEXT: or $7, $8, $7
447 ; MIPS32-NEXT: sll $8, $4, 8
448 ; MIPS32-NEXT: subu $1, $7, $1
449 ; MIPS32-NEXT: subu $7, $8, $6
450 ; MIPS32-NEXT: sll $9, $4, 10
451 ; MIPS32-NEXT: subu $10, $9, $7
452 ; MIPS32-NEXT: sltu $2, $3, $2
453 ; MIPS32-NEXT: sll $3, $4, 13
454 ; MIPS32-NEXT: srl $11, $4, 24
455 ; MIPS32-NEXT: sll $12, $5, 8
456 ; MIPS32-NEXT: subu $1, $1, $2
457 ; MIPS32-NEXT: or $2, $12, $11
458 ; MIPS32-NEXT: subu $11, $3, $10
459 ; MIPS32-NEXT: srl $12, $4, 22
460 ; MIPS32-NEXT: sll $13, $5, 10
461 ; MIPS32-NEXT: sll $14, $4, 16
462 ; MIPS32-NEXT: subu $15, $14, $11
463 ; MIPS32-NEXT: srl $24, $4, 14
464 ; MIPS32-NEXT: srl $25, $4, 12
465 ; MIPS32-NEXT: srl $gp, $4, 10
466 ; MIPS32-NEXT: srl $16, $4, 8
467 ; MIPS32-NEXT: subu $1, $2, $1
468 ; MIPS32-NEXT: or $2, $13, $12
469 ; MIPS32-NEXT: sltu $6, $8, $6
470 ; MIPS32-NEXT: srl $8, $4, 19
471 ; MIPS32-NEXT: sll $12, $5, 13
472 ; MIPS32-NEXT: srl $13, $4, 16
473 ; MIPS32-NEXT: sll $17, $5, 16
474 ; MIPS32-NEXT: sll $18, $5, 18
475 ; MIPS32-NEXT: sll $19, $5, 20
476 ; MIPS32-NEXT: sll $20, $5, 22
477 ; MIPS32-NEXT: sll $5, $5, 24
478 ; MIPS32-NEXT: sll $21, $4, 18
479 ; MIPS32-NEXT: subu $22, $21, $15
480 ; MIPS32-NEXT: or $5, $5, $16
481 ; MIPS32-NEXT: or $gp, $20, $gp
482 ; MIPS32-NEXT: or $25, $19, $25
483 ; MIPS32-NEXT: or $24, $18, $24
484 ; MIPS32-NEXT: or $13, $17, $13
485 ; MIPS32-NEXT: or $8, $12, $8
486 ; MIPS32-NEXT: sll $12, $4, 24
487 ; MIPS32-NEXT: sll $16, $4, 22
488 ; MIPS32-NEXT: sll $4, $4, 20
489 ; MIPS32-NEXT: subu $1, $1, $6
490 ; MIPS32-NEXT: subu $1, $2, $1
491 ; MIPS32-NEXT: sltu $2, $9, $7
492 ; MIPS32-NEXT: subu $1, $1, $2
493 ; MIPS32-NEXT: subu $1, $8, $1
494 ; MIPS32-NEXT: sltu $2, $3, $10
495 ; MIPS32-NEXT: subu $1, $1, $2
496 ; MIPS32-NEXT: subu $1, $13, $1
497 ; MIPS32-NEXT: sltu $2, $14, $11
498 ; MIPS32-NEXT: subu $1, $1, $2
499 ; MIPS32-NEXT: subu $1, $24, $1
500 ; MIPS32-NEXT: addu $3, $4, $22
501 ; MIPS32-NEXT: sltu $2, $21, $15
502 ; MIPS32-NEXT: subu $1, $1, $2
503 ; MIPS32-NEXT: addu $6, $16, $3
504 ; MIPS32-NEXT: addu $1, $25, $1
505 ; MIPS32-NEXT: addu $2, $12, $6
506 ; MIPS32-NEXT: sltu $7, $2, $12
507 ; MIPS32-NEXT: sltu $6, $6, $16
508 ; MIPS32-NEXT: sltu $3, $3, $4
509 ; MIPS32-NEXT: addu $1, $1, $3
510 ; MIPS32-NEXT: addu $1, $gp, $1
511 ; MIPS32-NEXT: addu $1, $1, $6
512 ; MIPS32-NEXT: addu $1, $5, $1
513 ; MIPS32-NEXT: addu $3, $1, $7
514 ; MIPS32-NEXT: lw $16, 4($sp) # 4-byte Folded Reload
515 ; MIPS32-NEXT: lw $17, 8($sp) # 4-byte Folded Reload
516 ; MIPS32-NEXT: lw $18, 12($sp) # 4-byte Folded Reload
517 ; MIPS32-NEXT: lw $19, 16($sp) # 4-byte Folded Reload
518 ; MIPS32-NEXT: lw $20, 20($sp) # 4-byte Folded Reload
519 ; MIPS32-NEXT: lw $21, 24($sp) # 4-byte Folded Reload
520 ; MIPS32-NEXT: lw $22, 28($sp) # 4-byte Folded Reload
521 ; MIPS32-NEXT: jr $ra
522 ; MIPS32-NEXT: addiu $sp, $sp, 32
523 ;
524 ; MIPS64-LABEL: mul22224078_64:
525 ; MIPS64: # %bb.0: # %entry
526 ; MIPS64-NEXT: dsll $1, $4, 1
527 ; MIPS64-NEXT: dsll $2, $4, 4
528 ; MIPS64-NEXT: dsubu $1, $2, $1
529 ; MIPS64-NEXT: dsll $2, $4, 6
530 ; MIPS64-NEXT: dsubu $1, $2, $1
531 ; MIPS64-NEXT: dsll $2, $4, 8
532 ; MIPS64-NEXT: dsubu $1, $2, $1
533 ; MIPS64-NEXT: dsll $2, $4, 10
534 ; MIPS64-NEXT: dsubu $1, $2, $1
535 ; MIPS64-NEXT: dsll $2, $4, 13
536 ; MIPS64-NEXT: dsubu $1, $2, $1
537 ; MIPS64-NEXT: dsll $2, $4, 16
538 ; MIPS64-NEXT: dsubu $1, $2, $1
539 ; MIPS64-NEXT: dsll $2, $4, 24
540 ; MIPS64-NEXT: dsll $3, $4, 22
541 ; MIPS64-NEXT: dsll $5, $4, 20
542 ; MIPS64-NEXT: dsll $4, $4, 18
543 ; MIPS64-NEXT: dsubu $1, $4, $1
544 ; MIPS64-NEXT: daddu $1, $5, $1
545 ; MIPS64-NEXT: daddu $1, $3, $1
546 ; MIPS64-NEXT: jr $ra
547 ; MIPS64-NEXT: daddu $2, $2, $1
548 entry:
549 %b = mul i64 %a, 22224078
550 ret i64 %b
551 }
552
553 define i32 @mul22245375_32(i32 %a) {
554 ; MIPS32-LABEL: mul22245375_32:
555 ; MIPS32: # %bb.0: # %entry
556 ; MIPS32-NEXT: sll $1, $4, 12
557 ; MIPS32-NEXT: addu $1, $1, $4
558 ; MIPS32-NEXT: sll $2, $4, 15
559 ; MIPS32-NEXT: addu $1, $2, $1
560 ; MIPS32-NEXT: sll $2, $4, 18
561 ; MIPS32-NEXT: subu $1, $2, $1
562 ; MIPS32-NEXT: sll $2, $4, 20
563 ; MIPS32-NEXT: addu $1, $2, $1
564 ; MIPS32-NEXT: sll $2, $4, 22
565 ; MIPS32-NEXT: addu $1, $2, $1
566 ; MIPS32-NEXT: sll $2, $4, 24
567 ; MIPS32-NEXT: jr $ra
568 ; MIPS32-NEXT: addu $2, $2, $1
569 ;
570 ; MIPS64-LABEL: mul22245375_32:
571 ; MIPS64: # %bb.0: # %entry
572 ; MIPS64-NEXT: sll $1, $4, 0
573 ; MIPS64-NEXT: sll $2, $1, 12
574 ; MIPS64-NEXT: addu $2, $2, $1
575 ; MIPS64-NEXT: sll $3, $1, 15
576 ; MIPS64-NEXT: addu $2, $3, $2
577 ; MIPS64-NEXT: sll $3, $1, 18
578 ; MIPS64-NEXT: subu $2, $3, $2
579 ; MIPS64-NEXT: sll $3, $1, 20
580 ; MIPS64-NEXT: addu $2, $3, $2
581 ; MIPS64-NEXT: sll $3, $1, 22
582 ; MIPS64-NEXT: addu $2, $3, $2
583 ; MIPS64-NEXT: sll $1, $1, 24
584 ; MIPS64-NEXT: jr $ra
585 ; MIPS64-NEXT: addu $2, $1, $2
586 entry:
587 %b = mul i32 %a, 22245375
588 ret i32 %b
589 }
590
591 define i64 @mul22245375_64(i64 %a) {
592 ; MIPS32-LABEL: mul22245375_64:
593 ; MIPS32: # %bb.0: # %entry
594 ; MIPS32-NEXT: sll $1, $4, 12
595 ; MIPS32-NEXT: addu $2, $1, $4
596 ; MIPS32-NEXT: sltu $1, $2, $1
597 ; MIPS32-NEXT: srl $3, $4, 20
598 ; MIPS32-NEXT: sll $6, $5, 12
599 ; MIPS32-NEXT: or $3, $6, $3
600 ; MIPS32-NEXT: addu $3, $3, $5
601 ; MIPS32-NEXT: addu $1, $3, $1
602 ; MIPS32-NEXT: srl $3, $4, 17
603 ; MIPS32-NEXT: sll $6, $5, 15
604 ; MIPS32-NEXT: or $3, $6, $3
605 ; MIPS32-NEXT: addu $1, $3, $1
606 ; MIPS32-NEXT: sll $3, $4, 15
607 ; MIPS32-NEXT: addu $2, $3, $2
608 ; MIPS32-NEXT: sltu $3, $2, $3
609 ; MIPS32-NEXT: addu $1, $1, $3
610 ; MIPS32-NEXT: srl $3, $4, 14
611 ; MIPS32-NEXT: sll $6, $5, 18
612 ; MIPS32-NEXT: or $3, $6, $3
613 ; MIPS32-NEXT: srl $6, $4, 12
614 ; MIPS32-NEXT: sll $7, $5, 20
615 ; MIPS32-NEXT: subu $1, $3, $1
616 ; MIPS32-NEXT: or $3, $7, $6
617 ; MIPS32-NEXT: sll $6, $4, 18
618 ; MIPS32-NEXT: srl $7, $4, 10
619 ; MIPS32-NEXT: sll $8, $5, 22
620 ; MIPS32-NEXT: srl $9, $4, 8
621 ; MIPS32-NEXT: sll $5, $5, 24
622 ; MIPS32-NEXT: or $5, $5, $9
623 ; MIPS32-NEXT: or $7, $8, $7
624 ; MIPS32-NEXT: sltu $8, $6, $2
625 ; MIPS32-NEXT: sll $9, $4, 24
626 ; MIPS32-NEXT: sll $10, $4, 22
627 ; MIPS32-NEXT: sll $4, $4, 20
628 ; MIPS32-NEXT: subu $1, $1, $8
629 ; MIPS32-NEXT: addu $1, $3, $1
630 ; MIPS32-NEXT: subu $2, $6, $2
631 ; MIPS32-NEXT: addu $2, $4, $2
632 ; MIPS32-NEXT: sltu $3, $2, $4
633 ; MIPS32-NEXT: addu $1, $1, $3
634 ; MIPS32-NEXT: addu $1, $7, $1
635 ; MIPS32-NEXT: addu $2, $10, $2
636 ; MIPS32-NEXT: sltu $3, $2, $10
637 ; MIPS32-NEXT: addu $1, $1, $3
638 ; MIPS32-NEXT: addu $1, $5, $1
639 ; MIPS32-NEXT: addu $2, $9, $2
640 ; MIPS32-NEXT: sltu $3, $2, $9
641 ; MIPS32-NEXT: jr $ra
642 ; MIPS32-NEXT: addu $3, $1, $3
643 ;
644 ; MIPS64-LABEL: mul22245375_64:
645 ; MIPS64: # %bb.0: # %entry
646 ; MIPS64-NEXT: dsll $1, $4, 12
647 ; MIPS64-NEXT: daddu $1, $1, $4
648 ; MIPS64-NEXT: dsll $2, $4, 15
649 ; MIPS64-NEXT: daddu $1, $2, $1
650 ; MIPS64-NEXT: dsll $2, $4, 18
651 ; MIPS64-NEXT: dsubu $1, $2, $1
652 ; MIPS64-NEXT: dsll $2, $4, 20
653 ; MIPS64-NEXT: daddu $1, $2, $1
654 ; MIPS64-NEXT: dsll $2, $4, 22
655 ; MIPS64-NEXT: daddu $1, $2, $1
656 ; MIPS64-NEXT: dsll $2, $4, 24
657 ; MIPS64-NEXT: jr $ra
658 ; MIPS64-NEXT: daddu $2, $2, $1
659 entry:
660 %b = mul i64 %a, 22245375
661 ret i64 %b
662 }
663
664 define i32 @mul25165824_32(i32 %a) {
665 ; MIPS32-LABEL: mul25165824_32:
666 ; MIPS32: # %bb.0: # %entry
667 ; MIPS32-NEXT: sll $1, $4, 12
668 ; MIPS32-NEXT: addu $1, $1, $4
669 ; MIPS32-NEXT: sll $2, $4, 15
670 ; MIPS32-NEXT: addu $1, $2, $1
671 ; MIPS32-NEXT: sll $2, $4, 18
672 ; MIPS32-NEXT: subu $1, $2, $1
673 ; MIPS32-NEXT: sll $2, $4, 20
674 ; MIPS32-NEXT: addu $1, $2, $1
675 ; MIPS32-NEXT: sll $2, $4, 22
676 ; MIPS32-NEXT: addu $1, $2, $1
677 ; MIPS32-NEXT: sll $2, $4, 24
678 ; MIPS32-NEXT: jr $ra
679 ; MIPS32-NEXT: addu $2, $2, $1
680 ;
681 ; MIPS64-LABEL: mul25165824_32:
682 ; MIPS64: # %bb.0: # %entry
683 ; MIPS64-NEXT: sll $1, $4, 0
684 ; MIPS64-NEXT: sll $2, $1, 12
685 ; MIPS64-NEXT: addu $2, $2, $1
686 ; MIPS64-NEXT: sll $3, $1, 15
687 ; MIPS64-NEXT: addu $2, $3, $2
688 ; MIPS64-NEXT: sll $3, $1, 18
689 ; MIPS64-NEXT: subu $2, $3, $2
690 ; MIPS64-NEXT: sll $3, $1, 20
691 ; MIPS64-NEXT: addu $2, $3, $2
692 ; MIPS64-NEXT: sll $3, $1, 22
693 ; MIPS64-NEXT: addu $2, $3, $2
694 ; MIPS64-NEXT: sll $1, $1, 24
695 ; MIPS64-NEXT: jr $ra
696 ; MIPS64-NEXT: addu $2, $1, $2
697 entry:
698 %b = mul i32 %a, 22245375
699 ret i32 %b
700 }
701
702 define i64 @mul25165824_64(i64 %a) {
703 ; MIPS32-LABEL: mul25165824_64:
704 ; MIPS32: # %bb.0: # %entry
705 ; MIPS32-NEXT: srl $1, $4, 9
706 ; MIPS32-NEXT: sll $2, $5, 23
707 ; MIPS32-NEXT: or $1, $2, $1
708 ; MIPS32-NEXT: srl $2, $4, 8
709 ; MIPS32-NEXT: sll $3, $5, 24
710 ; MIPS32-NEXT: or $2, $3, $2
711 ; MIPS32-NEXT: addu $1, $2, $1
712 ; MIPS32-NEXT: sll $2, $4, 23
713 ; MIPS32-NEXT: sll $3, $4, 24
714 ; MIPS32-NEXT: addu $2, $3, $2
715 ; MIPS32-NEXT: sltu $3, $2, $3
716 ; MIPS32-NEXT: jr $ra
717 ; MIPS32-NEXT: addu $3, $1, $3
718 ;
719 ; MIPS64-LABEL: mul25165824_64:
720 ; MIPS64: # %bb.0: # %entry
721 ; MIPS64-NEXT: dsll $1, $4, 23
722 ; MIPS64-NEXT: dsll $2, $4, 24
723 ; MIPS64-NEXT: jr $ra
724 ; MIPS64-NEXT: daddu $2, $2, $1
725 entry:
726 %b = mul i64 %a, 25165824
727 ret i64 %b
728 }
729
730 define i32 @mul33554432_32(i32 %a) {
731 ; MIPS32-LABEL: mul33554432_32:
732 ; MIPS32: # %bb.0: # %entry
733 ; MIPS32-NEXT: sll $1, $4, 12
734 ; MIPS32-NEXT: addu $1, $1, $4
735 ; MIPS32-NEXT: sll $2, $4, 15
736 ; MIPS32-NEXT: addu $1, $2, $1
737 ; MIPS32-NEXT: sll $2, $4, 18
738 ; MIPS32-NEXT: subu $1, $2, $1
739 ; MIPS32-NEXT: sll $2, $4, 20
740 ; MIPS32-NEXT: addu $1, $2, $1
741 ; MIPS32-NEXT: sll $2, $4, 22
742 ; MIPS32-NEXT: addu $1, $2, $1
743 ; MIPS32-NEXT: sll $2, $4, 24
744 ; MIPS32-NEXT: jr $ra
745 ; MIPS32-NEXT: addu $2, $2, $1
746 ;
747 ; MIPS64-LABEL: mul33554432_32:
748 ; MIPS64: # %bb.0: # %entry
749 ; MIPS64-NEXT: sll $1, $4, 0
750 ; MIPS64-NEXT: sll $2, $1, 12
751 ; MIPS64-NEXT: addu $2, $2, $1
752 ; MIPS64-NEXT: sll $3, $1, 15
753 ; MIPS64-NEXT: addu $2, $3, $2
754 ; MIPS64-NEXT: sll $3, $1, 18
755 ; MIPS64-NEXT: subu $2, $3, $2
756 ; MIPS64-NEXT: sll $3, $1, 20
757 ; MIPS64-NEXT: addu $2, $3, $2
758 ; MIPS64-NEXT: sll $3, $1, 22
759 ; MIPS64-NEXT: addu $2, $3, $2
760 ; MIPS64-NEXT: sll $1, $1, 24
761 ; MIPS64-NEXT: jr $ra
762 ; MIPS64-NEXT: addu $2, $1, $2
763 entry:
764 %b = mul i32 %a, 22245375
765 ret i32 %b
766 }
767
768 define i64 @mul33554432_64(i64 %a) {
769 ; MIPS32-LABEL: mul33554432_64:
770 ; MIPS32: # %bb.0: # %entry
771 ; MIPS32-NEXT: srl $1, $4, 7
772 ; MIPS32-NEXT: sll $2, $5, 25
773 ; MIPS32-NEXT: or $3, $2, $1
774 ; MIPS32-NEXT: jr $ra
775 ; MIPS32-NEXT: sll $2, $4, 25
776 ;
777 ; MIPS64-LABEL: mul33554432_64:
778 ; MIPS64: # %bb.0: # %entry
779 ; MIPS64-NEXT: jr $ra
780 ; MIPS64-NEXT: dsll $2, $4, 25
781 entry:
782 %b = mul i64 %a, 33554432
783 ret i64 %b
784 }