llvm.org GIT mirror llvm / cf2ab76
Update to more CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change. All changes were made by the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" grep -q "^; *RUN: *llc.*debug" $NAME && continue grep -q "^; *RUN:.*llvm-objdump" $NAME && continue grep -q "^; *RUN: *opt.*" $NAME && continue TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\([A-Za-z0-9_-]*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC[:]* *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME done This script catches a superset of the cases caught by the script associated with commit r186280. It initially found some false positives due to unusual constructs in a minority of tests; all such cases were disambiguated first in commit r186621. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186624 91177308-0d34-0410-b5e6-96231b3b80d8 Stephen Lin 6 years ago
41 changed file(s) with 118 addition(s) and 118 deletion(s). Raw diff Collapse all Expand all
0 ; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s
11 ; rdar://12201387
22
3 ;CHECK: select_s_v_v
3 ;CHECK-LABEL: select_s_v_v:
44 ;CHECK: it ne
55 ;CHECK-NEXT: vmovne.i32
66 ;CHECK: bx
0 ; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s
11
2 ;CHECK: foo
2 ;CHECK-LABEL: foo:
33 ;CHECK: adds
44 ;CHECK-NEXT: adc
55 ;CHECK-NEXT: bx
5959
6060 define i64 @f4(i64* %val) nounwind {
6161 entry:
62 ;CHECK: f4
62 ;CHECK-LABEL: f4:
6363 ;CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
6464 %0 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [$1]", "=&r,r,*Qo"(i64* %val, i64* %val) nounwind
6565 ret i64 %0
186186 ; Floating-point comparisons against zero produce results with integer
187187 ; elements, not floating-point elements.
188188 define void @test_vclez_fp() nounwind optsize {
189 ;CHECK: test_vclez_fp
189 ;CHECK-LABEL: test_vclez_fp:
190190 ;CHECK: vcle.f32
191191 entry:
192192 %0 = fcmp ole <4 x float> undef, zeroinitializer
262262 }
263263
264264 define <4 x i32> @tdupi(i32 %x, i32 %y) {
265 ;CHECK: tdupi
265 ;CHECK-LABEL: tdupi:
266266 ;CHECK: vdup.32
267267 %1 = insertelement <4 x i32> undef, i32 %x, i32 0
268268 %2 = insertelement <4 x i32> %1, i32 %x, i32 1
272272 }
273273
274274 define <4 x float> @tdupf(float %x, float %y) {
275 ;CHECK: tdupf
275 ;CHECK-LABEL: tdupf:
276276 ;CHECK: vdup.32
277277 %1 = insertelement <4 x float> undef, float %x, i32 0
278278 %2 = insertelement <4 x float> %1, float %x, i32 1
284284 ; This test checks that when splatting an element from a vector into another,
285285 ; the value isn't moved out to GPRs first.
286286 define <4 x i32> @tduplane(<4 x i32> %invec) {
287 ;CHECK: tduplane
287 ;CHECK-LABEL: tduplane:
288288 ;CHECK-NOT: vmov {{.*}}, d16[1]
289289 ;CHECK: vdup.32 {{.*}}, d16[1]
290290 %in = extractelement <4 x i32> %invec, i32 1
501501 ; we don't currently have a QQQQ_VFP2 super-regclass. (The "0" for the low
502502 ; part of %ins67 is supposed to be loaded by a VLDRS instruction in this test.)
503503 define <8 x i16> @test_qqqq_regsequence_subreg([6 x i64] %b) nounwind {
504 ;CHECK: test_qqqq_regsequence_subreg
504 ;CHECK-LABEL: test_qqqq_regsequence_subreg:
505505 ;CHECK: vld3.16
506506 %tmp63 = extractvalue [6 x i64] %b, 5
507507 %tmp64 = zext i64 %tmp63 to i128
385385 ; rdar://10723651
386386 define void @any_extend(<4 x i1> %x, <4 x i32> %y) nounwind ssp {
387387 entry:
388 ;CHECK: any_extend
388 ;CHECK-LABEL: any_extend:
389389 ;CHECK: vmovl
390390 %and.i186 = zext <4 x i1> %x to <4 x i32>
391391 %add.i185 = sub <4 x i32> %and.i186, %y
110110 }
111111
112112 define i8* @vst2update(i8* %out, <4 x i16>* %B) nounwind {
113 ;CHECK: vst2update
113 ;CHECK-LABEL: vst2update:
114114 ;CHECK: vst2.16 {d16, d17}, [r0]!
115115 %tmp1 = load <4 x i16>* %B
116116 tail call void @llvm.arm.neon.vst2.v4i16(i8* %out, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 2)
119119 }
120120
121121 define i8* @vst2update2(i8 * %out, <4 x float> * %this) nounwind optsize ssp align 2 {
122 ;CHECK: vst2update2
122 ;CHECK-LABEL: vst2update2:
123123 ;CHECK: vst2.32 {d16, d17, d18, d19}, [r0]!
124124 %tmp1 = load <4 x float>* %this
125125 call void @llvm.arm.neon.vst2.v4f32(i8* %out, <4 x float> %tmp1, <4 x float> %tmp1, i32 4) nounwind
6262
6363 define i32 @test_select_int_fcc(float %f, i32 %a, i32 %b) nounwind readnone noinline {
6464 entry:
65 ;V8: test_select_int_fcc
65 ;V8-LABEL: test_select_int_fcc:
6666 ;V8: fcmps
6767 ;V8: {{fbe|fbne}}
68 ;V9: test_select_int_fcc
68 ;V9-LABEL: test_select_int_fcc:
6969 ;V9: fcmps
7070 ;V9-NOT: {{fbe|fbne}}
7171 ;V9: mov{{e|ne}} %fcc0
7777
7878 define float @test_select_fp_fcc(float %f, float %f1, float %f2) nounwind readnone noinline {
7979 entry:
80 ;V8: test_select_fp_fcc
80 ;V8-LABEL: test_select_fp_fcc:
8181 ;V8: fcmps
8282 ;V8: {{fbe|fbne}}
83 ;V9: test_select_fp_fcc
83 ;V9-LABEL: test_select_fp_fcc:
8484 ;V9: fcmps
8585 ;V9-NOT: {{fbe|fbne}}
8686 ;V9: fmovs{{e|ne}} %fcc0
9191
9292 define double @test_select_dfp_fcc(double %f, double %f1, double %f2) nounwind readnone noinline {
9393 entry:
94 ;V8: test_select_dfp_fcc
94 ;V8-LABEL: test_select_dfp_fcc:
9595 ;V8: fcmpd
9696 ;V8: {{fbne|fbe}}
97 ;V9: test_select_dfp_fcc
97 ;V9-LABEL: test_select_dfp_fcc:
9898 ;V9: fcmpd
9999 ;V9-NOT: {{fbne|fbe}}
100100 ;V9: fmovd{{e|ne}} %fcc0
55
66 define i8* @frameaddr() nounwind readnone {
77 entry:
8 ;V8: frameaddr
8 ;V8-LABEL: frameaddr:
99 ;V8: save %sp, -96, %sp
1010 ;V8: jmp %i7+8
1111 ;V8: restore %g0, %fp, %o0
1212
13 ;V9: frameaddr
13 ;V9-LABEL: frameaddr:
1414 ;V9: save %sp, -96, %sp
1515 ;V9: jmp %i7+8
1616 ;V9: restore %g0, %fp, %o0
2020
2121 define i8* @frameaddr2() nounwind readnone {
2222 entry:
23 ;V8: frameaddr2
23 ;V8-LABEL: frameaddr2:
2424 ;V8: ta 3
2525 ;V8: ld [%fp+56], {{.+}}
2626 ;V8: ld [{{.+}}+56], {{.+}}
2727 ;V8: ld [{{.+}}+56], {{.+}}
2828
29 ;V9: frameaddr2
29 ;V9-LABEL: frameaddr2:
3030 ;V9: flushw
3131 ;V9: ld [%fp+56], {{.+}}
3232 ;V9: ld [{{.+}}+56], {{.+}}
4141
4242 define i8* @retaddr() nounwind readnone {
4343 entry:
44 ;V8: retaddr
44 ;V8-LABEL: retaddr:
4545 ;V8: or %g0, %o7, {{.+}}
4646
47 ;V9: retaddr
47 ;V9-LABEL: retaddr:
4848 ;V9: or %g0, %o7, {{.+}}
4949
5050 %0 = tail call i8* @llvm.returnaddress(i32 0)
5353
5454 define i8* @retaddr2() nounwind readnone {
5555 entry:
56 ;V8: retaddr2
56 ;V8-LABEL: retaddr2:
5757 ;V8: ta 3
5858 ;V8: ld [%fp+56], {{.+}}
5959 ;V8: ld [{{.+}}+56], {{.+}}
6060 ;V8: ld [{{.+}}+60], {{.+}}
6161
62 ;V9: retaddr2
62 ;V9-LABEL: retaddr2:
6363 ;V9: flushw
6464 ;V9: ld [%fp+56], {{.+}}
6565 ;V9: ld [{{.+}}+56], {{.+}}
6666 ;V9: ld [{{.+}}+60], {{.+}}
6767
68 ;V8LEAF: retaddr2
68 ;V8LEAF-LABEL: retaddr2:
6969 ;V8LEAF: ta 3
7070 ;V8LEAF: ld [%fp+56], %[[R:[goli][0-7]]]
7171 ;V8LEAF: ld [%[[R]]+56], %[[R1:[goli][0-7]]]
7272 ;V8LEAF: ld [%[[R1]]+60], {{.+}}
7373
74 ;V9LEAF: retaddr2
74 ;V9LEAF-LABEL: retaddr2:
7575 ;V9LEAF: flushw
7676 ;V9LEAF: ld [%fp+56], %[[R:[goli][0-7]]]
7777 ;V9LEAF: ld [%[[R]]+56], %[[R1:[goli][0-7]]]
5353
5454 define i32 @test_inlineasm(i32 %a) nounwind {
5555 entry:
56 ;CHECK: test_inlineasm
56 ;CHECK-LABEL: test_inlineasm:
5757 ;CHECK: sethi
5858 ;CHECK: !NO_APP
5959 ;CHECK-NEXT: cmp
7979
8080 define i32 @test_implicit_def() nounwind {
8181 entry:
82 ;UNOPT: test_implicit_def
82 ;UNOPT-LABEL: test_implicit_def:
8383 ;UNOPT: call func
8484 ;UNOPT-NEXT: nop
8585 %0 = tail call i32 @func(i32* undef) nounwind
8888
8989 define i32 @prevent_o7_in_call_delay_slot(i32 %i0) {
9090 entry:
91 ;CHECK: prevent_o7_in_call_delay_slot
91 ;CHECK-LABEL: prevent_o7_in_call_delay_slot:
9292 ;CHECK: add %i0, 2, %o5
9393 ;CHECK: add %i0, 3, %o7
9494 ;CHECK: add %o5, %o7, %o0
149149
150150 define i32 @restore_sethi(i32 %a) {
151151 entry:
152 ;CHECK: restore_sethi
152 ;CHECK-LABEL: restore_sethi:
153153 ;CHECK-NOT: sethi 3
154154 ;CHECK: restore %g0, 3072, %o0
155155 %0 = tail call i32 @bar(i32 %a) nounwind
160160
161161 define i32 @restore_sethi_3bit(i32 %a) {
162162 entry:
163 ;CHECK: restore_sethi_3bit
163 ;CHECK-LABEL: restore_sethi_3bit:
164164 ;CHECK: sethi 6
165165 ;CHECK-NOT: restore %g0, 6144, %o0
166166 %0 = tail call i32 @bar(i32 %a) nounwind
171171
172172 define i32 @restore_sethi_large(i32 %a) {
173173 entry:
174 ;CHECK: restore_sethi_large
174 ;CHECK-LABEL: restore_sethi_large:
175175 ;CHECK: sethi 4000, %i0
176176 ;CHECK: restore %g0, %g0, %g0
177177 %0 = tail call i32 @bar(i32 %a) nounwind
55
66 define i32 @test() nounwind {
77 entry:
8 ;CHECK: test
8 ;CHECK-LABEL: test:
99 ;CHECK: st
1010 ;CHECK: st
1111 ;CHECK: st
33
44 define weak void @make_foo(%struct.foo_t* noalias sret %agg.result, i32 %a, i32 %b, i32 %c) nounwind {
55 entry:
6 ;CHECK: make_foo
6 ;CHECK-LABEL: make_foo:
77 ;CHECK: ld [%sp+64], {{.+}}
88 ;CHECK: jmp %o7+12
99 %0 = getelementptr inbounds %struct.foo_t* %agg.result, i32 0, i32 0
1717
1818 define i32 @test() nounwind {
1919 entry:
20 ;CHECK: test
20 ;CHECK-LABEL: test:
2121 ;CHECK: st {{.+}}, [%sp+64]
2222 ;CHECK: call make_foo
2323 ;CHECK: unimp 12
258258 }
259259
260260 define i32 @f6(i32 %a) {
261 ;CHECK: f6
261 ;CHECK-LABEL: f6:
262262 ;CHECK: movw r0, #65535
263263 %tmp = add i32 0, 65535
264264 ret i32 %tmp
0 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 | FileCheck %s
11
22 ; Make sure that values of illegal types are not scalarized between basic blocks.
3 ;CHECK: test
3 ;CHECK-LABEL: test:
44 ;CHECK-NOT: pinsrw
55 ;CHECK-NOT: pextrb
66 ;CHECK: ret
0 ; RUN: llc < %s -march=x86 -mcpu=corei7 | FileCheck %s
11
2 ;CHECK: test
2 ;CHECK-LABEL: test:
33 ;CHECK-not: pshufd
44 ;CHECK: ret
55 define float @test(<4 x float>* %A) nounwind {
11
22 target triple = "x86_64-unknown-linux-gnu"
33
4 ;CHECK: ltstore
4 ;CHECK-LABEL: ltstore:
55 ;CHECK: movq
66 ;CHECK: movq
77 ;CHECK: ret
0 ; RUN: llc < %s -march=x86 -mcpu=corei7 | FileCheck %s
11
2 ;CHECK: addXX_test
2 ;CHECK-LABEL: addXX_test:
33 ;CHECK: padd
44 ;CHECK: ret
55
99 ret <16 x i8> %b
1010 }
1111
12 ;CHECK: instcombine_test
12 ;CHECK-LABEL: instcombine_test:
1313 ;CHECK: padd
1414 ;CHECK: ret
1515 define <16 x i8> @instcombine_test(<16 x i8> %a) {
44 ; 0x1 means that we only look at the first bit.
55
66 ;CHECK: 0x1
7 ;CHECK: ui_to_fp_conv
7 ;CHECK-LABEL: ui_to_fp_conv:
88 ;CHECK: ret
99 define void @ui_to_fp_conv(<8 x float> * nocapture %aFOO, <8 x float>* nocapture %RET) nounwind {
1010 allocas:
0 ; RUN: llc < %s -march=x86 -mcpu=corei7-avx -mattr=+avx -mtriple=i686-pc-win32 | FileCheck %s
11
2 ;CHECK: add18i16
2 ;CHECK-LABEL: add18i16:
33 define void @add18i16(<18 x i16>* nocapture sret %ret, <18 x i16>* %bp) nounwind {
44 ;CHECK: vmovaps
55 %b = load <18 x i16>* %bp, align 16
0 ; RUN: llc < %s -march=x86-64 -mcpu=corei7 -mtriple=x86_64-pc-win32 | FileCheck %s
11
2 ;CHECK: vcast
2 ;CHECK-LABEL: vcast:
33 define <2 x i32> @vcast(<2 x float> %a, <2 x float> %b) {
44 ;CHECK: pmovzxdq
55 ;CHECK: pmovzxdq
1212 }
1313
1414 ; Make sure that we store a 64bit value, even on 32bit systems.
15 ;CHECK: store_64
15 ;CHECK-LABEL: store_64:
1616 define void @store_64(<2 x i32>* %ptr) {
1717 BB:
1818 store <2 x i32> zeroinitializer, <2 x i32>* %ptr
2121 ;CHECK: ret
2222 }
2323
24 ;CHECK: load_64
24 ;CHECK-LABEL: load_64:
2525 define <2 x i32> @load_64(<2 x i32>* %ptr) {
2626 BB:
2727 %t = load <2 x i32>* %ptr
11
22 declare x86_fastcallcc i64 @barrier()
33
4 ;CHECK: bcast_fold
4 ;CHECK-LABEL: bcast_fold:
55 ;CHECK: vmov{{[au]}}ps %xmm{{[0-9]+}}, [[SPILLED:[^\)]+\)]]
66 ;CHECK: barrier
77 ;CHECK: vbroadcastss [[SPILLED]], %ymm0
22 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32"
33 target triple = "i686-pc-win32"
44
5 ;CHECK: bad_cast
5 ;CHECK-LABEL: bad_cast:
66 define void @bad_cast() {
77 entry:
88 %vext.i = shufflevector <2 x i64> undef, <2 x i64> undef, <3 x i32>
1313 }
1414
1515
16 ;CHECK: bad_insert
16 ;CHECK-LABEL: bad_insert:
1717 define void @bad_insert(i32 %t) {
1818 entry:
1919 ;CHECK: vpinsrd
146146 }
147147
148148
149 ;CHECK: merge_loads_i16
149 ;CHECK-LABEL: merge_loads_i16:
150150 ; load:
151151 ;CHECK: movw
152152 ; store:
180180 }
181181
182182 ; The loads and the stores are interleved. Can't merge them.
183 ;CHECK: no_merge_loads
183 ;CHECK-LABEL: no_merge_loads:
184184 ;CHECK: movb
185185 ;CHECK: movb
186186 ;CHECK: movb
214214 }
215215
216216
217 ;CHECK: merge_loads_integer
217 ;CHECK-LABEL: merge_loads_integer:
218218 ; load:
219219 ;CHECK: movq
220220 ; store:
248248 }
249249
250250
251 ;CHECK: merge_loads_vector
251 ;CHECK-LABEL: merge_loads_vector:
252252 ; load:
253253 ;CHECK: movups
254254 ; store:
289289 ret void
290290 }
291291
292 ;CHECK: merge_loads_no_align
292 ;CHECK-LABEL: merge_loads_no_align:
293293 ; load:
294294 ;CHECK: movl
295295 ;CHECK: movl
296296 }
297297
298298
299 ;YESCOLOR: multi_region_bb
300 ;NOCOLOR: multi_region_bb
299 ;YESCOLOR-LABEL: multi_region_bb:
300 ;NOCOLOR-LABEL: multi_region_bb:
301301 define void @multi_region_bb() nounwind ssp {
302302 entry:
303303 %A.i1 = alloca [100 x i32], align 4
352352
353353 ; Regression test for PR15707. %buf1 and %buf2 should not be merged
354354 ; in this test case.
355 ;YESCOLOR: myCall_pr15707
355 ;YESCOLOR-LABEL: myCall_pr15707:
356356 ;YESCOLOR: subq $200008, %rsp
357 ;NOCOLOR: myCall_pr15707
357 ;NOCOLOR-LABEL: myCall_pr15707:
358358 ;NOCOLOR: subq $200008, %rsp
359359 define void @myCall_pr15707() {
360360 %buf1 = alloca i8, i32 100000, align 16
373373
374374 ; Check that we don't assert and crash even when there are allocas
375375 ; outside the declared lifetime regions.
376 ;YESCOLOR: bad_range
377 ;NOCOLOR: bad_range
376 ;YESCOLOR-LABEL: bad_range:
377 ;NOCOLOR-LABEL: bad_range:
378378 define void @bad_range() nounwind ssp {
379379 entry:
380380 %A.i1 = alloca [100 x i32], align 4
399399
400400 ; Check that we don't assert and crash even when there are usages
401401 ; of allocas which do not read or write outside the declared lifetime regions.
402 ;YESCOLOR: shady_range
403 ;NOCOLOR: shady_range
402 ;YESCOLOR-LABEL: shady_range:
403 ;NOCOLOR-LABEL: shady_range:
404404
405405 %struct.Klass = type { i32, i32 }
406406
0 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx | FileCheck %s
11
2 ;CHECK: test
2 ;CHECK-LABEL: test:
33 ;CHECK: vaddps
44 ;CHECK: vmulps
55 ;CHECK: vsubps
77 %class.A = type { i32 (...)** }
88
99 define i32 @test1() #0 {
10 ;ATOM: test1
10 ;ATOM-LABEL: test1:
1111 entry:
1212 %call = tail call %class.A* @_Z3facv()
1313 %0 = bitcast %class.A* %call to void (%class.A*)***
2929 @p = external global void (i32)**
3030
3131 define i32 @test2() #0 {
32 ;ATOM: test2
32 ;ATOM-LABEL: test2:
3333 entry:
3434 %0 = load void (i32)*** @p, align 8
3535 %1 = load void (i32)** %0, align 8
11
22 ; AVX128 tests:
33
4 ;CHECK: vsel_float
4 ;CHECK-LABEL: vsel_float:
55 ;CHECK: vblendvps
66 ;CHECK: ret
77 define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
1010 }
1111
1212
13 ;CHECK: vsel_i32
13 ;CHECK-LABEL: vsel_i32:
1414 ;CHECK: vblendvps
1515 ;CHECK: ret
1616 define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {
1919 }
2020
2121
22 ;CHECK: vsel_double
22 ;CHECK-LABEL: vsel_double:
2323 ;CHECK: vblendvpd
2424 ;CHECK: ret
2525 define <2 x double> @vsel_double(<2 x double> %v1, <2 x double> %v2) {
2828 }
2929
3030
31 ;CHECK: vsel_i64
31 ;CHECK-LABEL: vsel_i64:
3232 ;CHECK: vblendvpd
3333 ;CHECK: ret
3434 define <2 x i64> @vsel_i64(<2 x i64> %v1, <2 x i64> %v2) {
3737 }
3838
3939
40 ;CHECK: vsel_i8
40 ;CHECK-LABEL: vsel_i8:
4141 ;CHECK: vpblendvb
4242 ;CHECK: ret
4343 define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
4949 ; AVX256 tests:
5050
5151
52 ;CHECK: vsel_float8
52 ;CHECK-LABEL: vsel_float8:
5353 ;CHECK: vblendvps
5454 ;CHECK: ret
5555 define <8 x float> @vsel_float8(<8 x float> %v1, <8 x float> %v2) {
5757 ret <8 x float> %vsel
5858 }
5959
60 ;CHECK: vsel_i328
60 ;CHECK-LABEL: vsel_i328:
6161 ;CHECK: vblendvps
6262 ;CHECK: ret
6363 define <8 x i32> @vsel_i328(<8 x i32> %v1, <8 x i32> %v2) {
6565 ret <8 x i32> %vsel
6666 }
6767
68 ;CHECK: vsel_double8
68 ;CHECK-LABEL: vsel_double8:
6969 ;CHECK: vblendvpd
7070 ;CHECK: ret
7171 define <8 x double> @vsel_double8(<8 x double> %v1, <8 x double> %v2) {
7373 ret <8 x double> %vsel
7474 }
7575
76 ;CHECK: vsel_i648
76 ;CHECK-LABEL: vsel_i648:
7777 ;CHECK: vblendvpd
7878 ;CHECK: ret
7979 define <8 x i64> @vsel_i648(<8 x i64> %v1, <8 x i64> %v2) {
219219 ret <16 x i16> %t
220220 }
221221
222 ;CHECK: test17
222 ;CHECK-LABEL: test17:
223223 ;CHECK-NOT: vinsertf128
224224 ;CHECK: ret
225225 define <8 x float> @test17(<4 x float> %y) {
0 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
11
22 define <8 x i32> @zext_8i16_to_8i32(<8 x i16> %A) nounwind uwtable readnone ssp {
3 ;CHECK: zext_8i16_to_8i32
3 ;CHECK-LABEL: zext_8i16_to_8i32:
44 ;CHECK: vpunpckhwd
55 ;CHECK: ret
66
99 }
1010
1111 define <4 x i64> @zext_4i32_to_4i64(<4 x i32> %A) nounwind uwtable readnone ssp {
12 ;CHECK: zext_4i32_to_4i64
12 ;CHECK-LABEL: zext_4i32_to_4i64:
1313 ;CHECK: vpunpckhdq
1414 ;CHECK: ret
1515
1818 }
1919
2020 define <8 x i32> @zext_8i8_to_8i32(<8 x i8> %z) {
21 ;CHECK: zext_8i8_to_8i32
21 ;CHECK-LABEL: zext_8i8_to_8i32:
2222 ;CHECK: vpunpckhwd
2323 ;CHECK: vpmovzxwd
2424 ;CHECK: vinsertf128
258258 ret <4 x double> %wide
259259 }
260260
261 ;CHECK: _inreg8xfloat
261 ;CHECK-LABEL: _inreg8xfloat:
262262 ;CHECK: vbroadcastss
263263 ;CHECK: ret
264264 define <8 x float> @_inreg8xfloat(<8 x float> %a) {
266266 ret <8 x float> %b
267267 }
268268
269 ;CHECK: _inreg4xfloat
269 ;CHECK-LABEL: _inreg4xfloat:
270270 ;CHECK: vbroadcastss
271271 ;CHECK: ret
272272 define <4 x float> @_inreg4xfloat(<4 x float> %a) {
274274 ret <4 x float> %b
275275 }
276276
277 ;CHECK: _inreg16xi16
277 ;CHECK-LABEL: _inreg16xi16:
278278 ;CHECK: vpbroadcastw
279279 ;CHECK: ret
280280 define <16 x i16> @_inreg16xi16(<16 x i16> %a) {
282282 ret <16 x i16> %b
283283 }
284284
285 ;CHECK: _inreg8xi16
285 ;CHECK-LABEL: _inreg8xi16:
286286 ;CHECK: vpbroadcastw
287287 ;CHECK: ret
288288 define <8 x i16> @_inreg8xi16(<8 x i16> %a) {
291291 }
292292
293293
294 ;CHECK: _inreg4xi64
294 ;CHECK-LABEL: _inreg4xi64:
295295 ;CHECK: vpbroadcastq
296296 ;CHECK: ret
297297 define <4 x i64> @_inreg4xi64(<4 x i64> %a) {
299299 ret <4 x i64> %b
300300 }
301301
302 ;CHECK: _inreg2xi64
302 ;CHECK-LABEL: _inreg2xi64:
303303 ;CHECK: vpbroadcastq
304304 ;CHECK: ret
305305 define <2 x i64> @_inreg2xi64(<2 x i64> %a) {
307307 ret <2 x i64> %b
308308 }
309309
310 ;CHECK: _inreg4xdouble
310 ;CHECK-LABEL: _inreg4xdouble:
311311 ;CHECK: vbroadcastsd
312312 ;CHECK: ret
313313 define <4 x double> @_inreg4xdouble(<4 x double> %a) {
315315 ret <4 x double> %b
316316 }
317317
318 ;CHECK: _inreg2xdouble
318 ;CHECK-LABEL: _inreg2xdouble:
319319 ;CHECK: vpbroadcastq
320320 ;CHECK: ret
321321 define <2 x double> @_inreg2xdouble(<2 x double> %a) {
323323 ret <2 x double> %b
324324 }
325325
326 ;CHECK: _inreg8xi32
326 ;CHECK-LABEL: _inreg8xi32:
327327 ;CHECK: vpbroadcastd
328328 ;CHECK: ret
329329 define <8 x i32> @_inreg8xi32(<8 x i32> %a) {
331331 ret <8 x i32> %b
332332 }
333333
334 ;CHECK: _inreg4xi32
334 ;CHECK-LABEL: _inreg4xi32:
335335 ;CHECK: vpbroadcastd
336336 ;CHECK: ret
337337 define <4 x i32> @_inreg4xi32(<4 x i32> %a) {
339339 ret <4 x i32> %b
340340 }
341341
342 ;CHECK: _inreg32xi8
342 ;CHECK-LABEL: _inreg32xi8:
343343 ;CHECK: vpbroadcastb
344344 ;CHECK: ret
345345 define <32 x i8> @_inreg32xi8(<32 x i8> %a) {
347347 ret <32 x i8> %b
348348 }
349349
350 ;CHECK: _inreg16xi8
350 ;CHECK-LABEL: _inreg16xi8:
351351 ;CHECK: vpbroadcastb
352352 ;CHECK: ret
353353 define <16 x i8> @_inreg16xi8(<16 x i8> %a) {
33 ; In this test we check that sign-extend of the mask bit is performed by
44 ; shifting the needed bit to the MSB, and not using shl+sra.
55
6 ;CHECK: vsel_float
6 ;CHECK-LABEL: vsel_float:
77 ;CHECK: movl $-2147483648
88 ;CHECK-NEXT: movd
99 ;CHECK-NEXT: blendvps
1313 ret <4 x float> %vsel
1414 }
1515
16 ;CHECK: vsel_4xi8
16 ;CHECK-LABEL: vsel_4xi8:
1717 ;CHECK: movl $-2147483648
1818 ;CHECK-NEXT: movd
1919 ;CHECK-NEXT: blendvps
2727 ; We do not have native support for v8i16 blends and we have to use the
2828 ; blendvb instruction or a sequence of NAND/OR/AND. Make sure that we do not r
2929 ; reduce the mask in this case.
30 ;CHECK: vsel_8xi16
30 ;CHECK-LABEL: vsel_8xi16:
3131 ;CHECK: psllw
3232 ;CHECK: psraw
3333 ;CHECK: pblendvb
0 ; RUN: llc < %s -mcpu=corei7-avx -mtriple=x86_64-linux | FileCheck %s
11
2 ;CHECK: cftx020
2 ;CHECK-LABEL: cftx020:
33 ;CHECK: vmovsd (%rdi), %xmm{{.*}}
44 ;CHECK: vmovsd 16(%rdi), %xmm{{.*}}
55 ;CHECK: vmovhpd 8(%rdi), %xmm{{.*}}
0 ; RUN: llc -mcpu=corei7 -mtriple=x86_64-linux -align-all-blocks=16 < %s | FileCheck %s
11
2 ;CHECK: foo
2 ;CHECK-LABEL: foo:
33 ;CHECK: .align 65536, 0x90
44 ;CHECK: .align 65536, 0x90
55 ;CHECK: .align 65536, 0x90
11
22 ; rdar://11897677
33
4 ;CHECK: intrin_pmov
4 ;CHECK-LABEL: intrin_pmov:
55 ;CHECK: pmovzxbw (%{{.*}}), %xmm0
66 ;CHECK-NEXT: movdqu
77 ;CHECK-NEXT: ret
0 ; RUN: llc -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -o - < %s | FileCheck %s
11
2 ;CHECK: wideloads
2 ;CHECK-LABEL: wideloads:
33 ;CHECK: vmovaps
44 ;CHECK: vinsertf128
55 ;CHECK: vmovaps
0 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -mattr=+sse41 | FileCheck %s
11
2 ;CHECK: vsel_float
2 ;CHECK-LABEL: vsel_float:
33 ;CHECK: blendvps
44 ;CHECK: ret
55 define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
88 }
99
1010
11 ;CHECK: vsel_4xi8
11 ;CHECK-LABEL: vsel_4xi8:
1212 ;CHECK: blendvps
1313 ;CHECK: ret
1414 define <4 x i8> @vsel_4xi8(<4 x i8> %v1, <4 x i8> %v2) {
1616 ret <4 x i8> %vsel
1717 }
1818
19 ;CHECK: vsel_4xi16
19 ;CHECK-LABEL: vsel_4xi16:
2020 ;CHECK: blendvps
2121 ;CHECK: ret
2222 define <4 x i16> @vsel_4xi16(<4 x i16> %v1, <4 x i16> %v2) {
2525 }
2626
2727
28 ;CHECK: vsel_i32
28 ;CHECK-LABEL: vsel_i32:
2929 ;CHECK: blendvps
3030 ;CHECK: ret
3131 define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {
3434 }
3535
3636
37 ;CHECK: vsel_double
37 ;CHECK-LABEL: vsel_double:
3838 ;CHECK: blendvpd
3939 ;CHECK: ret
4040 define <4 x double> @vsel_double(<4 x double> %v1, <4 x double> %v2) {
4343 }
4444
4545
46 ;CHECK: vsel_i64
46 ;CHECK-LABEL: vsel_i64:
4747 ;CHECK: blendvpd
4848 ;CHECK: ret
4949 define <4 x i64> @vsel_i64(<4 x i64> %v1, <4 x i64> %v2) {
5252 }
5353
5454
55 ;CHECK: vsel_i8
55 ;CHECK-LABEL: vsel_i8:
5656 ;CHECK: pblendvb
5757 ;CHECK: ret
5858 define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
0 ; RUN: llc < %s -march=x86-64 -mcpu=corei7 -mattr=+sse41 | FileCheck %s
11
2 ;CHECK: load_2_i8
2 ;CHECK-LABEL: load_2_i8:
33 ; A single 16-bit load
44 ;CHECK: pmovzxbq
55 ;CHECK: paddq
1515 ret void
1616 }
1717
18 ;CHECK: load_2_i16
18 ;CHECK-LABEL: load_2_i16:
1919 ; Read 32-bits
2020 ;CHECK: pmovzxwq
2121 ;CHECK: paddq
2929 ret void
3030 }
3131
32 ;CHECK: load_2_i32
32 ;CHECK-LABEL: load_2_i32:
3333 ;CHECK: pmovzxdq
3434 ;CHECK: paddq
3535 ;CHECK: pshufd
4141 ret void
4242 }
4343
44 ;CHECK: load_4_i8
44 ;CHECK-LABEL: load_4_i8:
4545 ;CHECK: pmovzxbd
4646 ;CHECK: paddd
4747 ;CHECK: pshufb
5353 ret void
5454 }
5555
56 ;CHECK: load_4_i16
56 ;CHECK-LABEL: load_4_i16:
5757 ;CHECK: pmovzxwd
5858 ;CHECK: paddd
5959 ;CHECK: pshufb
6565 ret void
6666 }
6767
68 ;CHECK: load_8_i8
68 ;CHECK-LABEL: load_8_i8:
6969 ;CHECK: pmovzxbw
7070 ;CHECK: paddw
7171 ;CHECK: pshufb
0 ; RUN: llc -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -o - < %s | FileCheck %s
11
2 ;CHECK: and_masks
2 ;CHECK-LABEL: and_masks:
33 ;CHECK: vmovaps
44 ;CHECK: vcmpltp
55 ;CHECK: vcmpltp
0 ; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=corei7-avx -mattr=+avx | FileCheck %s
11
2 ;CHECK: foo1_8
2 ;CHECK-LABEL: foo1_8:
33 ;CHECK: vcvtdq2ps
44 ;CHECK: ret
55 define <8 x float> @foo1_8(<8 x i8> %src) {
77 ret <8 x float> %res
88 }
99
10 ;CHECK: foo1_4
10 ;CHECK-LABEL: foo1_4:
1111 ;CHECK: vcvtdq2ps
1212 ;CHECK: ret
1313 define <4 x float> @foo1_4(<4 x i8> %src) {
1515 ret <4 x float> %res
1616 }
1717
18 ;CHECK: foo2_8
18 ;CHECK-LABEL: foo2_8:
1919 ;CHECK: vcvtdq2ps
2020 ;CHECK: ret
2121 define <8 x float> @foo2_8(<8 x i8> %src) {
2323 ret <8 x float> %res
2424 }
2525
26 ;CHECK: foo2_4
26 ;CHECK-LABEL: foo2_4:
2727 ;CHECK: vcvtdq2ps
2828 ;CHECK: ret
2929 define <4 x float> @foo2_4(<4 x i8> %src) {
3131 ret <4 x float> %res
3232 }
3333
34 ;CHECK: foo3_8
34 ;CHECK-LABEL: foo3_8:
3535 ;CHECK: vcvttps2dq
3636 ;CHECK: ret
3737 define <8 x i8> @foo3_8(<8 x float> %src) {
3838 %res = fptosi <8 x float> %src to <8 x i8>
3939 ret <8 x i8> %res
4040 }
41 ;CHECK: foo3_4
41 ;CHECK-LABEL: foo3_4:
4242 ;CHECK: vcvttps2dq
4343 ;CHECK: ret
4444 define <4 x i8> @foo3_4(<4 x float> %src) {