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ARM: thumb stores cannot use PC as dest register git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184179 91177308-0d34-0410-b5e6-96231b3b80d8 Amaury de la Vieuville 7 years ago
2 changed file(s) with 74 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
31633163 unsigned Rm = fieldFromInstruction(Val, 2, 4);
31643164 unsigned imm = fieldFromInstruction(Val, 0, 2);
31653165
3166 // Thumb stores cannot use PC as dest register.
3167 switch (Inst.getOpcode()) {
3168 case ARM::t2STRHs:
3169 case ARM::t2STRBs:
3170 case ARM::t2STRs:
3171 if (Rn == 15)
3172 return MCDisassembler::Fail;
3173 default:
3174 break;
3175 }
3176
31663177 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
31673178 return MCDisassembler::Fail;
31683179 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
32913302 unsigned Rn = fieldFromInstruction(Val, 9, 4);
32923303 unsigned imm = fieldFromInstruction(Val, 0, 9);
32933304
3305 // Thumb stores cannot use PC as dest register.
3306 switch (Inst.getOpcode()) {
3307 case ARM::t2STRT:
3308 case ARM::t2STRBT:
3309 case ARM::t2STRHT:
3310 case ARM::t2STRi8:
3311 case ARM::t2STRHi8:
3312 case ARM::t2STRBi8:
3313 if (Rn == 15)
3314 return MCDisassembler::Fail;
3315 break;
3316 default:
3317 break;
3318 }
3319
32943320 // Some instructions always use an additive offset.
32953321 switch (Inst.getOpcode()) {
32963322 case ARM::t2LDRT:
33513377
33523378 unsigned Rn = fieldFromInstruction(Val, 13, 4);
33533379 unsigned imm = fieldFromInstruction(Val, 0, 12);
3380
3381 // Thumb stores cannot use PC as dest register.
3382 switch (Inst.getOpcode()) {
3383 case ARM::t2STRi12:
3384 case ARM::t2STRBi12:
3385 case ARM::t2STRHi12:
3386 if (Rn == 15)
3387 return MCDisassembler::Fail;
3388 default:
3389 break;
3390 }
33543391
33553392 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
33563393 return MCDisassembler::Fail;
0 # invalid STRi12 Rn=PC
1 # RUN: echo "0xcf 0xf8 0x00 0x00" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
2
3 # invalid STRi8 Rn=PC
4 # RUN: echo "0x4f 0xf8 0x00 0x0c" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
5
6 # invalid STRs Rn=PC
7 # RUN: echo "0x4f 0xf8 0x00 0x00" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
8
9 # invalid STRBi12 Rn=PC
10 # RUN: echo "0x0f 0xf8 0x00 0x00" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
11
12 # invalid STRBi8 Rn=PC
13 # RUN: echo "0x0f 0xf8 0x00 0x0c" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
14
15 # invalid STRBs Rn=PC
16 # RUN: echo "0x0f 0xf8 0x00 0x00" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
17
18 # invalid STRHi12 Rn=PC
19 # RUN: echo "0xaf 0xf8 0x00 0x00" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
20
21 # invalid STRHi8 Rn=PC
22 # RUN: echo "0x2f 0xf8 0x00 0x0c" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
23
24 # invalid STRHs Rn=PC
25 # RUN: echo "0x2f 0xf8 0x00 0x00" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
26
27 # invalid STRBT Rn=PC
28 # RUN: echo "0x0f 0xf8 0x00 0x0e" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
29
30 # invalid STRHT Rn=PC
31 # RUN: echo "0x2f 0xf8 0x00 0x0e" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
32
33 # invalid STRT Rn=PC
34 # RUN: echo "0x4f 0xf8 0x00 0x0e" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
35
36 # CHECK: invalid instruction encoding