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[ARM] GlobalISel: Lower i8 and i16 register args This allows lowering i8 and i16 arguments if they can fit in the registers. Note that the lowering is incomplete - ABI extensions are handled in a subsequent patch. (Last part of) Differential Revision: https://reviews.llvm.org/D27704 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290106 91177308-0d34-0410-b5e6-96231b3b80d8 Diana Picus 3 years ago
3 changed file(s) with 72 addition(s) and 13 deletion(s). Raw diff Collapse all Expand all
3232 static bool isSupportedType(const DataLayout DL, const ARMTargetLowering &TLI,
3333 Type *T) {
3434 EVT VT = TLI.getValueType(DL, T);
35 return VT.isSimple() && VT.isInteger() &&
36 VT.getSimpleVT().getSizeInBits() == 32;
35 if (!VT.isSimple() || !VT.isInteger() || VT.isVector())
36 return false;
37
38 unsigned VTSize = VT.getSimpleVT().getSizeInBits();
39 return VTSize == 8 || VTSize == 16 || VTSize == 32;
3740 }
3841
3942 namespace {
5255 assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
5356 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
5457
55 assert(VA.getValVT().getSizeInBits() == 32 && "Unsupported value size");
58 assert(VA.getValVT().getSizeInBits() <= 32 && "Unsupported value size");
5659 assert(VA.getLocVT().getSizeInBits() == 32 && "Unsupported location size");
60
61 assert(VA.getLocInfo() != CCValAssign::SExt &&
62 VA.getLocInfo() != CCValAssign::ZExt &&
63 "ABI extensions not supported yet");
5764
5865 MIRBuilder.buildCopy(PhysReg, ValVReg);
5966 MIB.addUse(PhysReg, RegState::Implicit);
143150 assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
144151 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
145152
146 assert(VA.getValVT().getSizeInBits() == 32 && "Unsupported value size");
153 assert(VA.getValVT().getSizeInBits() <= 32 && "Unsupported value size");
147154 assert(VA.getLocVT().getSizeInBits() == 32 && "Unsupported location size");
148155
149156 MIRBuilder.getMBB().addLiveIn(PhysReg);
166173 auto &TLI = *getTLI();
167174
168175 auto &Args = F.getArgumentList();
169 for (auto &Arg : Args)
176 unsigned ArgIdx = 0;
177 for (auto &Arg : Args) {
178 ArgIdx++;
170179 if (!isSupportedType(DL, TLI, Arg.getType()))
171180 return false;
181
182 // FIXME: This check as well as ArgIdx are going away as soon as we support
183 // loading values < 32 bits.
184 if (ArgIdx > 4 && Arg.getType()->getIntegerBitWidth() != 32)
185 return false;
186 }
172187
173188 CCAssignFn *AssignFn =
174189 TLI.CCAssignFnForCall(F.getCallingConv(), F.isVarArg());
66 ret void
77 }
88
9 define i32 @test_add(i32 %x, i32 %y) {
10 ; CHECK-LABEL: name: test_add
9 define i8 @test_add_i8(i8 %x, i8 %y) {
10 ; CHECK-LABEL: name: test_add_i8
1111 ; CHECK: liveins: %r0, %r1
12 ; CHECK: [[VREGX:%[0-9]+]]{{.*}} = COPY %r0
13 ; CHECK: [[VREGY:%[0-9]+]]{{.*}} = COPY %r1
14 ; CHECK: [[SUM:%[0-9]+]]{{.*}} = G_ADD [[VREGX]], [[VREGY]]
15 ; CHECK: %r0 = COPY [[SUM]]
12 ; CHECK-DAG: [[VREGX:%[0-9]+]](s8) = COPY %r0
13 ; CHECK-DAG: [[VREGY:%[0-9]+]](s8) = COPY %r1
14 ; CHECK: [[SUM:%[0-9]+]](s8) = G_ADD [[VREGX]], [[VREGY]]
15 ; CHECK: %r0 = COPY [[SUM]](s8)
16 ; CHECK: BX_RET 14, _, implicit %r0
17 entry:
18 %sum = add i8 %x, %y
19 ret i8 %sum
20 }
21
22 define i16 @test_add_i16(i16 %x, i16 %y) {
23 ; CHECK-LABEL: name: test_add_i16
24 ; CHECK: liveins: %r0, %r1
25 ; CHECK-DAG: [[VREGX:%[0-9]+]](s16) = COPY %r0
26 ; CHECK-DAG: [[VREGY:%[0-9]+]](s16) = COPY %r1
27 ; CHECK: [[SUM:%[0-9]+]](s16) = G_ADD [[VREGX]], [[VREGY]]
28 ; CHECK: %r0 = COPY [[SUM]](s16)
29 ; CHECK: BX_RET 14, _, implicit %r0
30 entry:
31 %sum = add i16 %x, %y
32 ret i16 %sum
33 }
34
35 define i32 @test_add_i32(i32 %x, i32 %y) {
36 ; CHECK-LABEL: name: test_add_i32
37 ; CHECK: liveins: %r0, %r1
38 ; CHECK-DAG: [[VREGX:%[0-9]+]](s32) = COPY %r0
39 ; CHECK-DAG: [[VREGY:%[0-9]+]](s32) = COPY %r1
40 ; CHECK: [[SUM:%[0-9]+]](s32) = G_ADD [[VREGX]], [[VREGY]]
41 ; CHECK: %r0 = COPY [[SUM]](s32)
1642 ; CHECK: BX_RET 14, _, implicit %r0
1743 entry:
1844 %sum = add i32 %x, %y
66 ret void
77 }
88
9 define i32 @test_add(i32 %x, i32 %y) {
10 ; CHECK-LABEL: test_add:
9 define i8 @test_add_i8(i8 %x, i8 %y) {
10 ; CHECK-LABEL: test_add_i8:
11 ; CHECK: add r0, r0, r1
12 ; CHECK: bx lr
13 entry:
14 %sum = add i8 %x, %y
15 ret i8 %sum
16 }
17
18 define i16 @test_add_i16(i16 %x, i16 %y) {
19 ; CHECK-LABEL: test_add_i16:
20 ; CHECK: add r0, r0, r1
21 ; CHECK: bx lr
22 entry:
23 %sum = add i16 %x, %y
24 ret i16 %sum
25 }
26
27 define i32 @test_add_i32(i32 %x, i32 %y) {
28 ; CHECK-LABEL: test_add_i32:
1129 ; CHECK: add r0, r0, r1
1230 ; CHECK: bx lr
1331 entry: