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AMDGPU/GlobalISel: Implement select() for G_BITCAST s32 <--> <2 x s16> Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D45881 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332042 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 2 years ago
3 changed file(s) with 47 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
5656
5757 const char *AMDGPUInstructionSelector::getName() { return DEBUG_TYPE; }
5858
59 bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
60 MachineBasicBlock *BB = I.getParent();
61 MachineFunction *MF = BB->getParent();
62 MachineRegisterInfo &MRI = MF->getRegInfo();
63 I.setDesc(TII.get(TargetOpcode::COPY));
64 for (const MachineOperand &MO : I.operands()) {
65 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
66 continue;
67
68 const TargetRegisterClass *RC =
69 TRI.getConstrainedRegClassForOperand(MO, MRI);
70 if (!RC)
71 continue;
72 RBI.constrainGenericRegister(MO.getReg(), *RC, MRI);
73 }
74 return true;
75 }
76
5977 MachineOperand
6078 AMDGPUInstructionSelector::getSubOperand64(MachineOperand &MO,
6179 unsigned SubIdx) const {
440458 return selectImpl(I, CoverageInfo);
441459 case TargetOpcode::G_ADD:
442460 return selectG_ADD(I);
461 case TargetOpcode::G_BITCAST:
462 return selectCOPY(I);
443463 case TargetOpcode::G_CONSTANT:
444464 return selectG_CONSTANT(I);
445465 case TargetOpcode::G_GEP:
5858 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
5959
6060 MachineOperand getSubOperand64(MachineOperand &MO, unsigned SubIdx) const;
61 bool selectCOPY(MachineInstr &I) const;
6162 bool selectG_CONSTANT(MachineInstr &I) const;
6263 bool selectG_ADD(MachineInstr &I) const;
6364 bool selectG_GEP(MachineInstr &I) const;
0 # RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
1
2 --- |
3 define amdgpu_kernel void @bitcast(i32 addrspace(1)* %global0) {ret void}
4 ...
5 ---
6
7 name: bitcast
8 legalized: true
9 regBankSelected: true
10
11 # GCN-LABEL: name: bitcast
12 # GCN: [[A:%[0-9]+]]:vgpr_32 = COPY $vgpr0
13 # GCN: [[B:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
14 # GCN: FLAT_STORE_DWORD [[B]], [[A]]
15
16 body: |
17 bb.0:
18 liveins: $sgpr0, $vgpr3_vgpr4
19 %0:vgpr(s32) = COPY $vgpr0
20 %1:vgpr(s64) = COPY $vgpr3_vgpr4
21 %2:vgpr(<2 x s16>) = G_BITCAST %0
22 %3:vgpr(s32) = G_BITCAST %2
23 G_STORE %3, %1 :: (store 4 into %ir.global0)
24 ...
25 ---