llvm.org GIT mirror llvm / ce392eb
Make x86 test actually test x86 code generation. Fix the construct on ARM, which was breaking by coincidence, and add a similar testcase for ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79719 91177308-0d34-0410-b5e6-96231b3b80d8 Eli Friedman 10 years ago
3 changed file(s) with 15 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
21332133 N->getOperand(0), NegatedCount);
21342134 }
21352135
2136 assert(VT == MVT::i64 &&
2137 (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
2136 // We can get here for a node like i32 = ISD::SHL i32, i64
2137 if (VT != MVT::i64)
2138 return SDValue();
2139
2140 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
21382141 "Unknown shift to lower!");
21392142
21402143 // We only lower SRA, SRL of 1 here, all others use generic lowering.
0 ; RUN: llvm-as < %s | llc -march=arm -mattr=-neon
1
2 ; Example that requires splitting and expanding a vector shift.
3 define <2 x i64> @update(<2 x i64> %val) nounwind readnone {
4 entry:
5 %shr = lshr <2 x i64> %val, < i64 2, i64 2 > ; <<2 x i64>> [#uses=1]
6 ret <2 x i64> %shr
7 }
None ; RUN: llvm-as < %s | llc
0 ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
11
22 ; Example that requires splitting and expanding a vector shift.
33 define <2 x i64> @update(<2 x i64> %val) nounwind readnone {
44 entry:
5 %shr = lshr <2 x i64> %val, < i64 2, i64 2 > ; <<2 x i64>> [#uses=1]
5 %shr = lshr <2 x i64> %val, < i64 2, i64 3 >
66 ret <2 x i64> %shr
77 }