llvm.org GIT mirror llvm / ce1c8d9
Improve handling of COPY instructions with identical value numbers Testcases provided by Tim Renouf. Differential Revision: https://reviews.llvm.org/D48102 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335472 91177308-0d34-0410-b5e6-96231b3b80d8 Krzysztof Parzyszek 1 year, 8 months ago
8 changed file(s) with 1133 addition(s) and 30 deletion(s). Raw diff Collapse all Expand all
232232 void addUndefFlag(const LiveInterval &Int, SlotIndex UseIdx,
233233 MachineOperand &MO, unsigned SubRegIdx);
234234
235 /// Handle copies of undef values.
236 /// Returns true if @p CopyMI was a copy of an undef value and eliminated.
237 bool eliminateUndefCopy(MachineInstr *CopyMI);
235 /// Handle copies of undef values. If the undef value is an incoming
236 /// PHI value, it will convert @p CopyMI to an IMPLICIT_DEF.
237 /// Returns nullptr if @p CopyMI was not in any way eliminable. Otherwise,
238 /// it returns @p CopyMI (which could be an IMPLICIT_DEF at this point).
239 MachineInstr *eliminateUndefCopy(MachineInstr *CopyMI);
238240
239241 /// Check whether or not we should apply the terminal rule on the
240242 /// destination (Dst) of \p Copy.
13661368 return true;
13671369 }
13681370
1369 bool RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI) {
1371 MachineInstr *RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI) {
13701372 // ProcessImplicitDefs may leave some copies of values, it only
13711373 // removes local variables. When we have a copy like:
13721374 //
13901392 if ((SR.LaneMask & SrcMask).none())
13911393 continue;
13921394 if (SR.liveAt(Idx))
1393 return false;
1395 return nullptr;
13941396 }
13951397 } else if (SrcLI.liveAt(Idx))
1396 return false;
1397
1398 LLVM_DEBUG(dbgs() << "\tEliminating copy of value\n");
1399
1400 // Remove any DstReg segments starting at the instruction.
1398 return nullptr;
1399
1400 // If the undef copy defines a live-out value (i.e. an input to a PHI def),
1401 // then replace it with an IMPLICIT_DEF.
14011402 LiveInterval &DstLI = LIS->getInterval(DstReg);
14021403 SlotIndex RegIndex = Idx.getRegSlot();
1404 LiveRange::Segment *Seg = DstLI.getSegmentContaining(RegIndex);
1405 assert(Seg != nullptr && "No segment for defining instruction");
1406 if (VNInfo *V = DstLI.getVNInfoAt(Seg->end)) {
1407 if (V->isPHIDef()) {
1408 CopyMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
1409 for (unsigned i = CopyMI->getNumOperands(); i != 0; --i) {
1410 MachineOperand &MO = CopyMI->getOperand(i-1);
1411 if (MO.isReg() && MO.isUse())
1412 CopyMI->RemoveOperand(i-1);
1413 }
1414 LLVM_DEBUG(dbgs() << "\tReplaced copy of value with an "
1415 "implicit def\n");
1416 return CopyMI;
1417 }
1418 }
1419
1420 // Remove any DstReg segments starting at the instruction.
1421 LLVM_DEBUG(dbgs() << "\tEliminating copy of value\n");
1422
14031423 // Remove value or merge with previous one in case of a subregister def.
14041424 if (VNInfo *PrevVNI = DstLI.getVNInfoAt(Idx)) {
14051425 VNInfo *VNI = DstLI.getVNInfoAt(RegIndex);
14551475 MO.setIsUndef(true);
14561476 LIS->shrinkToUses(&DstLI);
14571477
1458 return true;
1478 return CopyMI;
14591479 }
14601480
14611481 void RegisterCoalescer::addUndefFlag(const LiveInterval &Int, SlotIndex UseIdx,
16211641 }
16221642
16231643 // Eliminate undefs.
1624 if (!CP.isPhys() && eliminateUndefCopy(CopyMI)) {
1625 deleteInstr(CopyMI);
1626 return false; // Not coalescable.
1644 if (!CP.isPhys()) {
1645 // If this is an IMPLICIT_DEF, leave it alone, but don't try to coalesce.
1646 if (MachineInstr *UndefMI = eliminateUndefCopy(CopyMI)) {
1647 if (UndefMI->isImplicitDef())
1648 return false;
1649 deleteInstr(CopyMI);
1650 return false; // Not coalescable.
1651 }
16271652 }
16281653
16291654 // Coalesced copies are normally removed immediately, but transformations
20772102 /// True once Pruned above has been computed.
20782103 bool PrunedComputed = false;
20792104
2105 /// True if this value is determined to be identical to OtherVNI
2106 /// (in valuesIdentical). This is used with CR_Erase where the erased
2107 /// copy is redundant, i.e. the source value is already the same as
2108 /// the destination. In such cases the subranges need to be updated
2109 /// properly. See comment at pruneSubRegValues for more info.
2110 bool Identical = false;
2111
20802112 Val() = default;
20812113
20822114 bool isAnalyzed() const { return WriteLanes.any(); }
22112243
22122244 std::pair JoinVals::followCopyChain(
22132245 const VNInfo *VNI) const {
2214 unsigned Reg = this->Reg;
2246 unsigned TrackReg = Reg;
22152247
22162248 while (!VNI->isPHIDef()) {
22172249 SlotIndex Def = VNI->def;
22182250 MachineInstr *MI = Indexes->getInstructionFromIndex(Def);
22192251 assert(MI && "No defining instruction");
22202252 if (!MI->isFullCopy())
2221 return std::make_pair(VNI, Reg);
2253 return std::make_pair(VNI, TrackReg);
22222254 unsigned SrcReg = MI->getOperand(1).getReg();
22232255 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
2224 return std::make_pair(VNI, Reg);
2256 return std::make_pair(VNI, TrackReg);
22252257
22262258 const LiveInterval &LI = LIS->getInterval(SrcReg);
22272259 const VNInfo *ValueIn;
22422274 break;
22432275 }
22442276 }
2245 if (ValueIn == nullptr)
2246 break;
2277 if (ValueIn == nullptr) {
2278 // Reaching an undefined value is legitimate, for example:
2279 //
2280 // 1 undef %0.sub1 = ... ;; %0.sub0 == undef
2281 // 2 %1 = COPY %0 ;; %1 is defined here.
2282 // 3 %0 = COPY %1 ;; Now %0.sub0 has a definition,
2283 // ;; but it's equivalent to "undef".
2284 return std::make_pair(nullptr, SrcReg);
2285 }
22472286 VNI = ValueIn;
2248 Reg = SrcReg;
2249 }
2250 return std::make_pair(VNI, Reg);
2287 TrackReg = SrcReg;
2288 }
2289 return std::make_pair(VNI, TrackReg);
22512290 }
22522291
22532292 bool JoinVals::valuesIdentical(VNInfo *Value0, VNInfo *Value1,
22552294 const VNInfo *Orig0;
22562295 unsigned Reg0;
22572296 std::tie(Orig0, Reg0) = followCopyChain(Value0);
2258 if (Orig0 == Value1)
2297 if (Orig0 == Value1 && Reg0 == Other.Reg)
22592298 return true;
22602299
22612300 const VNInfo *Orig1;
22622301 unsigned Reg1;
22632302 std::tie(Orig1, Reg1) = Other.followCopyChain(Value1);
2303 // If both values are undefined, and the source registers are the same
2304 // register, the values are identical. Filter out cases where only one
2305 // value is defined.
2306 if (Orig0 == nullptr || Orig1 == nullptr)
2307 return Orig0 == Orig1 && Reg0 == Reg1;
22642308
22652309 // The values are equal if they are defined at the same place and use the
22662310 // same register. Note that we cannot compare VNInfos directly as some of
24362480 // %other = COPY %ext
24372481 // %this = COPY %ext <-- Erase this copy
24382482 //
2439 if (DefMI->isFullCopy() && !CP.isPartial()
2440 && valuesIdentical(VNI, V.OtherVNI, Other))
2483 if (DefMI->isFullCopy() && !CP.isPartial() &&
2484 valuesIdentical(VNI, V.OtherVNI, Other)) {
2485 V.Identical = true;
24412486 return CR_Erase;
2487 }
24422488
24432489 // If the lanes written by this instruction were all undef in OtherVNI, it is
24442490 // still safe to join the live ranges. This can't be done with a simple value
27422788 }
27432789 }
27442790
2791 /// Consider the following situation when coalescing the copy between
2792 /// %31 and %45 at 800. (The vertical lines represent live range segments.)
2793 ///
2794 /// Main range Subrange 0004 (sub2)
2795 /// %31 %45 %31 %45
2796 /// 544 %45 = COPY %28 + +
2797 /// | v1 | v1
2798 /// 560B bb.1: + +
2799 /// 624 = %45.sub2 | v2 | v2
2800 /// 800 %31 = COPY %45 + + + +
2801 /// | v0 | v0
2802 /// 816 %31.sub1 = ... + |
2803 /// 880 %30 = COPY %31 | v1 +
2804 /// 928 %45 = COPY %30 | + +
2805 /// | | v0 | v0 <--+
2806 /// 992B ; backedge -> bb.1 | + + |
2807 /// 1040 = %31.sub0 + |
2808 /// This value must remain
2809 /// live-out!
2810 ///
2811 /// Assuming that %31 is coalesced into %45, the copy at 928 becomes
2812 /// redundant, since it copies the value from %45 back into it. The
2813 /// conflict resolution for the main range determines that %45.v0 is
2814 /// to be erased, which is ok since %31.v1 is identical to it.
2815 /// The problem happens with the subrange for sub2: it has to be live
2816 /// on exit from the block, but since 928 was actually a point of
2817 /// definition of %45.sub2, %45.sub2 was not live immediately prior
2818 /// to that definition. As a result, when 928 was erased, the value v0
2819 /// for %45.sub2 was pruned in pruneSubRegValues. Consequently, an
2820 /// IMPLICIT_DEF was inserted as a "backedge" definition for %45.sub2,
2821 /// providing an incorrect value to the use at 624.
2822 ///
2823 /// Since the main-range values %31.v1 and %45.v0 were proved to be
2824 /// identical, the corresponding values in subranges must also be the
2825 /// same. A redundant copy is removed because it's not needed, and not
2826 /// because it copied an undefined value, so any liveness that originated
2827 /// from that copy cannot disappear. When pruning a value that started
2828 /// at the removed copy, the corresponding identical value must be
2829 /// extended to replace it.
27452830 void JoinVals::pruneSubRegValues(LiveInterval &LI, LaneBitmask &ShrinkMask) {
27462831 // Look for values being erased.
27472832 bool DidPrune = false;
27482833 for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
2834 Val &V = Vals[i];
27492835 // We should trigger in all cases in which eraseInstrs() does something.
27502836 // match what eraseInstrs() is doing, print a message so
2751 if (Vals[i].Resolution != CR_Erase &&
2752 (Vals[i].Resolution != CR_Keep || !Vals[i].ErasableImplicitDef ||
2753 !Vals[i].Pruned))
2837 if (V.Resolution != CR_Erase &&
2838 (V.Resolution != CR_Keep || !V.ErasableImplicitDef || !V.Pruned))
27542839 continue;
27552840
27562841 // Check subranges at the point where the copy will be removed.
27572842 SlotIndex Def = LR.getValNumInfo(i)->def;
2843 SlotIndex OtherDef;
2844 if (V.Identical)
2845 OtherDef = V.OtherVNI->def;
2846
27582847 // Print message so mismatches with eraseInstrs() can be diagnosed.
27592848 LLVM_DEBUG(dbgs() << "\t\tExpecting instruction removal at " << Def
27602849 << '\n');
27672856 if (ValueOut != nullptr && Q.valueIn() == nullptr) {
27682857 LLVM_DEBUG(dbgs() << "\t\tPrune sublane " << PrintLaneMask(S.LaneMask)
27692858 << " at " << Def << "\n");
2770 LIS->pruneValue(S, Def, nullptr);
2859 SmallVector EndPoints;
2860 LIS->pruneValue(S, Def, &EndPoints);
27712861 DidPrune = true;
27722862 // Mark value number as unused.
27732863 ValueOut->markUnused();
2864
2865 if (V.Identical && S.Query(OtherDef).valueOut()) {
2866 // If V is identical to V.OtherVNI (and S was live at OtherDef),
2867 // then we can't simply prune V from S. V needs to be replaced
2868 // with V.OtherVNI.
2869 LIS->extendToIndices(S, EndPoints);
2870 }
27742871 continue;
27752872 }
27762873 // If a subrange ends at the copy, then a value was copied but only
29633060 LRange.join(RRange, LHSVals.getAssignments(), RHSVals.getAssignments(),
29643061 NewVNInfo);
29653062
2966 LLVM_DEBUG(dbgs() << "\t\tjoined lanes: " << LRange << "\n");
3063 LLVM_DEBUG(dbgs() << "\t\tjoined lanes: " << PrintLaneMask(LaneMask)
3064 << ' ' << LRange << "\n");
29673065 if (EndPoints.empty())
29683066 return;
29693067
0 # RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx803 -run-pass=simple-register-coalescing -o - %s | FileCheck -check-prefix=GCN %s
1
2 # GCN: {{^body}}
3
4 ---
5 name: foo
6 tracksRegLiveness: true
7 body: |
8 bb.0:
9 successors: %bb.2
10 %0:sreg_32_xm0 = S_MOV_B32 1
11 %1:vgpr_32 = COPY %0
12 INLINEASM &"; %1", 1, 327690, def %1, 2147483657, %1(tied-def 3)
13 %2:sreg_64 = V_CMP_NE_U32_e64 0, %1, implicit $exec
14 undef %3.sub0:sreg_128 = COPY %0
15 %3.sub1:sreg_128 = COPY %0
16 %3.sub2:sreg_128 = COPY %0
17 %4:sreg_128 = COPY %3
18 %5:vgpr_32 = V_MOV_B32_e32 -64, implicit $exec
19 %6:vreg_128 = COPY %4
20 %7:sreg_32_xm0 = S_AND_B32 target-flags(amdgpu-gotprel) 1, %2.sub0, implicit-def dead $scc
21 %8:sreg_32_xm0 = S_MOV_B32 0
22 %9:vgpr_32 = COPY %5
23 %10:vreg_128 = COPY %6
24 S_BRANCH %bb.2
25
26 bb.1:
27 %11:vgpr_32 = V_OR_B32_e32 %12.sub0, %12.sub1, implicit $exec
28 %13:vgpr_32 = V_OR_B32_e32 %11, %12.sub2, implicit $exec
29 %14:vgpr_32 = V_AND_B32_e32 1, %13, implicit $exec
30 %15:sreg_64_xexec = V_CMP_EQ_U32_e64 0, %14, implicit $exec
31 %16:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %15, implicit $exec
32 BUFFER_STORE_DWORD_OFFEN_exact %16, undef %17:vgpr_32, undef %18:sreg_128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into constant-pool, align 1, addrspace 4)
33 S_ENDPGM
34
35 bb.2:
36 successors: %bb.3, %bb.4
37 %19:sreg_64 = V_CMP_EQ_U32_e64 1, %7, implicit $exec
38 %20:sreg_64 = COPY $exec, implicit-def $exec
39 %21:sreg_64 = S_AND_B64 %20, %19, implicit-def dead $scc
40 $exec = S_MOV_B64_term %21
41 SI_MASK_BRANCH %bb.4, implicit $exec
42 S_BRANCH %bb.3
43
44 bb.3:
45 successors: %bb.4
46 undef %22.sub0:sreg_128 = COPY %8
47 %22.sub1:sreg_128 = COPY %8
48 %22.sub2:sreg_128 = COPY %8
49 %23:sreg_128 = COPY %22
50 %24:vreg_128 = COPY %23
51 %10:vreg_128 = COPY %24
52
53 bb.4:
54 successors: %bb.5
55 $exec = S_OR_B64 $exec, %20, implicit-def $scc
56
57 bb.5:
58 successors: %bb.7, %bb.6
59 S_CBRANCH_SCC0 %bb.7, implicit undef $scc
60
61 bb.6:
62 successors: %bb.9
63 %12:vreg_128 = COPY %10
64 S_BRANCH %bb.9
65
66 bb.7:
67 successors: %bb.8, %bb.10
68 %25:vgpr_32 = V_AND_B32_e32 target-flags(amdgpu-gotprel32-hi) 1, %10.sub2, implicit $exec
69 %26:sreg_64 = V_CMP_EQ_U32_e64 1, %25, implicit $exec
70 %27:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
71 %28:vreg_1 = COPY %27
72 %29:sreg_64 = COPY $exec, implicit-def $exec
73 %30:sreg_64 = S_AND_B64 %29, %26, implicit-def dead $scc
74 $exec = S_MOV_B64_term %30
75 SI_MASK_BRANCH %bb.10, implicit $exec
76 S_BRANCH %bb.8
77
78 bb.8:
79 successors: %bb.10
80 %31:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN undef %32:vgpr_32, undef %33:sreg_128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from constant-pool, align 1, addrspace 4)
81 %34:sreg_64_xexec = V_CMP_NE_U32_e64 0, %31, implicit $exec
82 %35:vgpr_32 = V_CNDMASK_B32_e64 0, -1, %34, implicit $exec
83 %28:vreg_1 = COPY %35
84 S_BRANCH %bb.10
85
86 bb.9:
87 successors: %bb.11
88 S_BRANCH %bb.11
89
90 bb.10:
91 successors: %bb.9
92 $exec = S_OR_B64 $exec, %29, implicit-def $scc
93 %36:vreg_1 = COPY %28
94 %37:sreg_64_xexec = V_CMP_NE_U32_e64 0, %36, implicit $exec
95 %38:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %37, implicit $exec
96 %39:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
97 undef %40.sub0:vreg_128 = COPY %39
98 %40.sub1:vreg_128 = COPY %39
99 %40.sub2:vreg_128 = COPY %38
100 %41:vreg_128 = COPY %40
101 %12:vreg_128 = COPY %41
102 S_BRANCH %bb.9
103
104 bb.11:
105 successors: %bb.2, %bb.1
106 %42:vgpr_32 = V_ADD_I32_e32 32, %9, implicit-def dead $vcc, implicit $exec
107 V_CMP_EQ_U32_e32 0, %42, implicit-def $vcc, implicit $exec
108 %43:vgpr_32 = COPY %42
109 $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
110 %44:vreg_128 = COPY %12
111 %9:vgpr_32 = COPY %43
112 %10:vreg_128 = COPY %44
113 S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc
114 S_BRANCH %bb.2
115 ...
0 # RUN: llc -mtriple=amdgcn--amdpal -run-pass=simple-register-coalescing -o - %s | FileCheck %s
1
2 # Check that this doesn't crash. Check for some legitimate output.
3 # CHECK: S_CBRANCH_SCC1
4
5 ---
6 name: fred
7 tracksRegLiveness: true
8 body: |
9 bb.0:
10 successors: %bb.1, %bb.2
11 liveins: $sgpr4
12 undef %0.sub2:sreg_128 = COPY $sgpr4
13 %3 = IMPLICIT_DEF
14 S_CBRANCH_SCC1 %bb.2, implicit undef $scc
15
16 bb.1:
17 successors: %bb.2
18 %0.sub0:sreg_128 = COPY %0.sub2
19 %0.sub1:sreg_128 = COPY %0.sub2
20 %1:sreg_128 = COPY %0
21 %2:sreg_128 = COPY %0
22 %0:sreg_128 = COPY %2
23 %3:sreg_128 = COPY %1
24
25 bb.2:
26 $sgpr1 = COPY %3
27 $sgpr2 = COPY %0.sub2
28 ...
0 # RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx803 -run-pass=simple-register-coalescing -o - %s | FileCheck -check-prefix=GCN %s
1
2 # With one version of the D48102 fix, this test failed with
3 # Assertion failed: (ValNo && "CopyMI input register not live"), function reMaterializeTrivialDef, file ../lib/CodeGen/RegisterCoalescer.cpp, line 1107.
4
5 # GCN: {{^body}}
6
7 --- |
8 target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
9 target triple = "amdgcn--amdpal"
10
11 define amdgpu_cs void @_amdgpu_cs_main(<3 x i32>) #0 {
12 ret void
13 }
14
15 attributes #0 = { nounwind "target-cpu"="gfx803" }
16 ...
17
18 ---
19 name: _amdgpu_cs_main
20 tracksRegLiveness: true
21 body: |
22 bb.0:
23 successors: %bb.1(0x40000000), %bb.2(0x40000000)
24 %0:vgpr_32 = V_MUL_F32_e32 0, undef %1:vgpr_32, implicit $exec
25 %2:vgpr_32 = V_CVT_U32_F32_e32 killed %0, implicit $exec
26 %3:vgpr_32 = V_CVT_F32_I32_e32 killed %2, implicit $exec
27 %4:vgpr_32 = V_CVT_U32_F32_e32 killed %3, implicit $exec
28 %5:vgpr_32 = V_LSHRREV_B32_e32 4, killed %4, implicit $exec
29 S_CBRANCH_SCC0 %bb.2, implicit undef $scc
30
31 bb.1:
32 successors: %bb.5(0x80000000)
33 undef %6.sub1:vreg_128 = COPY killed %5
34 %7:vreg_128 = COPY killed %6
35 S_BRANCH %bb.5
36
37 bb.2:
38 successors: %bb.3(0x40000000), %bb.4(0x40000000)
39 S_CBRANCH_SCC0 %bb.4, implicit undef $scc
40
41 bb.3:
42 successors: %bb.5(0x80000000)
43 %8:sreg_32_xm0 = S_MOV_B32 0
44 undef %9.sub0:sreg_128 = COPY %8
45 %9.sub1:sreg_128 = COPY %8
46 %9.sub2:sreg_128 = COPY %8
47 %9.sub3:sreg_128 = COPY killed %8
48 %10:vreg_128 = COPY killed %9
49 %7:vreg_128 = COPY killed %10
50 S_BRANCH %bb.5
51
52 bb.4:
53 successors: %bb.5(0x80000000)
54 %11:sreg_32_xm0 = S_MOV_B32 0
55 undef %12.sub0:sreg_128 = COPY %11
56 %12.sub1:sreg_128 = COPY %11
57 %12.sub2:sreg_128 = COPY %11
58 %12.sub3:sreg_128 = COPY killed %11
59 %13:sreg_128 = COPY killed %12
60 %14:vreg_128 = COPY killed %13
61 %7:vreg_128 = COPY killed %14
62
63 bb.5:
64 successors: %bb.8(0x40000000), %bb.6(0x40000000)
65 %15:vreg_128 = COPY killed %7
66 S_CBRANCH_SCC0 %bb.8, implicit undef $scc
67
68 bb.6:
69 successors: %bb.7(0x80000000)
70 %16:vreg_128 = COPY killed %15
71
72 bb.7:
73 successors: %bb.14(0x80000000)
74 %17:vreg_128 = COPY killed %16
75 S_BRANCH %bb.14
76
77 bb.8:
78 successors: %bb.9(0x40000000), %bb.11(0x40000000)
79 %18:vgpr_32 = V_MUL_LO_I32 %15.sub1, target-flags(amdgpu-gotprel32-lo) 7, implicit $exec
80 S_CBRANCH_SCC1 %bb.11, implicit undef $scc
81 S_BRANCH %bb.9
82
83 bb.9:
84 successors: %bb.10(0x80000000)
85 %19:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN killed %18, undef %20:sreg_128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, align 1, addrspace 4)
86 %21:sreg_64 = V_CMP_NE_U32_e64 target-flags(amdgpu-gotprel) 0, killed %19.sub0, implicit $exec
87 %22:sreg_64 = COPY $exec, implicit-def $exec
88 %23:sreg_64 = S_AND_B64 %22, %21, implicit-def dead $scc
89 $exec = S_MOV_B64_term killed %23
90
91 bb.10:
92 successors: %bb.12(0x80000000)
93 $exec = S_OR_B64 $exec, killed %22, implicit-def $scc
94 S_BRANCH %bb.12
95
96 bb.11:
97 successors: %bb.13(0x80000000)
98 %24:vreg_128 = COPY killed %15
99 %24.sub0:vreg_128 = COPY undef %18
100 S_BRANCH %bb.13
101
102 bb.12:
103 successors: %bb.11(0x80000000)
104 S_BRANCH %bb.11
105
106 bb.13:
107 successors: %bb.7(0x80000000)
108 %16:vreg_128 = COPY killed %24
109 S_BRANCH %bb.7
110
111 bb.14:
112 successors: %bb.15(0x80000000)
113 S_CBRANCH_SCC1 %bb.15, implicit undef $scc
114 S_BRANCH %bb.15
115
116 bb.15:
117 undef %25.sub2:vreg_128 = COPY killed %17.sub2
118 %26:sreg_32_xm0 = S_MOV_B32 0
119 undef %27.sub0:sreg_256 = COPY %26
120 %27.sub1:sreg_256 = COPY %26
121 %27.sub2:sreg_256 = COPY %26
122 %27.sub3:sreg_256 = COPY %26
123 %27.sub4:sreg_256 = COPY %26
124 %27.sub5:sreg_256 = COPY %26
125 %27.sub6:sreg_256 = COPY %26
126 %27.sub7:sreg_256 = COPY killed %26
127 %28:vgpr_32 = IMAGE_LOAD_V1_V4 killed %25, killed %27, 2, -1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, addrspace 4)
128 %29:vgpr_32 = V_ADD_F32_e32 0, killed %28, implicit $exec
129 $m0 = S_MOV_B32 -1
130 DS_WRITE_B32 undef %30:vgpr_32, killed %29, 0, 0, implicit $m0, implicit $exec :: (store 4 into `i32 addrspace(3)* undef`, addrspace 3)
131 S_ENDPGM
132 ...
0 # RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx803 -run-pass=simple-register-coalescing -o - %s | FileCheck -check-prefix=GCN %s
1
2 # With one version of the D48102 fix, this test failed with
3 # Assertion failed: (Id != S.end() && T != S.end() && T->valno == Id->valno), function pruneSubRegValues, file ../lib/CodeGen/RegisterCoalescer.cpp, line 2875.
4
5 # GCN: {{^body}}
6
7 --- |
8 target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
9 target triple = "amdgcn--amdpal"
10
11 ; Function Attrs: nounwind
12 define amdgpu_ps void @_amdgpu_ps_main(float %arg) #0 {
13 ret void
14 }
15
16 attributes #0 = { nounwind "InitialPSInputAddr"="3842" "target-cpu"="gfx803" }
17 ...
18
19 ---
20 name: _amdgpu_ps_main
21 tracksRegLiveness: true
22 body: |
23 bb.0:
24 successors: %bb.2(0x40000000), %bb.1(0x40000000)
25 %0:sreg_64 = COPY $exec
26 %1:sgpr_32 = S_MOV_B32 0
27 undef %2.sub0:sreg_128 = COPY %1
28 %2.sub1:sreg_128 = COPY %1
29 %2.sub2:sreg_128 = COPY %1
30 %2.sub3:sreg_128 = COPY %1
31 $exec = S_WQM_B64 $exec, implicit-def dead $scc
32 S_CBRANCH_SCC0 %bb.2, implicit undef $scc
33
34 bb.1:
35 successors: %bb.3(0x80000000)
36 %3:sreg_128 = COPY killed %2
37 %4:vreg_128 = COPY killed %3
38 %5:vreg_128 = COPY killed %4
39 S_BRANCH %bb.3
40
41 bb.2:
42 successors: %bb.4(0x80000000)
43 %6:vgpr_32 = V_MUL_F32_e32 1031798784, undef %7:vgpr_32, implicit $exec
44 %8:vgpr_32 = V_FLOOR_F32_e32 killed %6, implicit $exec
45 %9:vgpr_32 = V_ADD_F32_e32 0, killed %8, implicit $exec
46 %10:vgpr_32 = V_CVT_U32_F32_e32 killed %9, implicit $exec
47 %11:vgpr_32 = V_LSHLREV_B32_e32 1, killed %10, implicit $exec
48 %12:sreg_64 = S_MOV_B64 0
49 %13:sreg_128 = COPY killed %2
50 %14:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
51 %15:vreg_128 = COPY killed %13
52 %16:sreg_64 = COPY killed %12
53 %17:vreg_128 = IMPLICIT_DEF
54 %18:vgpr_32 = COPY killed %14
55 %19:vreg_128 = COPY killed %15
56 S_BRANCH %bb.4
57
58 bb.3:
59 successors: %bb.17(0x80000000)
60 %20:vreg_128 = COPY killed %5
61 S_BRANCH %bb.17
62
63 bb.4:
64 successors: %bb.8(0x40000000), %bb.9(0x40000000)
65 %21:vreg_128 = COPY killed %19
66 %22:vgpr_32 = COPY killed %18
67 %23:vreg_128 = COPY killed %17
68 %24:sreg_64 = COPY killed %16
69 %25:vgpr_32 = V_OR_B32_e32 %22, %11, implicit $exec
70 %26:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN killed %25, undef %27:sreg_128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, align 1, addrspace 4)
71 %28:vgpr_32 = V_LSHRREV_B32_e32 30, killed %26.sub0, implicit $exec
72 %29:vreg_128 = COPY killed %21
73 %29.sub0:vreg_128 = COPY %1
74 %30:sreg_64 = V_CMP_NE_U32_e64 0, %28, implicit $exec
75 %31:sreg_64_xexec = V_CMP_EQ_U32_e64 0, %28, implicit $exec
76 dead %32:vgpr_32 = V_CNDMASK_B32_e64 0, -1, killed %31, implicit $exec
77 %33:vreg_128 = COPY %29
78 %33.sub1:vreg_128 = COPY undef %32
79 %34:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
80 %35:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
81 %36:sreg_64 = COPY %24
82 %37:vreg_128 = COPY %23
83 %38:vreg_128 = IMPLICIT_DEF
84 %39:vreg_128 = IMPLICIT_DEF
85 %40:vgpr_32 = IMPLICIT_DEF
86 %41:vreg_1 = COPY killed %35
87 %42:vreg_1 = COPY killed %34
88 %43:sreg_64 = COPY $exec, implicit-def $exec
89 %44:sreg_64 = S_AND_B64 %43, %30, implicit-def dead $scc
90 %45:sreg_64 = S_XOR_B64 %44, %43, implicit-def dead $scc
91 $exec = S_MOV_B64_term killed %44
92 SI_MASK_BRANCH %bb.9, implicit $exec
93 S_BRANCH %bb.8
94
95 bb.5:
96 successors: %bb.9(0x80000000)
97 $exec = S_OR_B64 $exec, %46, implicit-def $scc
98 %47:vreg_1 = COPY killed %48
99 %49:vgpr_32 = COPY killed %50
100 %51:vreg_128 = COPY killed %52
101 %53:vreg_128 = COPY killed %54
102 %55:sreg_64 = COPY killed %56
103 %57:sreg_64 = S_AND_B64 $exec, %46, implicit-def $scc
104 %57:sreg_64 = S_OR_B64 %57, killed %55, implicit-def $scc
105 %58:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
106 %36:sreg_64 = COPY killed %57
107 %37:vreg_128 = COPY killed %53
108 %38:vreg_128 = COPY killed %59
109 %39:vreg_128 = COPY killed %51
110 %40:vgpr_32 = COPY killed %49
111 %41:vreg_1 = COPY killed %47
112 %42:vreg_1 = COPY killed %58
113 S_BRANCH %bb.9
114
115 bb.6:
116 successors: %bb.7(0x40000000), %bb.13(0x40000000)
117 $exec = S_OR_B64 $exec, killed %60, implicit-def $scc
118 %61:sreg_64 = V_CMP_NE_U32_e64 0, killed %62, implicit $exec
119 %63:vreg_128 = COPY killed %64
120 %65:vreg_1 = COPY killed %66
121 %67:sreg_64 = COPY $exec, implicit-def $exec
122 %68:sreg_64 = S_AND_B64 %67, %61, implicit-def dead $scc
123 $exec = S_MOV_B64_term killed %68
124 SI_MASK_BRANCH %bb.13, implicit $exec
125 S_BRANCH %bb.7
126
127 bb.7:
128 successors: %bb.13(0x80000000)
129 %69:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
130 %70:vreg_128 = COPY killed %33
131 %63:vreg_128 = COPY killed %70
132 %65:vreg_1 = COPY killed %69
133 S_BRANCH %bb.13
134
135 bb.8:
136 successors: %bb.10(0x80000000)
137 %71:sreg_64 = S_MOV_B64 0
138 %72:vreg_128 = COPY %33
139 %73:sreg_64 = COPY killed %71
140 %74:vreg_128 = COPY killed %72
141 %75:vreg_128 = COPY killed %29
142 S_BRANCH %bb.10
143
144 bb.9:
145 successors: %bb.6(0x04000000), %bb.4(0x7c000000)
146 $exec = S_OR_B64 $exec, %45, implicit-def $scc
147 %62:vreg_1 = COPY killed %42
148 %66:vreg_1 = COPY killed %41
149 %76:vgpr_32 = COPY killed %40
150 %77:vreg_128 = COPY killed %39
151 %64:vreg_128 = COPY killed %38
152 %78:vreg_128 = COPY killed %37
153 %79:sreg_64 = COPY killed %36
154 %60:sreg_64 = S_AND_B64 $exec, %45, implicit-def $scc
155 %60:sreg_64 = S_OR_B64 %60, killed %79, implicit-def $scc
156 %80:vreg_128 = COPY %78
157 %16:sreg_64 = COPY %60
158 %17:vreg_128 = COPY killed %80
159 %18:vgpr_32 = COPY killed %76
160 %19:vreg_128 = COPY killed %77
161 $exec = S_ANDN2_B64_term $exec, %60
162 S_CBRANCH_EXECNZ %bb.4, implicit $exec
163 S_BRANCH %bb.6
164
165 bb.10:
166 successors: %bb.11(0x80000000)
167 %81:vreg_128 = COPY killed %75
168 %82:vreg_128 = COPY killed %74
169 %83:sreg_64 = COPY killed %73
170
171 bb.11:
172 successors: %bb.12(0x04000000), %bb.10(0x7c000000)
173 undef %59.sub0:vreg_128 = COPY %81.sub0
174 %59.sub2:vreg_128 = COPY %82.sub2
175 %59.sub3:vreg_128 = COPY killed %82.sub3
176 %84:sreg_64 = V_CMP_GE_U32_e64 killed %81.sub0, %28, implicit $exec
177 %85:sreg_64 = S_OR_B64 killed %84, killed %83, implicit-def $scc
178 %86:vreg_128 = COPY %59
179 %73:sreg_64 = COPY %85
180 %74:vreg_128 = COPY %59
181 %75:vreg_128 = COPY killed %86
182 $exec = S_ANDN2_B64_term $exec, %85
183 S_CBRANCH_EXECNZ %bb.10, implicit $exec
184 S_BRANCH %bb.12
185
186 bb.12:
187 successors: %bb.15(0x40000000), %bb.5(0x40000000)
188 $exec = S_OR_B64 $exec, killed %85, implicit-def $scc
189 %87:sreg_64 = V_CMP_LT_U32_e64 11, killed %28, implicit $exec
190 %88:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
191 %56:sreg_64 = COPY %24
192 %54:vreg_128 = COPY killed %23
193 %52:vreg_128 = IMPLICIT_DEF
194 %50:vgpr_32 = IMPLICIT_DEF
195 %48:vreg_1 = COPY killed %88
196 %89:sreg_64 = COPY $exec, implicit-def $exec
197 %90:sreg_64 = S_AND_B64 %89, %87, implicit-def dead $scc
198 %46:sreg_64 = S_XOR_B64 %90, %89, implicit-def dead $scc
199 $exec = S_MOV_B64_term killed %90
200 SI_MASK_BRANCH %bb.5, implicit $exec
201 S_BRANCH %bb.15
202
203 bb.13:
204 successors: %bb.14(0x40000000), %bb.16(0x40000000)
205 $exec = S_OR_B64 $exec, killed %67, implicit-def $scc
206 %91:vreg_1 = COPY killed %65
207 %92:vreg_128 = COPY killed %63
208 %93:sreg_64 = V_CMP_NE_U32_e64 0, killed %91, implicit $exec
209 %94:vreg_128 = COPY killed %78
210 %95:sreg_64 = COPY $exec, implicit-def $exec
211 %96:sreg_64 = S_AND_B64 %95, %93, implicit-def dead $scc
212 $exec = S_MOV_B64_term killed %96
213 SI_MASK_BRANCH %bb.16, implicit $exec
214 S_BRANCH %bb.14
215
216 bb.14:
217 successors: %bb.16(0x80000000)
218 %97:vreg_128 = COPY killed %92
219 %94:vreg_128 = COPY killed %97
220 S_BRANCH %bb.16
221
222 bb.15:
223 successors: %bb.5(0x80000000)
224 %98:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
225 %99:sreg_64 = V_CMP_NE_U32_e64 0, killed %22, implicit $exec
226 %100:sreg_64 = S_OR_B64 killed %99, killed %24, implicit-def $scc
227 %101:vreg_128 = COPY %59
228 %102:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
229 %56:sreg_64 = COPY killed %100
230 %54:vreg_128 = COPY killed %101
231 %52:vreg_128 = COPY %59
232 %50:vgpr_32 = COPY killed %102
233 %48:vreg_1 = COPY killed %98
234 S_BRANCH %bb.5
235
236 bb.16:
237 successors: %bb.3(0x80000000)
238 $exec = S_OR_B64 $exec, killed %95, implicit-def $scc
239 %103:vreg_128 = COPY killed %94
240 %104:vreg_128 = COPY killed %103
241 %5:vreg_128 = COPY killed %104
242 S_BRANCH %bb.3
243
244 bb.17:
245 %105:vgpr_32 = V_ADD_F32_e32 target-flags(amdgpu-rel32-lo) 0, %20.sub3, implicit $exec
246 %106:vgpr_32 = V_ADD_F32_e32 target-flags(amdgpu-gotprel32-hi) 0, killed %20.sub2, implicit $exec
247 undef %107.sub0:vreg_64 = COPY killed %106
248 %107.sub1:vreg_64 = COPY killed %105
249 $exec = S_AND_B64 $exec, killed %0, implicit-def dead $scc
250 %108:sreg_32_xm0 = S_MOV_B32 0
251 undef %109.sub0:sreg_256 = COPY %108
252 %109.sub1:sreg_256 = COPY %108
253 %109.sub2:sreg_256 = COPY %108
254 %109.sub3:sreg_256 = COPY %108
255 %109.sub4:sreg_256 = COPY %108
256 %109.sub5:sreg_256 = COPY %108
257 %109.sub6:sreg_256 = COPY %108
258 %109.sub7:sreg_256 = COPY killed %108
259 %110:vgpr_32 = IMAGE_SAMPLE_V1_V2 killed %107, killed %109, undef %111:sreg_128, 8, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, addrspace 4)
260 %112:vgpr_32 = V_MUL_F32_e32 0, killed %110, implicit $exec
261 %113:vgpr_32 = V_MUL_F32_e32 0, killed %112, implicit $exec
262 %114:vgpr_32 = V_MAD_F32 0, killed %113, 0, 0, 0, 0, 0, 0, implicit $exec
263 %115:vgpr_32 = V_MAX_F32_e32 0, killed %114, implicit $exec
264 %116:vgpr_32 = V_CVT_PKRTZ_F16_F32_e64 0, killed %115, 0, 1065353216, 0, implicit $exec
265 EXP 0, undef %117:vgpr_32, killed %116, undef %118:vgpr_32, undef %119:vgpr_32, -1, -1, 15, implicit $exec
266 S_ENDPGM
267 ...
0 # RUN: llc -march=amdgcn -run-pass simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
1 #
2 # See bug http://llvm.org/PR33152 for details of the bug this test is checking
3 # for.
4 # This test will provoke a subrange join during simple register
5 # coalescing. Withough a fix for PR33152 this causes an unreachable in SubRange
6 # Join
7 #
8 # The lines where the problem exhibits are the last 2 copy instructions in the
9 # BB (bb.25)
10 #
11 # GCN-LABEL: bb.6:
12 # GCN: successors: %bb.7(0x{{[0-9]+}}), %bb.18(0x{{[0-9]+}})
13 # GCN: %{{[0-9]+}}:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %{{[0-9]+}}, 0, 0, 0, 0, 0, implicit $exec
14 #
15
16 --- |
17 target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
18 target triple = "amdgcn--amdpal"
19
20 define amdgpu_ps void @main() #0 {
21 ret void
22 }
23
24 attributes #0 = { "target-cpu"="gfx803" }
25 ...
26
27 ---
28 name: main
29 tracksRegLiveness: true
30 body: |
31 bb.0:
32 successors: %bb.2(0x40000000), %bb.1(0x40000000)
33 S_CBRANCH_SCC0 %bb.2, implicit undef $scc
34
35 bb.1:
36 successors: %bb.9(0x80000000)
37 %0:vreg_128 = IMPLICIT_DEF
38 S_BRANCH %bb.9
39
40 bb.2:
41 successors: %bb.4(0x40000000), %bb.3(0x40000000)
42 S_CBRANCH_SCC0 %bb.4, implicit undef $scc
43
44 bb.3:
45 successors: %bb.5(0x80000000)
46 %1:vreg_128 = IMPLICIT_DEF
47 S_BRANCH %bb.5
48
49 bb.4:
50 successors: %bb.6(0x80000000)
51 %2:sreg_64 = S_MOV_B64 0
52 %3:sreg_32_xm0 = S_MOV_B32 61440
53 %4:sreg_32_xm0 = S_MOV_B32 -1
54 %5:sreg_64 = COPY killed %2
55 %6:vreg_128 = IMPLICIT_DEF
56 S_BRANCH %bb.6
57
58 bb.5:
59 successors: %bb.9(0x80000000)
60 %7:vreg_128 = COPY killed %1
61 %8:vreg_128 = COPY killed %7
62 %0:vreg_128 = COPY killed %8
63 S_BRANCH %bb.9
64
65 bb.6:
66 successors: %bb.7(0x40000000), %bb.18(0x40000000)
67 %9:vreg_128 = COPY killed %6
68 %10:sreg_64 = COPY killed %5
69 undef %11.sub2:sreg_128 = COPY %4
70 %11.sub3:sreg_128 = COPY %3
71 %12:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET killed %11, 0, 0, 0, 0, 0, implicit $exec
72 undef %13.sub1:vreg_128 = COPY %9.sub1
73 %13.sub2:vreg_128 = COPY %9.sub2
74 %14:sreg_64 = V_CMP_GT_F32_e64 0, target-flags(amdgpu-rel32-lo) 0, 0, killed %12.sub3, 0, implicit $exec
75 %15:vgpr_32 = V_ADD_F32_e32 1065353216, undef %16:vgpr_32, implicit $exec
76 %17:sreg_64 = V_CMP_GT_F32_e64 0, 0, 0, killed %15, 0, implicit $exec
77 %18:sreg_64 = S_AND_B64 killed %17, killed %14, implicit-def dead $scc
78 %19:sreg_64 = COPY %10
79 %20:vreg_128 = COPY %13
80 %21:vreg_128 = IMPLICIT_DEF
81 %22:sreg_64 = COPY $exec, implicit-def $exec
82 %23:sreg_64 = S_AND_B64 %22, %18, implicit-def dead $scc
83 %24:sreg_64 = S_XOR_B64 %23, %22, implicit-def dead $scc
84 $exec = S_MOV_B64_term killed %23
85 SI_MASK_BRANCH %bb.7, implicit $exec
86 S_BRANCH %bb.18
87
88 bb.7:
89 successors: %bb.6(0x40000000), %bb.8(0x40000000)
90 $exec = S_OR_B64 $exec, %24, implicit-def $scc
91 %25:vreg_128 = COPY killed %21
92 %26:vreg_128 = COPY killed %20
93 %27:sreg_64 = COPY killed %19
94 %28:sreg_64 = S_OR_B64 %24, killed %27, implicit-def dead $scc
95 %5:sreg_64 = COPY %28
96 %6:vreg_128 = COPY killed %25
97 $exec = S_ANDN2_B64_term $exec, %28
98 S_CBRANCH_EXECNZ %bb.6, implicit $exec
99 S_BRANCH %bb.8
100
101 bb.8:
102 successors: %bb.5(0x80000000)
103 $exec = S_OR_B64 $exec, killed %28, implicit-def $scc
104 %29:vreg_128 = COPY killed %26
105 %1:vreg_128 = COPY killed %29
106 S_BRANCH %bb.5
107
108 bb.9:
109 successors: %bb.10(0x80000000)
110 %30:vreg_128 = COPY killed %0
111 S_BRANCH %bb.10
112
113 bb.10:
114 successors: %bb.12(0x40000000), %bb.11(0x40000000)
115 S_CBRANCH_SCC0 %bb.12, implicit undef $scc
116
117 bb.11:
118 successors: %bb.14(0x80000000)
119 %31:vreg_128 = IMPLICIT_DEF
120 S_BRANCH %bb.14
121
122 bb.12:
123 successors: %bb.13(0x80000000)
124 S_CBRANCH_SCC1 %bb.13, implicit undef $scc
125 S_BRANCH %bb.13
126
127 bb.13:
128 successors: %bb.14(0x80000000)
129 %32:vgpr_32 = V_MUL_F32_e32 undef %33:vgpr_32, killed %30.sub1, implicit $exec
130 %34:vgpr_32 = V_MUL_F32_e32 undef %35:vgpr_32, killed %32, implicit $exec
131 undef %36.sub0:vreg_128 = COPY %34
132 %31:vreg_128 = COPY killed %36
133
134 bb.14:
135 successors: %bb.16(0x40000000), %bb.15(0x40000000)
136 %37:vreg_128 = COPY killed %31
137 S_CBRANCH_SCC0 %bb.16, implicit undef $scc
138
139 bb.15:
140 successors: %bb.17(0x80000000)
141 %38:vreg_128 = IMPLICIT_DEF
142 S_BRANCH %bb.17
143
144 bb.16:
145 successors: %bb.17(0x80000000)
146 %39:vgpr_32 = V_FMA_F32 0, undef %40:vgpr_32, 0, killed %37.sub0, 0, undef %41:vgpr_32, 0, 0, implicit $exec
147 %42:vgpr_32 = V_FMA_F32 0, undef %43:vgpr_32, 0, undef %44:vgpr_32, 0, killed %39, 0, 0, implicit $exec
148 %45:vgpr_32 = V_FMA_F32 0, undef %46:vgpr_32, 0, undef %47:vgpr_32, 0, killed %42, 0, 0, implicit $exec
149 dead %48:vgpr_32 = V_MUL_F32_e32 undef %49:vgpr_32, killed %45, implicit $exec
150 %50:vgpr_32 = V_MUL_F32_e32 undef %51:vgpr_32, undef %52:vgpr_32, implicit $exec
151 undef %53.sub1:vreg_128 = COPY %50
152 %38:vreg_128 = COPY killed %53
153
154 bb.17:
155 %54:vreg_128 = COPY killed %38
156 %55:vgpr_32 = V_FMA_F32 0, killed %54.sub1, 0, target-flags(amdgpu-gotprel32-lo) 1056964608, 0, 1056964608, 0, 0, implicit $exec
157 EXP 1, undef %56:vgpr_32, killed %55, undef %57:vgpr_32, undef %58:vgpr_32, -1, 0, 15, implicit $exec
158 S_ENDPGM
159
160 bb.18:
161 successors: %bb.7(0x80000000)
162 dead %59:vgpr_32 = V_FMA_F32 0, killed %9.sub2, 0, undef %60:vgpr_32, 0, undef %61:vgpr_32, 0, 0, implicit $exec
163 dead %62:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN undef %63:vgpr_32, undef %64:sreg_128, undef %65:sreg_32, 0, 0, 0, 0, implicit $exec
164 undef %66.sub1:vreg_128 = COPY %13.sub1
165 %66.sub2:vreg_128 = COPY %13.sub2
166 %67:sreg_64 = V_CMP_NGT_F32_e64 0, 0, 0, undef %68:vgpr_32, 0, implicit $exec
167 %69:vgpr_32 = V_ADD_F32_e32 1065353216, undef %70:vgpr_32, implicit $exec
168 %71:vgpr_32 = V_ADD_F32_e32 1065353216, killed %69, implicit $exec
169 %72:sreg_64 = V_CMP_NGT_F32_e64 0, 0, 0, killed %71, 0, implicit $exec
170 %73:sreg_64 = S_OR_B64 killed %72, killed %67, implicit-def dead $scc
171 %74:sreg_64 = S_OR_B64 killed %73, killed %10, implicit-def dead $scc
172 %19:sreg_64 = COPY killed %74
173 %20:vreg_128 = COPY %66
174 %21:vreg_128 = COPY killed %66
175 S_BRANCH %bb.7
176 ...
0 # RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx803 -run-pass=simple-register-coalescing -o - %s | FileCheck -check-prefix=GCN %s
1
2 # With one version of the D48102 fix, this test failed with
3 # Assertion failed: (Id != S.end() && T != S.end() && T->valno == Id->valno), function pruneSubRegValues, file ../lib/CodeGen/RegisterCoalescer.cpp, line 2870.
4
5 # GCN: {{^body}}
6
7 --- |
8 target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
9 target triple = "amdgcn--amdpal"
10
11 ; Function Attrs: nounwind
12 define amdgpu_cs void @_amdgpu_cs_main(<3 x i32> %arg) #0 {
13 ret void
14 }
15
16 attributes #0 = { nounwind "target-cpu"="gfx803" }
17 ...
18
19 ---
20 name: _amdgpu_cs_main
21 tracksRegLiveness: true
22 liveins:
23 - { reg: '$vgpr0', virtual-reg: '%0' }
24 body: |
25 bb.0:
26 successors: %bb.1(0x40000000), %bb.21(0x40000000)
27 liveins: $vgpr0, $vgpr1, $vgpr2
28 %0:vgpr_32 = COPY killed $vgpr0
29 S_CBRANCH_SCC1 %bb.21, implicit undef $scc
30
31 bb.1:
32 successors: %bb.2(0x40000000), %bb.17(0x40000000)
33 S_CBRANCH_SCC1 %bb.17, implicit undef $scc
34
35 bb.2:
36 successors: %bb.4(0x40000000), %bb.3(0x40000000)
37 %1:sreg_32_xm0 = S_MOV_B32 0
38 %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
39 undef %3.sub0:vreg_128 = COPY killed %0
40 %3.sub2:vreg_128 = COPY killed %2
41 undef %4.sub0:sreg_256 = COPY %1
42 %4.sub1:sreg_256 = COPY %1
43 %4.sub2:sreg_256 = COPY %1
44 %4.sub3:sreg_256 = COPY %1
45 %4.sub4:sreg_256 = COPY %1
46 %4.sub5:sreg_256 = COPY %1
47 %4.sub6:sreg_256 = COPY %1
48 %4.sub7:sreg_256 = COPY killed %1
49 %5:vgpr_32 = IMAGE_LOAD_V1_V4 killed %3, killed %4, 1, -1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, addrspace 4)
50 %6:vgpr_32 = V_MAD_F32 0, killed %5, 0, 0, 0, 0, 0, 0, implicit $exec
51 %7:vgpr_32 = V_RCP_F32_e32 killed %6, implicit $exec
52 %8:vgpr_32 = V_MUL_F32_e32 0, killed %7, implicit $exec
53 %9:vgpr_32 = V_MAD_F32 0, killed %8, 0, 0, 0, 0, 0, 0, implicit $exec
54 dead %10:vgpr_32 = V_MAC_F32_e32 undef %11:vgpr_32, undef %12:vgpr_32, undef %10, implicit $exec
55 undef %13.sub0:vreg_128 = COPY %9
56 %14:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
57 S_CBRANCH_SCC0 %bb.4, implicit undef $scc
58
59 bb.3:
60 successors: %bb.6(0x80000000)
61 %15:vreg_128 = IMPLICIT_DEF
62 %16:vreg_1 = COPY killed %14
63 S_BRANCH %bb.6
64
65 bb.4:
66 successors: %bb.5(0x40000000), %bb.7(0x40000000)
67 %17:vgpr_32 = V_MAD_F32 0, killed %9, 0, 0, 0, 0, 0, 0, implicit $exec
68 %18:vgpr_32 = V_MIN_F32_e32 1065353216, killed %17, implicit $exec
69 %19:sreg_64_xexec = V_CMP_NEQ_F32_e64 0, 1065353216, 0, killed %18, 0, implicit $exec
70 %20:vgpr_32 = V_MOV_B32_e32 2143289344, implicit $exec
71 %21:vgpr_32 = V_CNDMASK_B32_e64 0, killed %20, killed %19, implicit $exec
72 %22:sreg_64 = V_CMP_LT_F32_e64 0, 0, 0, killed %21, 0, implicit $exec
73 %23:sreg_64 = COPY $exec, implicit-def $exec
74 %24:sreg_64 = S_AND_B64 %23, %22, implicit-def dead $scc
75 $exec = S_MOV_B64_term killed %24
76 SI_MASK_BRANCH %bb.7, implicit $exec
77 S_BRANCH %bb.5
78
79 bb.5:
80 successors: %bb.7(0x80000000)
81 S_BRANCH %bb.7
82
83 bb.6:
84 successors: %bb.8(0x40000000), %bb.10(0x40000000)
85 %25:vreg_1 = COPY killed %16
86 %26:vreg_128 = COPY killed %15
87 %27:sreg_64 = V_CMP_NE_U32_e64 0, killed %25, implicit $exec
88 %28:sreg_64 = S_AND_B64 $exec, killed %27, implicit-def dead $scc
89 $vcc = COPY killed %28
90 %29:vreg_128 = COPY killed %26
91 S_CBRANCH_VCCNZ %bb.8, implicit killed $vcc
92 S_BRANCH %bb.10
93
94 bb.7:
95 successors: %bb.6(0x80000000)
96 $exec = S_OR_B64 $exec, killed %23, implicit-def $scc
97 %30:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
98 %15:vreg_128 = COPY %13
99 %16:vreg_1 = COPY killed %30
100 S_BRANCH %bb.6
101
102 bb.8:
103 successors: %bb.9(0x40000000), %bb.11(0x40000000)
104 %31:vreg_128 = COPY killed %13
105 S_CBRANCH_SCC1 %bb.11, implicit undef $scc
106 S_BRANCH %bb.9
107
108 bb.9:
109 successors: %bb.11(0x80000000)
110 %32:sreg_32_xm0 = S_MOV_B32 0
111 undef %33.sub0:sreg_128 = COPY %32
112 %33.sub1:sreg_128 = COPY %32
113 %33.sub2:sreg_128 = COPY %32
114 %33.sub3:sreg_128 = COPY killed %32
115 %34:sreg_128 = COPY killed %33
116 %35:vreg_128 = COPY killed %34
117 %31:vreg_128 = COPY killed %35
118 S_BRANCH %bb.11
119
120 bb.10:
121 successors: %bb.14(0x80000000)
122 %36:vreg_128 = COPY killed %29
123 S_BRANCH %bb.14
124
125 bb.11:
126 successors: %bb.13(0x40000000), %bb.12(0x40000000)
127 %37:vreg_128 = COPY killed %31
128 S_CBRANCH_SCC0 %bb.13, implicit undef $scc
129
130 bb.12:
131 successors: %bb.10(0x80000000)
132 %29:vreg_128 = COPY killed %37
133 S_BRANCH %bb.10
134
135 bb.13:
136 successors: %bb.10(0x80000000)
137 %29:vreg_128 = COPY killed %37
138 S_BRANCH %bb.10
139
140 bb.14:
141 successors: %bb.15(0x40000000), %bb.16(0x40000000)
142 %38:vgpr_32 = V_MAD_F32 0, killed %36.sub0, 0, target-flags(amdgpu-gotprel) 0, 0, 0, 0, 0, implicit $exec
143 %39:vgpr_32 = V_MAD_F32 0, killed %38, 0, 0, 0, 0, 0, 0, implicit $exec
144 %40:vgpr_32 = V_MAD_F32 0, killed %39, 0, -1090519040, 0, 1056964608, 0, 0, implicit $exec
145 %41:vgpr_32 = V_MAD_F32 0, killed %40, 0, 0, 0, -1090519040, 0, 0, implicit $exec
146 %42:vgpr_32 = V_CVT_I32_F32_e32 killed %41, implicit $exec
147 %43:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %44:sreg_128, 12, 0 :: (dereferenceable invariant load 4)
148 %45:vgpr_32 = V_MUL_LO_I32 killed %42, killed %43, implicit $exec
149 %46:vgpr_32 = V_LSHLREV_B32_e32 2, killed %45, implicit $exec
150 %47:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN killed %46, undef %48:sreg_128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from constant-pool, align 1, addrspace 4)
151 %49:sreg_64 = V_CMP_NE_U32_e64 0, killed %47, implicit $exec
152 %50:sreg_64 = COPY $exec, implicit-def $exec
153 %51:sreg_64 = S_AND_B64 %50, %49, implicit-def dead $scc
154 $exec = S_MOV_B64_term killed %51
155 SI_MASK_BRANCH %bb.16, implicit $exec
156 S_BRANCH %bb.15
157
158 bb.15:
159 successors: %bb.16(0x80000000)
160
161 bb.16:
162 successors: %bb.17(0x80000000)
163 $exec = S_OR_B64 $exec, killed %50, implicit-def $scc
164 S_BRANCH %bb.17
165
166 bb.17:
167 successors: %bb.21(0x40000000), %bb.18(0x40000000)
168 S_CBRANCH_SCC1 %bb.21, implicit undef $scc
169
170 bb.18:
171 successors: %bb.19(0x40000000), %bb.20(0x40000000)
172 S_CBRANCH_SCC1 %bb.19, implicit undef $scc
173 S_BRANCH %bb.20
174
175 bb.19:
176 successors: %bb.20(0x80000000)
177
178 bb.20:
179 successors: %bb.21(0x80000000)
180
181 bb.21:
182 S_ENDPGM
183 ...
0 # RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx803 -run-pass=simple-register-coalescing,rename-independent-subregs %s -o - | FileCheck -check-prefix=GCN %s
1
2 # This test is for a bug where the following happens:
3 #
4 # Inside the loop, %29.sub2 is used in a V_LSHLREV whose result is then used
5 # in an LDS read. %29 is a 128 bit value that is linked by copies to
6 # %45 (from phi elimination), %28 (the value in the loop pre-header),
7 # %31 (defined and subreg-modified in the loop, and used after the loop)
8 # and %30:
9 #
10 # %45:vreg_128 = COPY killed %28
11 # bb.1:
12 # %29:vreg_128 = COPY killed %45
13 # %39:vgpr_32 = V_LSHLREV_B32_e32 2, %29.sub2, implicit $exec
14 # %31:vreg_128 = COPY killed %29
15 # %31.sub1:vreg_128 = COPY %34
16 # %30:vreg_128 = COPY %31
17 # %45:vreg_128 = COPY killed %30
18 # S_CBRANCH_EXECNZ %bb.39, implicit $exec
19 # S_BRANCH %bb.40
20 # bb.2:
21 # undef %32.sub0:vreg_128 = COPY killed %31.sub0
22 #
23 # So this coalesces together into a single 128 bit value whose sub1 is modified
24 # in the loop, but the sub2 used in the V_LSHLREV is not modified in the loop.
25 #
26 # The bug is that the coalesced value has a L00000004 subrange (for sub2) that
27 # says that it is not live up to the end of the loop block. The symptom is that
28 # Rename Independent Subregs separates sub2 into its own register, and it is
29 # not live round the loop, so that pass adds an IMPLICIT_DEF for it just before
30 # the loop backedge.
31
32 # GCN: bb.1:
33 # GCN: V_LSHLREV_B32_e32 2, [[val:%[0-9][0-9]*]].sub2
34 # GCN-NOT: [[val]]:vreg_128 = IMPLICIT_DEF
35
36 ---
37 name: _amdgpu_cs_main
38 tracksRegLiveness: true
39 body: |
40 bb.0:
41 successors: %bb.1
42
43 %3:sgpr_32 = S_MOV_B32 0
44 undef %19.sub1:vreg_128 = COPY undef %3
45 %4:sgpr_32 = S_MOV_B32 1
46 %5:sgpr_32 = S_MOV_B32 2
47 %11:sreg_32_xm0 = S_MOV_B32 255
48 undef %28.sub0:vreg_128 = COPY killed %3
49 %28.sub1:vreg_128 = COPY killed %4
50 %28.sub2:vreg_128 = COPY killed %11
51 %28.sub3:vreg_128 = COPY killed %5
52 %2:sreg_64 = S_MOV_B64 0
53 %34:sreg_32 = S_MOV_B32 7
54 %37:vreg_128 = COPY undef %42:vreg_128
55 %43:sreg_64 = COPY killed %2
56 %44:vreg_128 = COPY killed %37
57 %45:vreg_128 = COPY killed %28
58
59 bb.1:
60 successors: %bb.1, %bb.2
61
62 %29:vreg_128 = COPY killed %45
63 %36:vreg_128 = COPY killed %44
64 %0:sreg_64 = COPY killed %43
65 %39:vgpr_32 = V_LSHLREV_B32_e32 2, %29.sub2, implicit $exec
66 %41:vgpr_32 = V_ADD_I32_e32 1152, %39, implicit-def dead $vcc, implicit $exec
67 $m0 = S_MOV_B32 -1
68 %12:vreg_64 = DS_READ2_B32 killed %41, 0, 1, 0, implicit $m0, implicit $exec
69 %13:vreg_64 = DS_READ2_B32 %39, -112, -111, 0, implicit $m0, implicit $exec
70 %14:vreg_64 = DS_READ2_B32 %39, 0, 1, 0, implicit $m0, implicit $exec
71 %40:vgpr_32 = V_ADD_I32_e32 1160, %39, implicit-def dead $vcc, implicit $exec
72 %15:vreg_64 = DS_READ2_B32 killed %40, 0, 1, 0, implicit $m0, implicit $exec
73 %16:vreg_64 = DS_READ2_B32 %39, -110, -109, 0, implicit $m0, implicit $exec
74 %17:vreg_64 = DS_READ2_B32 %39, 2, 3, 0, implicit $m0, implicit $exec
75 undef %35.sub1:vreg_128 = COPY undef %34
76 %31:vreg_128 = COPY killed %29
77 %31.sub1:vreg_128 = COPY %34
78 %38:vgpr_32 = V_ADD_I32_e32 1, %36.sub0, implicit-def dead $vcc, implicit $exec
79 %18:sreg_64 = V_CMP_LT_I32_e64 5, %38, implicit $exec
80 %1:sreg_64 = S_OR_B64 killed %18, killed %0, implicit-def $scc
81 %30:vreg_128 = COPY %31
82 %43:sreg_64 = COPY %1
83 %44:vreg_128 = COPY %35
84 %45:vreg_128 = COPY killed %30
85 $exec = S_ANDN2_B64_term $exec, %1
86 S_CBRANCH_EXECNZ %bb.1, implicit $exec
87 S_BRANCH %bb.2
88
89 bb.2:
90 $exec = S_OR_B64 $exec, killed %1, implicit-def $scc
91 %33:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
92 undef %32.sub0:vreg_128 = COPY killed %31.sub0
93 %32.sub2:vreg_128 = COPY %33
94 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %32:vreg_128
95 S_ENDPGM
96
97 ...