llvm.org GIT mirror llvm / cd775ce
Move callee-saved regs spills / reloads to TFI git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120228 91177308-0d34-0410-b5e6-96231b3b80d8 Anton Korobeynikov 9 years ago
27 changed file(s) with 639 addition(s) and 624 deletion(s). Raw diff Collapse all Expand all
1313 #ifndef LLVM_TARGET_TARGETFRAMEINFO_H
1414 #define LLVM_TARGET_TARGETFRAMEINFO_H
1515
16 #include "llvm/CodeGen/MachineBasicBlock.h"
17
1618 #include
1719 #include
1820
1921 namespace llvm {
22 class CalleeSavedInfo;
2023 class MachineFunction;
2124 class MachineBasicBlock;
2225 class MachineMove;
107110 virtual void emitEpilogue(MachineFunction &MF,
108111 MachineBasicBlock &MBB) const = 0;
109112
113 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
114 /// saved registers and returns true if it isn't possible / profitable to do
115 /// so by issuing a series of store instructions via
116 /// storeRegToStackSlot(). Returns false otherwise.
117 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
118 MachineBasicBlock::iterator MI,
119 const std::vector &CSI,
120 const TargetRegisterInfo *TRI) const {
121 return false;
122 }
123
124 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
125 /// saved registers and returns true if it isn't possible / profitable to do
126 /// so by issuing a series of load instructions via loadRegToStackSlot().
127 /// Returns false otherwise.
128 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
129 MachineBasicBlock::iterator MI,
130 const std::vector &CSI,
131 const TargetRegisterInfo *TRI) const {
132 return false;
133 }
134
110135 /// hasFP - Return true if the specified function should have a dedicated
111136 /// frame pointer register. For most targets this is true only if the function
112137 /// has variable sized allocas or if frame pointer elimination is disabled.
1818
1919 namespace llvm {
2020
21 class CalleeSavedInfo;
2221 class InstrItineraryData;
2322 class LiveVariables;
2423 class MCAsmInfo;
374373 const TargetRegisterInfo *TRI) const {
375374 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
376375 }
377
378 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
379 /// saved registers and returns true if it isn't possible / profitable to do
380 /// so by issuing a series of store instructions via
381 /// storeRegToStackSlot(). Returns false otherwise.
382 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
383 MachineBasicBlock::iterator MI,
384 const std::vector &CSI,
385 const TargetRegisterInfo *TRI) const {
386 return false;
387 }
388
389 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
390 /// saved registers and returns true if it isn't possible / profitable to do
391 /// so by issuing a series of load instructions via loadRegToStackSlot().
392 /// Returns false otherwise.
393 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
394 MachineBasicBlock::iterator MI,
395 const std::vector &CSI,
396 const TargetRegisterInfo *TRI) const {
397 return false;
398 }
399
376
400377 /// emitFrameIndexDebugValue - Emit a target-dependent form of
401378 /// DBG_VALUE encoding the address of a frame index. Addresses would
402379 /// normally be lowered the same way as other addresses on the target,
294294 return;
295295
296296 const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
297 const TargetFrameInfo *TFI = Fn.getTarget().getFrameInfo();
297298 const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo();
298299 MachineBasicBlock::iterator I;
299300
300301 if (! ShrinkWrapThisFunction) {
301302 // Spill using target interface.
302303 I = EntryBlock->begin();
303 if (!TII.spillCalleeSavedRegisters(*EntryBlock, I, CSI, TRI)) {
304 if (!TFI->spillCalleeSavedRegisters(*EntryBlock, I, CSI, TRI)) {
304305 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
305306 // Add the callee-saved register as live-in.
306307 // It's killed at the spill.
332333
333334 // Restore all registers immediately before the return and any
334335 // terminators that preceed it.
335 if (!TII.restoreCalleeSavedRegisters(*MBB, I, CSI, TRI)) {
336 if (!TFI->restoreCalleeSavedRegisters(*MBB, I, CSI, TRI)) {
336337 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
337338 unsigned Reg = CSI[i].getReg();
338339 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
194194 MFI->insert(MBBI, NewMIs[1]);
195195 MFI->insert(MBBI, NewMIs[0]);
196196 return NewMIs[0];
197 }
198
199 void
200 ARMBaseInstrInfo::emitPushInst(MachineBasicBlock &MBB,
201 MachineBasicBlock::iterator MI,
202 const std::vector &CSI, unsigned Opc,
203 bool(*Func)(unsigned, bool)) const {
204 MachineFunction &MF = *MBB.getParent();
205 DebugLoc DL;
206 if (MI != MBB.end()) DL = MI->getDebugLoc();
207
208 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
209 MIB.addReg(ARM::SP, getDefRegState(true));
210 MIB.addReg(ARM::SP);
211 AddDefaultPred(MIB);
212 bool NumRegs = false;
213 for (unsigned i = CSI.size(); i != 0; --i) {
214 unsigned Reg = CSI[i-1].getReg();
215 if (!(Func)(Reg, Subtarget.isTargetDarwin())) continue;
216
217 // Add the callee-saved register as live-in unless it's LR and
218 // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
219 // then it's already added to the function and entry block live-in sets.
220 bool isKill = true;
221 if (Reg == ARM::LR) {
222 if (MF.getFrameInfo()->isReturnAddressTaken() &&
223 MF.getRegInfo().isLiveIn(Reg))
224 isKill = false;
225 }
226
227 if (isKill)
228 MBB.addLiveIn(Reg);
229
230 NumRegs = true;
231 MIB.addReg(Reg, getKillRegState(isKill));
232 }
233
234 // It's illegal to emit push instruction without operands.
235 if (NumRegs)
236 MBB.insert(MI, &*MIB);
237 else
238 MF.DeleteMachineInstr(MIB);
239 }
240
241 bool
242 ARMBaseInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
243 MachineBasicBlock::iterator MI,
244 const std::vector &CSI,
245 const TargetRegisterInfo *TRI) const {
246 if (CSI.empty())
247 return false;
248
249 MachineFunction &MF = *MBB.getParent();
250 ARMFunctionInfo *AFI = MF.getInfo();
251 DebugLoc DL = MI->getDebugLoc();
252
253 unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD;
254 unsigned FltOpc = ARM::VSTMDDB_UPD;
255 emitPushInst(MBB, MI, CSI, PushOpc, &isARMArea1Register);
256 emitPushInst(MBB, MI, CSI, PushOpc, &isARMArea2Register);
257 emitPushInst(MBB, MI, CSI, FltOpc, &isARMArea3Register);
258
259 return true;
260 }
261
262 void
263 ARMBaseInstrInfo::emitPopInst(MachineBasicBlock &MBB,
264 MachineBasicBlock::iterator MI,
265 const std::vector &CSI, unsigned Opc,
266 bool isVarArg, bool(*Func)(unsigned, bool)) const {
267
268 MachineFunction &MF = *MBB.getParent();
269 ARMFunctionInfo *AFI = MF.getInfo();
270 DebugLoc DL = MI->getDebugLoc();
271
272 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
273 MIB.addReg(ARM::SP, getDefRegState(true));
274 MIB.addReg(ARM::SP);
275 AddDefaultPred(MIB);
276 bool NumRegs = false;
277 for (unsigned i = CSI.size(); i != 0; --i) {
278 unsigned Reg = CSI[i-1].getReg();
279 if (!(Func)(Reg, Subtarget.isTargetDarwin())) continue;
280
281 if (Reg == ARM::LR && !isVarArg) {
282 Reg = ARM::PC;
283 unsigned Opc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET;
284 (*MIB).setDesc(get(Opc));
285 MI = MBB.erase(MI);
286 }
287
288 MIB.addReg(Reg, RegState::Define);
289 NumRegs = true;
290 }
291
292 // It's illegal to emit pop instruction without operands.
293 if (NumRegs)
294 MBB.insert(MI, &*MIB);
295 else
296 MF.DeleteMachineInstr(MIB);
297 }
298
299 bool
300 ARMBaseInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
301 MachineBasicBlock::iterator MI,
302 const std::vector &CSI,
303 const TargetRegisterInfo *TRI) const {
304 if (CSI.empty())
305 return false;
306
307 MachineFunction &MF = *MBB.getParent();
308 ARMFunctionInfo *AFI = MF.getInfo();
309 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
310 DebugLoc DL = MI->getDebugLoc();
311
312 unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
313 unsigned FltOpc = ARM::VLDMDIA_UPD;
314 emitPopInst(MBB, MI, CSI, FltOpc, isVarArg, &isARMArea3Register);
315 emitPopInst(MBB, MI, CSI, PopOpc, isVarArg, &isARMArea2Register);
316 emitPopInst(MBB, MI, CSI, PopOpc, isVarArg, &isARMArea1Register);
317
318 return true;
319197 }
320198
321199
205205 virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
206206 const ARMSubtarget &getSubtarget() const { return Subtarget; }
207207
208 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
209 MachineBasicBlock::iterator MI,
210 const std::vector &CSI,
211 const TargetRegisterInfo *TRI) const;
212
213 bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
214 MachineBasicBlock::iterator MI,
215 const std::vector &CSI,
216 const TargetRegisterInfo *TRI) const;
217
218 private:
219 void emitPopInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
220 const std::vector &CSI, unsigned Opc,
221 bool isVarArg, bool(*Func)(unsigned, bool)) const;
222 void emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
223 const std::vector &CSI, unsigned Opc,
224 bool(*Func)(unsigned, bool)) const;
225
226
227208 public:
228209 // Branch analysis.
229210 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
173173 DPRCSSize += 8;
174174 }
175175 }
176
176
177177 // Move past area 1.
178178 if (GPRCS1Size > 0) MBBI++;
179
179
180180 // Set FP to point to the stack slot that contains the previous FP.
181181 // For Darwin, FP is R7, which has now been stored in spill area 1.
182182 // Otherwise, if this is not Darwin, all the callee-saved registers go
190190 .addFrameIndex(FramePtrSpillFI).addImm(0);
191191 AddDefaultCC(AddDefaultPred(MIB));
192192 }
193
193
194194 // Move past area 2.
195195 if (GPRCS2Size > 0) MBBI++;
196
196
197197 // Determine starting offsets of spill areas.
198198 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
199199 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
207207
208208 // Move past area 3.
209209 if (DPRCSSize > 0) MBBI++;
210
210
211211 NumBytes = DPRCSOffset;
212212 if (NumBytes) {
213213 // Adjust SP after all the callee-save spills.
491491 unsigned FrameReg;
492492 return getFrameIndexReference(MF, FI, FrameReg);
493493 }
494
495 void ARMFrameInfo::emitPushInst(MachineBasicBlock &MBB,
496 MachineBasicBlock::iterator MI,
497 const std::vector &CSI,
498 unsigned Opc,
499 bool(*Func)(unsigned, bool)) const {
500 MachineFunction &MF = *MBB.getParent();
501 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
502
503 DebugLoc DL;
504 if (MI != MBB.end()) DL = MI->getDebugLoc();
505
506 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(Opc));
507 MIB.addReg(ARM::SP, getDefRegState(true));
508 MIB.addReg(ARM::SP);
509 AddDefaultPred(MIB);
510 bool NumRegs = false;
511 for (unsigned i = CSI.size(); i != 0; --i) {
512 unsigned Reg = CSI[i-1].getReg();
513 if (!(Func)(Reg, STI.isTargetDarwin())) continue;
514
515 // Add the callee-saved register as live-in unless it's LR and
516 // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
517 // then it's already added to the function and entry block live-in sets.
518 bool isKill = true;
519 if (Reg == ARM::LR) {
520 if (MF.getFrameInfo()->isReturnAddressTaken() &&
521 MF.getRegInfo().isLiveIn(Reg))
522 isKill = false;
523 }
524
525 if (isKill)
526 MBB.addLiveIn(Reg);
527
528 NumRegs = true;
529 MIB.addReg(Reg, getKillRegState(isKill));
530 }
531
532 // It's illegal to emit push instruction without operands.
533 if (NumRegs)
534 MBB.insert(MI, &*MIB);
535 else
536 MF.DeleteMachineInstr(MIB);
537 }
538
539 bool ARMFrameInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
540 MachineBasicBlock::iterator MI,
541 const std::vector &CSI,
542 const TargetRegisterInfo *TRI) const {
543 if (CSI.empty())
544 return false;
545
546 MachineFunction &MF = *MBB.getParent();
547 ARMFunctionInfo *AFI = MF.getInfo();
548 DebugLoc DL = MI->getDebugLoc();
549
550 unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD;
551 unsigned FltOpc = ARM::VSTMDDB_UPD;
552 emitPushInst(MBB, MI, CSI, PushOpc, &isARMArea1Register);
553 emitPushInst(MBB, MI, CSI, PushOpc, &isARMArea2Register);
554 emitPushInst(MBB, MI, CSI, FltOpc, &isARMArea3Register);
555
556 return true;
557 }
558
559 void ARMFrameInfo::emitPopInst(MachineBasicBlock &MBB,
560 MachineBasicBlock::iterator MI,
561 const std::vector &CSI,
562 unsigned Opc, bool isVarArg,
563 bool(*Func)(unsigned, bool)) const {
564 MachineFunction &MF = *MBB.getParent();
565 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
566 ARMFunctionInfo *AFI = MF.getInfo();
567 DebugLoc DL = MI->getDebugLoc();
568
569 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(Opc));
570 MIB.addReg(ARM::SP, getDefRegState(true));
571 MIB.addReg(ARM::SP);
572 AddDefaultPred(MIB);
573 bool NumRegs = false;
574 for (unsigned i = CSI.size(); i != 0; --i) {
575 unsigned Reg = CSI[i-1].getReg();
576 if (!(Func)(Reg, STI.isTargetDarwin())) continue;
577
578 if (Reg == ARM::LR && !isVarArg) {
579 Reg = ARM::PC;
580 unsigned Opc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET;
581 (*MIB).setDesc(TII.get(Opc));
582 MI = MBB.erase(MI);
583 }
584
585 MIB.addReg(Reg, RegState::Define);
586 NumRegs = true;
587 }
588
589 // It's illegal to emit pop instruction without operands.
590 if (NumRegs)
591 MBB.insert(MI, &*MIB);
592 else
593 MF.DeleteMachineInstr(MIB);
594 }
595
596 bool ARMFrameInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
597 MachineBasicBlock::iterator MI,
598 const std::vector &CSI,
599 const TargetRegisterInfo *TRI) const {
600 if (CSI.empty())
601 return false;
602
603 MachineFunction &MF = *MBB.getParent();
604 ARMFunctionInfo *AFI = MF.getInfo();
605 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
606 DebugLoc DL = MI->getDebugLoc();
607
608 unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
609 unsigned FltOpc = ARM::VLDMDIA_UPD;
610 emitPopInst(MBB, MI, CSI, FltOpc, isVarArg, &isARMArea3Register);
611 emitPopInst(MBB, MI, CSI, PopOpc, isVarArg, &isARMArea2Register);
612 emitPopInst(MBB, MI, CSI, PopOpc, isVarArg, &isARMArea1Register);
613
614 return true;
615 }
3434 void emitPrologue(MachineFunction &MF) const;
3535 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
3636
37 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
38 MachineBasicBlock::iterator MI,
39 const std::vector &CSI,
40 const TargetRegisterInfo *TRI) const;
41
42 bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
43 MachineBasicBlock::iterator MI,
44 const std::vector &CSI,
45 const TargetRegisterInfo *TRI) const;
46
3747 bool hasFP(const MachineFunction &MF) const;
3848 bool hasReservedCallFrame(const MachineFunction &MF) const;
3949 bool canSimplifyCallFramePseudos(const MachineFunction &MF) const;
4353 unsigned &FrameReg, int SPAdj) const;
4454 int getFrameIndexOffset(const MachineFunction &MF, int FI) const;
4555
56 private:
57 void emitPopInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
58 const std::vector &CSI, unsigned Opc,
59 bool isVarArg, bool(*Func)(unsigned, bool)) const;
60 void emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
61 const std::vector &CSI, unsigned Opc,
62 bool(*Func)(unsigned, bool)) const;
4663 };
4764
4865 } // End llvm namespace
263263 MBB.erase(MBBI);
264264 }
265265 }
266
267 bool Thumb1FrameInfo::
268 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
269 MachineBasicBlock::iterator MI,
270 const std::vector &CSI,
271 const TargetRegisterInfo *TRI) const {
272 if (CSI.empty())
273 return false;
274
275 DebugLoc DL;
276 MachineFunction &MF = *MBB.getParent();
277 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
278
279 if (MI != MBB.end()) DL = MI->getDebugLoc();
280
281 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH));
282 AddDefaultPred(MIB);
283 for (unsigned i = CSI.size(); i != 0; --i) {
284 unsigned Reg = CSI[i-1].getReg();
285 bool isKill = true;
286
287 // Add the callee-saved register as live-in unless it's LR and
288 // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
289 // then it's already added to the function and entry block live-in sets.
290 if (Reg == ARM::LR) {
291 MachineFunction &MF = *MBB.getParent();
292 if (MF.getFrameInfo()->isReturnAddressTaken() &&
293 MF.getRegInfo().isLiveIn(Reg))
294 isKill = false;
295 }
296
297 if (isKill)
298 MBB.addLiveIn(Reg);
299
300 MIB.addReg(Reg, getKillRegState(isKill));
301 }
302 return true;
303 }
304
305 bool Thumb1FrameInfo::
306 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
307 MachineBasicBlock::iterator MI,
308 const std::vector &CSI,
309 const TargetRegisterInfo *TRI) const {
310 if (CSI.empty())
311 return false;
312
313 MachineFunction &MF = *MBB.getParent();
314 ARMFunctionInfo *AFI = MF.getInfo();
315 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
316
317 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
318 DebugLoc DL = MI->getDebugLoc();
319 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP));
320 AddDefaultPred(MIB);
321
322 bool NumRegs = false;
323 for (unsigned i = CSI.size(); i != 0; --i) {
324 unsigned Reg = CSI[i-1].getReg();
325 if (Reg == ARM::LR) {
326 // Special epilogue for vararg functions. See emitEpilogue
327 if (isVarArg)
328 continue;
329 Reg = ARM::PC;
330 (*MIB).setDesc(TII.get(ARM::tPOP_RET));
331 MI = MBB.erase(MI);
332 }
333 MIB.addReg(Reg, getDefRegState(true));
334 NumRegs = true;
335 }
336
337 // It's illegal to emit pop instruction without operands.
338 if (NumRegs)
339 MBB.insert(MI, &*MIB);
340 else
341 MF.DeleteMachineInstr(MIB);
342
343 return true;
344 }
3434 void emitPrologue(MachineFunction &MF) const;
3535 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
3636
37 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
38 MachineBasicBlock::iterator MI,
39 const std::vector &CSI,
40 const TargetRegisterInfo *TRI) const;
41 bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
42 MachineBasicBlock::iterator MI,
43 const std::vector &CSI,
44 const TargetRegisterInfo *TRI) const;
45
3746 bool hasReservedCallFrame(const MachineFunction &MF) const;
3847 };
3948
108108 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
109109 }
110110 }
111
112 bool Thumb1InstrInfo::
113 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
114 MachineBasicBlock::iterator MI,
115 const std::vector &CSI,
116 const TargetRegisterInfo *TRI) const {
117 if (CSI.empty())
118 return false;
119
120 DebugLoc DL;
121 if (MI != MBB.end()) DL = MI->getDebugLoc();
122
123 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
124 AddDefaultPred(MIB);
125 for (unsigned i = CSI.size(); i != 0; --i) {
126 unsigned Reg = CSI[i-1].getReg();
127 bool isKill = true;
128
129 // Add the callee-saved register as live-in unless it's LR and
130 // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
131 // then it's already added to the function and entry block live-in sets.
132 if (Reg == ARM::LR) {
133 MachineFunction &MF = *MBB.getParent();
134 if (MF.getFrameInfo()->isReturnAddressTaken() &&
135 MF.getRegInfo().isLiveIn(Reg))
136 isKill = false;
137 }
138
139 if (isKill)
140 MBB.addLiveIn(Reg);
141
142 MIB.addReg(Reg, getKillRegState(isKill));
143 }
144 return true;
145 }
146
147 bool Thumb1InstrInfo::
148 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
149 MachineBasicBlock::iterator MI,
150 const std::vector &CSI,
151 const TargetRegisterInfo *TRI) const {
152 MachineFunction &MF = *MBB.getParent();
153 ARMFunctionInfo *AFI = MF.getInfo();
154 if (CSI.empty())
155 return false;
156
157 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
158 DebugLoc DL = MI->getDebugLoc();
159 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::tPOP));
160 AddDefaultPred(MIB);
161
162 bool NumRegs = false;
163 for (unsigned i = CSI.size(); i != 0; --i) {
164 unsigned Reg = CSI[i-1].getReg();
165 if (Reg == ARM::LR) {
166 // Special epilogue for vararg functions. See emitEpilogue
167 if (isVarArg)
168 continue;
169 Reg = ARM::PC;
170 (*MIB).setDesc(get(ARM::tPOP_RET));
171 MI = MBB.erase(MI);
172 }
173 MIB.addReg(Reg, getDefRegState(true));
174 NumRegs = true;
175 }
176
177 // It's illegal to emit pop instruction without operands.
178 if (NumRegs)
179 MBB.insert(MI, &*MIB);
180 else
181 MF.DeleteMachineInstr(MIB);
182
183 return true;
184 }
3636 ///
3737 const Thumb1RegisterInfo &getRegisterInfo() const { return RI; }
3838
39 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
40 MachineBasicBlock::iterator MI,
41 const std::vector &CSI,
42 const TargetRegisterInfo *TRI) const;
43 bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
44 MachineBasicBlock::iterator MI,
45 const std::vector &CSI,
46 const TargetRegisterInfo *TRI) const;
47
4839 void copyPhysReg(MachineBasicBlock &MBB,
4940 MachineBasicBlock::iterator I, DebugLoc DL,
5041 unsigned DestReg, unsigned SrcReg,
173173 }
174174 }
175175 }
176
177 // FIXME: Can we eleminate these in favour of generic code?
178 bool
179 MSP430FrameInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
180 MachineBasicBlock::iterator MI,
181 const std::vector &CSI,
182 const TargetRegisterInfo *TRI) const {
183 if (CSI.empty())
184 return false;
185
186 DebugLoc DL;
187 if (MI != MBB.end()) DL = MI->getDebugLoc();
188
189 MachineFunction &MF = *MBB.getParent();
190 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
191 MSP430MachineFunctionInfo *MFI = MF.getInfo();
192 MFI->setCalleeSavedFrameSize(CSI.size() * 2);
193
194 for (unsigned i = CSI.size(); i != 0; --i) {
195 unsigned Reg = CSI[i-1].getReg();
196 // Add the callee-saved register as live-in. It's killed at the spill.
197 MBB.addLiveIn(Reg);
198 BuildMI(MBB, MI, DL, TII.get(MSP430::PUSH16r))
199 .addReg(Reg, RegState::Kill);
200 }
201 return true;
202 }
203
204 bool
205 MSP430FrameInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
206 MachineBasicBlock::iterator MI,
207 const std::vector &CSI,
208 const TargetRegisterInfo *TRI) const {
209 if (CSI.empty())
210 return false;
211
212 DebugLoc DL;
213 if (MI != MBB.end()) DL = MI->getDebugLoc();
214
215 MachineFunction &MF = *MBB.getParent();
216 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
217
218 for (unsigned i = 0, e = CSI.size(); i != e; ++i)
219 BuildMI(MBB, MI, DL, TII.get(MSP430::POP16r), CSI[i].getReg());
220
221 return true;
222 }
3434 void emitPrologue(MachineFunction &MF) const;
3535 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
3636
37 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
38 MachineBasicBlock::iterator MI,
39 const std::vector &CSI,
40 const TargetRegisterInfo *TRI) const;
41 bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
42 MachineBasicBlock::iterator MI,
43 const std::vector &CSI,
44 const TargetRegisterInfo *TRI) const;
45
3746 bool hasFP(const MachineFunction &MF) const;
3847 bool hasReservedCallFrame(const MachineFunction &MF) const;
3948 };
9898
9999 BuildMI(MBB, I, DL, get(Opc), DestReg)
100100 .addReg(SrcReg, getKillRegState(KillSrc));
101 }
102
103 bool
104 MSP430InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
105 MachineBasicBlock::iterator MI,
106 const std::vector &CSI,
107 const TargetRegisterInfo *TRI) const {
108 if (CSI.empty())
109 return false;
110
111 DebugLoc DL;
112 if (MI != MBB.end()) DL = MI->getDebugLoc();
113
114 MachineFunction &MF = *MBB.getParent();
115 MSP430MachineFunctionInfo *MFI = MF.getInfo();
116 MFI->setCalleeSavedFrameSize(CSI.size() * 2);
117
118 for (unsigned i = CSI.size(); i != 0; --i) {
119 unsigned Reg = CSI[i-1].getReg();
120 // Add the callee-saved register as live-in. It's killed at the spill.
121 MBB.addLiveIn(Reg);
122 BuildMI(MBB, MI, DL, get(MSP430::PUSH16r))
123 .addReg(Reg, RegState::Kill);
124 }
125 return true;
126 }
127
128 bool
129 MSP430InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
130 MachineBasicBlock::iterator MI,
131 const std::vector &CSI,
132 const TargetRegisterInfo *TRI) const {
133 if (CSI.empty())
134 return false;
135
136 DebugLoc DL;
137 if (MI != MBB.end()) DL = MI->getDebugLoc();
138
139 for (unsigned i = 0, e = CSI.size(); i != e; ++i)
140 BuildMI(MBB, MI, DL, get(MSP430::POP16r), CSI[i].getReg());
141
142 return true;
143101 }
144102
145103 unsigned MSP430InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
6565 const TargetRegisterClass *RC,
6666 const TargetRegisterInfo *TRI) const;
6767
68 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
69 MachineBasicBlock::iterator MI,
70 const std::vector &CSI,
71 const TargetRegisterInfo *TRI) const;
72 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
73 MachineBasicBlock::iterator MI,
74 const std::vector &CSI,
75 const TargetRegisterInfo *TRI) const;
76
7768 unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
7869
7970 // Branch folding goodness
2626
2727 using namespace llvm;
2828
29 SystemZFrameInfo::SystemZFrameInfo(const SystemZSubtarget &sti)
30 : TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 8, -160), STI(sti) {
31 // Fill the spill offsets map
32 static const unsigned SpillOffsTab[][2] = {
33 { SystemZ::R2D, 0x10 },
34 { SystemZ::R3D, 0x18 },
35 { SystemZ::R4D, 0x20 },
36 { SystemZ::R5D, 0x28 },
37 { SystemZ::R6D, 0x30 },
38 { SystemZ::R7D, 0x38 },
39 { SystemZ::R8D, 0x40 },
40 { SystemZ::R9D, 0x48 },
41 { SystemZ::R10D, 0x50 },
42 { SystemZ::R11D, 0x58 },
43 { SystemZ::R12D, 0x60 },
44 { SystemZ::R13D, 0x68 },
45 { SystemZ::R14D, 0x70 },
46 { SystemZ::R15D, 0x78 }
47 };
48
49 RegSpillOffsets.grow(SystemZ::NUM_TARGET_REGS);
50
51 for (unsigned i = 0, e = array_lengthof(SpillOffsTab); i != e; ++i)
52 RegSpillOffsets[SpillOffsTab[i][0]] = SpillOffsTab[i][1];
53 }
2954
3055 /// needsFP - Return true if the specified function should have a dedicated
3156 /// frame pointer register. This is true if the function has variable sized
196221
197222 return Offset;
198223 }
224
225 bool
226 SystemZFrameInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
227 MachineBasicBlock::iterator MI,
228 const std::vector &CSI,
229 const TargetRegisterInfo *TRI) const {
230 if (CSI.empty())
231 return false;
232
233 DebugLoc DL;
234 if (MI != MBB.end()) DL = MI->getDebugLoc();
235
236 MachineFunction &MF = *MBB.getParent();
237 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
238 SystemZMachineFunctionInfo *MFI = MF.getInfo();
239 unsigned CalleeFrameSize = 0;
240
241 // Scan the callee-saved and find the bounds of register spill area.
242 unsigned LowReg = 0, HighReg = 0, StartOffset = -1U, EndOffset = 0;
243 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
244 unsigned Reg = CSI[i].getReg();
245 if (!SystemZ::FP64RegClass.contains(Reg)) {
246 unsigned Offset = RegSpillOffsets[Reg];
247 CalleeFrameSize += 8;
248 if (StartOffset > Offset) {
249 LowReg = Reg; StartOffset = Offset;
250 }
251 if (EndOffset < Offset) {
252 HighReg = Reg; EndOffset = RegSpillOffsets[Reg];
253 }
254 }
255 }
256
257 // Save information for epilogue inserter.
258 MFI->setCalleeSavedFrameSize(CalleeFrameSize);
259 MFI->setLowReg(LowReg); MFI->setHighReg(HighReg);
260
261 // Save GPRs
262 if (StartOffset) {
263 // Build a store instruction. Use STORE MULTIPLE instruction if there are many
264 // registers to store, otherwise - just STORE.
265 MachineInstrBuilder MIB =
266 BuildMI(MBB, MI, DL, TII.get((LowReg == HighReg ?
267 SystemZ::MOV64mr : SystemZ::MOV64mrm)));
268
269 // Add store operands.
270 MIB.addReg(SystemZ::R15D).addImm(StartOffset);
271 if (LowReg == HighReg)
272 MIB.addReg(0);
273 MIB.addReg(LowReg, RegState::Kill);
274 if (LowReg != HighReg)
275 MIB.addReg(HighReg, RegState::Kill);
276
277 // Do a second scan adding regs as being killed by instruction
278 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
279 unsigned Reg = CSI[i].getReg();
280 // Add the callee-saved register as live-in. It's killed at the spill.
281 MBB.addLiveIn(Reg);
282 if (Reg != LowReg && Reg != HighReg)
283 MIB.addReg(Reg, RegState::ImplicitKill);
284 }
285 }
286
287 // Save FPRs
288 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
289 unsigned Reg = CSI[i].getReg();
290 if (SystemZ::FP64RegClass.contains(Reg)) {
291 MBB.addLiveIn(Reg);
292 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx(),
293 &SystemZ::FP64RegClass, TRI);
294 }
295 }
296
297 return true;
298 }
299
300 bool
301 SystemZFrameInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
302 MachineBasicBlock::iterator MI,
303 const std::vector &CSI,
304 const TargetRegisterInfo *TRI) const {
305 if (CSI.empty())
306 return false;
307
308 DebugLoc DL;
309 if (MI != MBB.end()) DL = MI->getDebugLoc();
310
311 MachineFunction &MF = *MBB.getParent();
312 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
313 SystemZMachineFunctionInfo *MFI = MF.getInfo();
314
315 // Restore FP registers
316 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
317 unsigned Reg = CSI[i].getReg();
318 if (SystemZ::FP64RegClass.contains(Reg))
319 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(),
320 &SystemZ::FP64RegClass, TRI);
321 }
322
323 // Restore GP registers
324 unsigned LowReg = MFI->getLowReg(), HighReg = MFI->getHighReg();
325 unsigned StartOffset = RegSpillOffsets[LowReg];
326
327 if (StartOffset) {
328 // Build a load instruction. Use LOAD MULTIPLE instruction if there are many
329 // registers to load, otherwise - just LOAD.
330 MachineInstrBuilder MIB =
331 BuildMI(MBB, MI, DL, TII.get((LowReg == HighReg ?
332 SystemZ::MOV64rm : SystemZ::MOV64rmm)));
333 // Add store operands.
334 MIB.addReg(LowReg, RegState::Define);
335 if (LowReg != HighReg)
336 MIB.addReg(HighReg, RegState::Define);
337
338 MIB.addReg(hasFP(MF) ? SystemZ::R11D : SystemZ::R15D);
339 MIB.addImm(StartOffset);
340 if (LowReg == HighReg)
341 MIB.addReg(0);
342
343 // Do a second scan adding regs as being defined by instruction
344 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
345 unsigned Reg = CSI[i].getReg();
346 if (Reg != LowReg && Reg != HighReg)
347 MIB.addReg(Reg, RegState::ImplicitDefine);
348 }
349 }
350
351 return true;
352 }
1616 #include "SystemZ.h"
1717 #include "SystemZSubtarget.h"
1818 #include "llvm/Target/TargetFrameInfo.h"
19 #include "llvm/ADT/IndexedMap.h"
1920
2021 namespace llvm {
2122 class SystemZSubtarget;
2223
2324 class SystemZFrameInfo : public TargetFrameInfo {
25 IndexedMap RegSpillOffsets;
2426 protected:
2527 const SystemZSubtarget &STI;
2628
2729 public:
28 explicit SystemZFrameInfo(const SystemZSubtarget &sti)
29 : TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 8, -160), STI(sti) {
30 }
30 explicit SystemZFrameInfo(const SystemZSubtarget &sti);
3131
3232 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
3333 /// the function.
3434 void emitPrologue(MachineFunction &MF) const;
3535 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
36
37 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
38 MachineBasicBlock::iterator MI,
39 const std::vector &CSI,
40 const TargetRegisterInfo *TRI) const;
41 bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
42 MachineBasicBlock::iterator MI,
43 const std::vector &CSI,
44 const TargetRegisterInfo *TRI) const;
3645
3746 bool hasReservedCallFrame(const MachineFunction &MF) const { return true; }
3847 bool hasFP(const MachineFunction &MF) const;
2727 SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm)
2828 : TargetInstrInfoImpl(SystemZInsts, array_lengthof(SystemZInsts)),
2929 RI(tm, *this), TM(tm) {
30 // Fill the spill offsets map
31 static const unsigned SpillOffsTab[][2] = {
32 { SystemZ::R2D, 0x10 },
33 { SystemZ::R3D, 0x18 },
34 { SystemZ::R4D, 0x20 },
35 { SystemZ::R5D, 0x28 },
36 { SystemZ::R6D, 0x30 },
37 { SystemZ::R7D, 0x38 },
38 { SystemZ::R8D, 0x40 },
39 { SystemZ::R9D, 0x48 },
40 { SystemZ::R10D, 0x50 },
41 { SystemZ::R11D, 0x58 },
42 { SystemZ::R12D, 0x60 },
43 { SystemZ::R13D, 0x68 },
44 { SystemZ::R14D, 0x70 },
45 { SystemZ::R15D, 0x78 }
46 };
47
48 RegSpillOffsets.grow(SystemZ::NUM_TARGET_REGS);
49
50 for (unsigned i = 0, e = array_lengthof(SpillOffsTab); i != e; ++i)
51 RegSpillOffsets[SpillOffsTab[i][0]] = SpillOffsTab[i][1];
5230 }
5331
5432 /// isGVStub - Return true if the GV requires an extra load to get the
210188 return 0;
211189 }
212190
213 bool
214 SystemZInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
215 MachineBasicBlock::iterator MI,
216 const std::vector &CSI,
217 const TargetRegisterInfo *TRI) const {
218 if (CSI.empty())
219 return false;
220
221 DebugLoc DL;
222 if (MI != MBB.end()) DL = MI->getDebugLoc();
223
224 MachineFunction &MF = *MBB.getParent();
225 SystemZMachineFunctionInfo *MFI = MF.getInfo();
226 unsigned CalleeFrameSize = 0;
227
228 // Scan the callee-saved and find the bounds of register spill area.
229 unsigned LowReg = 0, HighReg = 0, StartOffset = -1U, EndOffset = 0;
230 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
231 unsigned Reg = CSI[i].getReg();
232 if (!SystemZ::FP64RegClass.contains(Reg)) {
233 unsigned Offset = RegSpillOffsets[Reg];
234 CalleeFrameSize += 8;
235 if (StartOffset > Offset) {
236 LowReg = Reg; StartOffset = Offset;
237 }
238 if (EndOffset < Offset) {
239 HighReg = Reg; EndOffset = RegSpillOffsets[Reg];
240 }
241 }
242 }
243
244 // Save information for epilogue inserter.
245 MFI->setCalleeSavedFrameSize(CalleeFrameSize);
246 MFI->setLowReg(LowReg); MFI->setHighReg(HighReg);
247
248 // Save GPRs
249 if (StartOffset) {
250 // Build a store instruction. Use STORE MULTIPLE instruction if there are many
251 // registers to store, otherwise - just STORE.
252 MachineInstrBuilder MIB =
253 BuildMI(MBB, MI, DL, get((LowReg == HighReg ?
254 SystemZ::MOV64mr : SystemZ::MOV64mrm)));
255
256 // Add store operands.
257 MIB.addReg(SystemZ::R15D).addImm(StartOffset);
258 if (LowReg == HighReg)
259 MIB.addReg(0);
260 MIB.addReg(LowReg, RegState::Kill);
261 if (LowReg != HighReg)
262 MIB.addReg(HighReg, RegState::Kill);
263
264 // Do a second scan adding regs as being killed by instruction
265 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
266 unsigned Reg = CSI[i].getReg();
267 // Add the callee-saved register as live-in. It's killed at the spill.
268 MBB.addLiveIn(Reg);
269 if (Reg != LowReg && Reg != HighReg)
270 MIB.addReg(Reg, RegState::ImplicitKill);
271 }
272 }
273
274 // Save FPRs
275 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
276 unsigned Reg = CSI[i].getReg();
277 if (SystemZ::FP64RegClass.contains(Reg)) {
278 MBB.addLiveIn(Reg);
279 storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx(),
280 &SystemZ::FP64RegClass, &RI);
281 }
282 }
283
284 return true;
285 }
286
287 bool
288 SystemZInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
289 MachineBasicBlock::iterator MI,
290 const std::vector &CSI,
291 const TargetRegisterInfo *TRI) const {
292 if (CSI.empty())
293 return false;
294
295 DebugLoc DL;
296 if (MI != MBB.end()) DL = MI->getDebugLoc();
297
298 MachineFunction &MF = *MBB.getParent();
299 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
300 SystemZMachineFunctionInfo *MFI = MF.getInfo();
301
302 // Restore FP registers
303 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
304 unsigned Reg = CSI[i].getReg();
305 if (SystemZ::FP64RegClass.contains(Reg))
306 loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(),
307 &SystemZ::FP64RegClass, &RI);
308 }
309
310 // Restore GP registers
311 unsigned LowReg = MFI->getLowReg(), HighReg = MFI->getHighReg();
312 unsigned StartOffset = RegSpillOffsets[LowReg];
313
314 if (StartOffset) {
315 // Build a load instruction. Use LOAD MULTIPLE instruction if there are many
316 // registers to load, otherwise - just LOAD.
317 MachineInstrBuilder MIB =
318 BuildMI(MBB, MI, DL, get((LowReg == HighReg ?
319 SystemZ::MOV64rm : SystemZ::MOV64rmm)));
320 // Add store operands.
321 MIB.addReg(LowReg, RegState::Define);
322 if (LowReg != HighReg)
323 MIB.addReg(HighReg, RegState::Define);
324
325 MIB.addReg(TFI->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D);
326 MIB.addImm(StartOffset);
327 if (LowReg == HighReg)
328 MIB.addReg(0);
329
330 // Do a second scan adding regs as being defined by instruction
331 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
332 unsigned Reg = CSI[i].getReg();
333 if (Reg != LowReg && Reg != HighReg)
334 MIB.addReg(Reg, RegState::ImplicitDefine);
335 }
336 }
337
338 return true;
339 }
340
341191 bool SystemZInstrInfo::
342192 ReverseBranchCondition(SmallVectorImpl &Cond) const {
343193 assert(Cond.size() == 1 && "Invalid Xbranch condition!");
4949 class SystemZInstrInfo : public TargetInstrInfoImpl {
5050 const SystemZRegisterInfo RI;
5151 SystemZTargetMachine &TM;
52 IndexedMap RegSpillOffsets;
5352 public:
5453 explicit SystemZInstrInfo(SystemZTargetMachine &TM);
5554
7877 unsigned DestReg, int FrameIdx,
7978 const TargetRegisterClass *RC,
8079 const TargetRegisterInfo *TRI) const;
81
82 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
83 MachineBasicBlock::iterator MI,
84 const std::vector &CSI,
85 const TargetRegisterInfo *TRI) const;
86 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
87 MachineBasicBlock::iterator MI,
88 const std::vector &CSI,
89 const TargetRegisterInfo *TRI) const;
9080
9181 bool ReverseBranchCondition(SmallVectorImpl &Cond) const;
9282 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
798798
799799 return Offset;
800800 }
801
802 bool X86FrameInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
803 MachineBasicBlock::iterator MI,
804 const std::vector &CSI,
805 const TargetRegisterInfo *TRI) const {
806 if (CSI.empty())
807 return false;
808
809 DebugLoc DL = MBB.findDebugLoc(MI);
810
811 MachineFunction &MF = *MBB.getParent();
812
813 bool isWin64 = STI.isTargetWin64();
814 unsigned SlotSize = STI.is64Bit() ? 8 : 4;
815 unsigned FPReg = TRI->getFrameRegister(MF);
816 unsigned CalleeFrameSize = 0;
817
818 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
819 X86MachineFunctionInfo *X86FI = MF.getInfo();
820
821 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
822 for (unsigned i = CSI.size(); i != 0; --i) {
823 unsigned Reg = CSI[i-1].getReg();
824 // Add the callee-saved register as live-in. It's killed at the spill.
825 MBB.addLiveIn(Reg);
826 if (Reg == FPReg)
827 // X86RegisterInfo::emitPrologue will handle spilling of frame register.
828 continue;
829 if (!X86::VR128RegClass.contains(Reg) && !isWin64) {
830 CalleeFrameSize += SlotSize;
831 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill);
832 } else {
833 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
834 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(),
835 RC, TRI);
836 }
837 }
838
839 X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
840 return true;
841 }
842
843 bool X86FrameInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
844 MachineBasicBlock::iterator MI,
845 const std::vector &CSI,
846 const TargetRegisterInfo *TRI) const {
847 if (CSI.empty())
848 return false;
849
850 DebugLoc DL = MBB.findDebugLoc(MI);
851
852 MachineFunction &MF = *MBB.getParent();
853 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
854 unsigned FPReg = TRI->getFrameRegister(MF);
855 bool isWin64 = STI.isTargetWin64();
856 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
857 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
858 unsigned Reg = CSI[i].getReg();
859 if (Reg == FPReg)
860 // X86RegisterInfo::emitEpilogue will handle restoring of frame register.
861 continue;
862 if (!X86::VR128RegClass.contains(Reg) && !isWin64) {
863 BuildMI(MBB, MI, DL, TII.get(Opc), Reg);
864 } else {
865 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
866 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(),
867 RC, TRI);
868 }
869 }
870 return true;
871 }
3939 void emitPrologue(MachineFunction &MF) const;
4040 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
4141
42 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
43 MachineBasicBlock::iterator MI,
44 const std::vector &CSI,
45 const TargetRegisterInfo *TRI) const;
46
47 bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
48 MachineBasicBlock::iterator MI,
49 const std::vector &CSI,
50 const TargetRegisterInfo *TRI) const;
51
4252 bool hasFP(const MachineFunction &MF) const;
4353 bool hasReservedCallFrame(const MachineFunction &MF) const;
4454
21502150 NewMIs.push_back(MIB);
21512151 }
21522152
2153 bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
2154 MachineBasicBlock::iterator MI,
2155 const std::vector &CSI,
2156 const TargetRegisterInfo *TRI) const {
2157 if (CSI.empty())
2158 return false;
2159
2160 DebugLoc DL = MBB.findDebugLoc(MI);
2161
2162 bool is64Bit = TM.getSubtarget().is64Bit();
2163 bool isWin64 = TM.getSubtarget().isTargetWin64();
2164 unsigned SlotSize = is64Bit ? 8 : 4;
2165
2166 MachineFunction &MF = *MBB.getParent();
2167 unsigned FPReg = RI.getFrameRegister(MF);
2168 X86MachineFunctionInfo *X86FI = MF.getInfo();
2169 unsigned CalleeFrameSize = 0;
2170
2171 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
2172 for (unsigned i = CSI.size(); i != 0; --i) {
2173 unsigned Reg = CSI[i-1].getReg();
2174 // Add the callee-saved register as live-in. It's killed at the spill.
2175 MBB.addLiveIn(Reg);
2176 if (Reg == FPReg)
2177 // X86RegisterInfo::emitPrologue will handle spilling of frame register.
2178 continue;
2179 if (!X86::VR128RegClass.contains(Reg) && !isWin64) {
2180 CalleeFrameSize += SlotSize;
2181 BuildMI(MBB, MI, DL, get(Opc)).addReg(Reg, RegState::Kill);
2182 } else {
2183 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
2184 storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(),
2185 RC, &RI);
2186 }
2187 }
2188
2189 X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
2190 return true;
2191 }
2192
2193 bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
2194 MachineBasicBlock::iterator MI,
2195 const std::vector &CSI,
2196 const TargetRegisterInfo *TRI) const {
2197 if (CSI.empty())
2198 return false;
2199
2200 DebugLoc DL = MBB.findDebugLoc(MI);
2201
2202 MachineFunction &MF = *MBB.getParent();
2203 unsigned FPReg = RI.getFrameRegister(MF);
2204 bool is64Bit = TM.getSubtarget().is64Bit();
2205 bool isWin64 = TM.getSubtarget().isTargetWin64();
2206 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
2207 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2208 unsigned Reg = CSI[i].getReg();
2209 if (Reg == FPReg)
2210 // X86RegisterInfo::emitEpilogue will handle restoring of frame register.
2211 continue;
2212 if (!X86::VR128RegClass.contains(Reg) && !isWin64) {
2213 BuildMI(MBB, MI, DL, get(Opc), Reg);
2214 } else {
2215 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
2216 loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(),
2217 RC, &RI);
2218 }
2219 }
2220 return true;
2221 }
2222
22232153 MachineInstr*
22242154 X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
22252155 int FrameIx, uint64_t Offset,
741741 MachineInstr::mmo_iterator MMOBegin,
742742 MachineInstr::mmo_iterator MMOEnd,
743743 SmallVectorImpl &NewMIs) const;
744
745 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
746 MachineBasicBlock::iterator MI,
747 const std::vector &CSI,
748 const TargetRegisterInfo *TRI) const;
749
750 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
751 MachineBasicBlock::iterator MI,
752 const std::vector &CSI,
753 const TargetRegisterInfo *TRI) const;
754
755744 virtual
756745 MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
757746 int FrameIx, uint64_t Offset,
270270 MachineLocation Src(XCore::SP, 0);
271271 Moves.push_back(MachineMove(0, Dst, Src));
272272 }
273
274 bool XCoreFrameInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
275 MachineBasicBlock::iterator MI,
276 const std::vector &CSI,
277 const TargetRegisterInfo *TRI) const {
278 if (CSI.empty())
279 return true;
280
281 MachineFunction *MF = MBB.getParent();
282 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
283
284 XCoreFunctionInfo *XFI = MF->getInfo();
285 bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(*MF);
286
287 DebugLoc DL;
288 if (MI != MBB.end()) DL = MI->getDebugLoc();
289
290 for (std::vector::const_iterator it = CSI.begin();
291 it != CSI.end(); ++it) {
292 // Add the callee-saved register as live-in. It's killed at the spill.
293 MBB.addLiveIn(it->getReg());
294
295 unsigned Reg = it->getReg();
296 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
297 TII.storeRegToStackSlot(MBB, MI, Reg, true,
298 it->getFrameIdx(), RC, TRI);
299 if (emitFrameMoves) {
300 MCSymbol *SaveLabel = MF->getContext().CreateTempSymbol();
301 BuildMI(MBB, MI, DL, TII.get(XCore::PROLOG_LABEL)).addSym(SaveLabel);
302 XFI->getSpillLabels().push_back(std::make_pair(SaveLabel, *it));
303 }
304 }
305 return true;
306 }
307
308 bool XCoreFrameInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
309 MachineBasicBlock::iterator MI,
310 const std::vector &CSI,
311 const TargetRegisterInfo *TRI) const{
312 MachineFunction *MF = MBB.getParent();
313 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
314
315 bool AtStart = MI == MBB.begin();
316 MachineBasicBlock::iterator BeforeI = MI;
317 if (!AtStart)
318 --BeforeI;
319 for (std::vector::const_iterator it = CSI.begin();
320 it != CSI.end(); ++it) {
321 unsigned Reg = it->getReg();
322 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
323 TII.loadRegFromStackSlot(MBB, MI, it->getReg(), it->getFrameIdx(),
324 RC, TRI);
325 assert(MI != MBB.begin() &&
326 "loadRegFromStackSlot didn't insert any code!");
327 // Insert in reverse order. loadRegFromStackSlot can insert multiple
328 // instructions.
329 if (AtStart)
330 MI = MBB.begin();
331 else {
332 MI = BeforeI;
333 ++MI;
334 }
335 }
336 return true;
337 }
3030 void emitPrologue(MachineFunction &MF) const;
3131 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
3232
33 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
34 MachineBasicBlock::iterator MI,
35 const std::vector &CSI,
36 const TargetRegisterInfo *TRI) const;
37 bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
38 MachineBasicBlock::iterator MI,
39 const std::vector &CSI,
40 const TargetRegisterInfo *TRI) const;
41
3342 bool hasFP(const MachineFunction &MF) const;
3443
3544 void getInitialFrameState(std::vector &Moves) const;
383383 .addImm(0);
384384 }
385385
386 bool XCoreInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
387 MachineBasicBlock::iterator MI,
388 const std::vector &CSI,
389 const TargetRegisterInfo *TRI) const {
390 if (CSI.empty()) {
391 return true;
392 }
393 MachineFunction *MF = MBB.getParent();
394 XCoreFunctionInfo *XFI = MF->getInfo();
395
396 bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(*MF);
397
398 DebugLoc DL;
399 if (MI != MBB.end()) DL = MI->getDebugLoc();
400
401 for (std::vector::const_iterator it = CSI.begin();
402 it != CSI.end(); ++it) {
403 // Add the callee-saved register as live-in. It's killed at the spill.
404 MBB.addLiveIn(it->getReg());
405
406 unsigned Reg = it->getReg();
407 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
408 storeRegToStackSlot(MBB, MI, Reg, true,
409 it->getFrameIdx(), RC, &RI);
410 if (emitFrameMoves) {
411 MCSymbol *SaveLabel = MF->getContext().CreateTempSymbol();
412 BuildMI(MBB, MI, DL, get(XCore::PROLOG_LABEL)).addSym(SaveLabel);
413 XFI->getSpillLabels().push_back(std::make_pair(SaveLabel, *it));
414 }
415 }
416 return true;
417 }
418
419 bool XCoreInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
420 MachineBasicBlock::iterator MI,
421 const std::vector &CSI,
422 const TargetRegisterInfo *TRI) const
423 {
424 bool AtStart = MI == MBB.begin();
425 MachineBasicBlock::iterator BeforeI = MI;
426 if (!AtStart)
427 --BeforeI;
428 for (std::vector::const_iterator it = CSI.begin();
429 it != CSI.end(); ++it) {
430 unsigned Reg = it->getReg();
431 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
432 loadRegFromStackSlot(MBB, MI, it->getReg(),
433 it->getFrameIdx(),
434 RC, &RI);
435 assert(MI != MBB.begin() &&
436 "loadRegFromStackSlot didn't insert any code!");
437 // Insert in reverse order. loadRegFromStackSlot can insert multiple
438 // instructions.
439 if (AtStart)
440 MI = MBB.begin();
441 else {
442 MI = BeforeI;
443 ++MI;
444 }
445 }
446 return true;
447 }
448
449386 /// ReverseBranchCondition - Return the inverse opcode of the
450387 /// specified Branch instruction.
451388 bool XCoreInstrInfo::
452 ReverseBranchCondition(SmallVectorImpl &Cond) const
453 {
389 ReverseBranchCondition(SmallVectorImpl &Cond) const {
454390 assert((Cond.size() == 2) &&
455391 "Invalid XCore branch condition!");
456392 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm()));
7474 const TargetRegisterClass *RC,
7575 const TargetRegisterInfo *TRI) const;
7676
77 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
78 MachineBasicBlock::iterator MI,
79 const std::vector &CSI,
80 const TargetRegisterInfo *TRI) const;
81
82 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
83 MachineBasicBlock::iterator MI,
84 const std::vector &CSI,
85 const TargetRegisterInfo *TRI) const;
8677
8778 virtual bool ReverseBranchCondition(
8879 SmallVectorImpl &Cond) const;