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[X86] Also create+widen FMIN/FMAX nodes for v2f32. This happens in the HINT benchmark, where the SLP-vectorizer created v2f32 fcmp/select code. The "correct" solution would have been to teach the vectorizer cost model that v2f32 isn't legal (because really, it isn't), but if we can vectorize we might as well do so. We legalize these v2f32 FMIN/FMAX nodes by widening to v4f32 later on. v3f32 were already widened to v4f32 by the generic unroll-and-build-vector legalization. rdar://15763436 Differential Revision: http://reviews.llvm.org/D6557 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225691 91177308-0d34-0410-b5e6-96231b3b80d8 Ahmed Bougacha 5 years ago
2 changed file(s) with 54 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
1965719657 switch (N->getOpcode()) {
1965819658 default:
1965919659 llvm_unreachable("Do not know how to custom type legalize this operation!");
19660 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
19661 case X86ISD::FMINC:
19662 case X86ISD::FMIN:
19663 case X86ISD::FMAXC:
19664 case X86ISD::FMAX: {
19665 EVT VT = N->getValueType(0);
19666 if (VT != MVT::v2f32)
19667 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
19668 SDValue UNDEF = DAG.getUNDEF(VT);
19669 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19670 N->getOperand(0), UNDEF);
19671 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19672 N->getOperand(1), UNDEF);
19673 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
19674 return;
19675 }
1966019676 case ISD::SIGN_EXTEND_INREG:
1966119677 case ISD::ADDC:
1966219678 case ISD::ADDE:
2307623092 // instructions match the semantics of the common C idiom x
2307723093 // x<=y?x:y, because of how they handle negative zero (which can be
2307823094 // ignored in unsafe-math mode).
23095 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
2307923096 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
23080 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
23097 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
2308123098 (Subtarget->hasSSE2() ||
2308223099 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
2308323100 ISD::CondCode CC = cast(Cond.getOperand(2))->get();
988988 %min = select <4 x i1> %min_is_x, <4 x float> %x, <4 x float> %y
989989 ret <4 x float> %min
990990 }
991
992 ; UNSAFE-LABEL: test_maxps_illegal_v2f32:
993 ; UNSAFE-NEXT: maxps %xmm1, %xmm0
994 ; UNSAFE-NEXT: ret
995 define <2 x float> @test_maxps_illegal_v2f32(<2 x float> %x, <2 x float> %y) nounwind {
996 %max_is_x = fcmp oge <2 x float> %x, %y
997 %max = select <2 x i1> %max_is_x, <2 x float> %x, <2 x float> %y
998 ret <2 x float> %max
999 }
1000
1001 ; UNSAFE-LABEL: test_minps_illegal_v2f32:
1002 ; UNSAFE-NEXT: minps %xmm1, %xmm0
1003 ; UNSAFE-NEXT: ret
1004 define <2 x float> @test_minps_illegal_v2f32(<2 x float> %x, <2 x float> %y) nounwind {
1005 %min_is_x = fcmp ole <2 x float> %x, %y
1006 %min = select <2 x i1> %min_is_x, <2 x float> %x, <2 x float> %y
1007 ret <2 x float> %min
1008 }
1009
1010 ; UNSAFE-LABEL: test_maxps_illegal_v3f32:
1011 ; UNSAFE-NEXT: maxps %xmm1, %xmm0
1012 ; UNSAFE-NEXT: ret
1013 define <3 x float> @test_maxps_illegal_v3f32(<3 x float> %x, <3 x float> %y) nounwind {
1014 %max_is_x = fcmp oge <3 x float> %x, %y
1015 %max = select <3 x i1> %max_is_x, <3 x float> %x, <3 x float> %y
1016 ret <3 x float> %max
1017 }
1018
1019 ; UNSAFE-LABEL: test_minps_illegal_v3f32:
1020 ; UNSAFE-NEXT: minps %xmm1, %xmm0
1021 ; UNSAFE-NEXT: ret
1022 define <3 x float> @test_minps_illegal_v3f32(<3 x float> %x, <3 x float> %y) nounwind {
1023 %min_is_x = fcmp ole <3 x float> %x, %y
1024 %min = select <3 x i1> %min_is_x, <3 x float> %x, <3 x float> %y
1025 ret <3 x float> %min
1026 }