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[ARM] Add a batch of MVE integer instructions. This includes integer arithmetic of various kinds (add/sub/multiply, saturating and not), and the immediate forms of VMOV and VMVN that load an immediate into all lanes of a vector. Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62674 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363936 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Tatham 28 days ago
5 changed file(s) with 1127 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
15201520
15211521 // end of mve_bit instructions
15221522
1523 // start of MVE Integer instructions
1524
1525 class MVE_int size, list pattern=[]>
1526 : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm), NoItinerary,
1527 iname, suffix, "$Qd, $Qn, $Qm", vpred_r, "", pattern> {
1528 bits<4> Qd;
1529 bits<4> Qn;
1530 bits<4> Qm;
1531
1532 let Inst{22} = Qd{3};
1533 let Inst{21-20} = size;
1534 let Inst{19-17} = Qn{2-0};
1535 let Inst{15-13} = Qd{2-0};
1536 let Inst{7} = Qn{3};
1537 let Inst{6} = 0b1;
1538 let Inst{5} = Qm{3};
1539 let Inst{3-1} = Qm{2-0};
1540 }
1541
1542 class MVE_VMULt1 size, list pattern=[]>
1543 : MVE_int<"vmul", suffix, size, pattern> {
1544
1545 let Inst{28} = 0b0;
1546 let Inst{25-23} = 0b110;
1547 let Inst{16} = 0b0;
1548 let Inst{12-8} = 0b01001;
1549 let Inst{4} = 0b1;
1550 let Inst{0} = 0b0;
1551 }
1552
1553 def MVE_VMULt1i8 : MVE_VMULt1<"i8", 0b00>;
1554 def MVE_VMULt1i16 : MVE_VMULt1<"i16", 0b01>;
1555 def MVE_VMULt1i32 : MVE_VMULt1<"i32", 0b10>;
1556
1557 class MVE_VQxDMULH size, bit rounding,
1558 list pattern=[]>
1559 : MVE_int {
1560
1561 let Inst{28} = rounding;
1562 let Inst{25-23} = 0b110;
1563 let Inst{16} = 0b0;
1564 let Inst{12-8} = 0b01011;
1565 let Inst{4} = 0b0;
1566 let Inst{0} = 0b0;
1567 }
1568
1569 class MVE_VQDMULH size, list pattern=[]>
1570 : MVE_VQxDMULH<"vqdmulh", suffix, size, 0b0, pattern>;
1571 class MVE_VQRDMULH size, list pattern=[]>
1572 : MVE_VQxDMULH<"vqrdmulh", suffix, size, 0b1, pattern>;
1573
1574 def MVE_VQDMULHi8 : MVE_VQDMULH<"s8", 0b00>;
1575 def MVE_VQDMULHi16 : MVE_VQDMULH<"s16", 0b01>;
1576 def MVE_VQDMULHi32 : MVE_VQDMULH<"s32", 0b10>;
1577
1578 def MVE_VQRDMULHi8 : MVE_VQRDMULH<"s8", 0b00>;
1579 def MVE_VQRDMULHi16 : MVE_VQRDMULH<"s16", 0b01>;
1580 def MVE_VQRDMULHi32 : MVE_VQRDMULH<"s32", 0b10>;
1581
1582 class MVE_VADDSUB size, bit subtract,
1583 list pattern=[]>
1584 : MVE_int {
1585
1586 let Inst{28} = subtract;
1587 let Inst{25-23} = 0b110;
1588 let Inst{16} = 0b0;
1589 let Inst{12-8} = 0b01000;
1590 let Inst{4} = 0b0;
1591 let Inst{0} = 0b0;
1592 }
1593
1594 class MVE_VADD size, list pattern=[]>
1595 : MVE_VADDSUB<"vadd", suffix, size, 0b0, pattern>;
1596 class MVE_VSUB size, list pattern=[]>
1597 : MVE_VADDSUB<"vsub", suffix, size, 0b1, pattern>;
1598
1599 def MVE_VADDi8 : MVE_VADD<"i8", 0b00>;
1600 def MVE_VADDi16 : MVE_VADD<"i16", 0b01>;
1601 def MVE_VADDi32 : MVE_VADD<"i32", 0b10>;
1602
1603 def MVE_VSUBi8 : MVE_VSUB<"i8", 0b00>;
1604 def MVE_VSUBi16 : MVE_VSUB<"i16", 0b01>;
1605 def MVE_VSUBi32 : MVE_VSUB<"i32", 0b10>;
1606
1607 class MVE_VQADDSUB
1608 bits<2> size, list pattern=[]>
1609 : MVE_int {
1610
1611 let Inst{28} = U;
1612 let Inst{25-23} = 0b110;
1613 let Inst{16} = 0b0;
1614 let Inst{12-10} = 0b000;
1615 let Inst{9} = subtract;
1616 let Inst{8} = 0b0;
1617 let Inst{4} = 0b1;
1618 let Inst{0} = 0b0;
1619 }
1620
1621 class MVE_VQADD size, list pattern=[]>
1622 : MVE_VQADDSUB<"vqadd", suffix, U, 0b0, size, pattern>;
1623 class MVE_VQSUB size, list pattern=[]>
1624 : MVE_VQADDSUB<"vqsub", suffix, U, 0b1, size, pattern>;
1625
1626 def MVE_VQADDs8 : MVE_VQADD<"s8", 0b0, 0b00>;
1627 def MVE_VQADDs16 : MVE_VQADD<"s16", 0b0, 0b01>;
1628 def MVE_VQADDs32 : MVE_VQADD<"s32", 0b0, 0b10>;
1629 def MVE_VQADDu8 : MVE_VQADD<"u8", 0b1, 0b00>;
1630 def MVE_VQADDu16 : MVE_VQADD<"u16", 0b1, 0b01>;
1631 def MVE_VQADDu32 : MVE_VQADD<"u32", 0b1, 0b10>;
1632
1633 def MVE_VQSUBs8 : MVE_VQSUB<"s8", 0b0, 0b00>;
1634 def MVE_VQSUBs16 : MVE_VQSUB<"s16", 0b0, 0b01>;
1635 def MVE_VQSUBs32 : MVE_VQSUB<"s32", 0b0, 0b10>;
1636 def MVE_VQSUBu8 : MVE_VQSUB<"u8", 0b1, 0b00>;
1637 def MVE_VQSUBu16 : MVE_VQSUB<"u16", 0b1, 0b01>;
1638 def MVE_VQSUBu32 : MVE_VQSUB<"u32", 0b1, 0b10>;
1639
1640 class MVE_VABD_int size, list pattern=[]>
1641 : MVE_int<"vabd", suffix, size, pattern> {
1642
1643 let Inst{28} = U;
1644 let Inst{25-23} = 0b110;
1645 let Inst{16} = 0b0;
1646 let Inst{12-8} = 0b00111;
1647 let Inst{4} = 0b0;
1648 let Inst{0} = 0b0;
1649 }
1650
1651 def MVE_VABDs8 : MVE_VABD_int<"s8", 0b0, 0b00>;
1652 def MVE_VABDs16 : MVE_VABD_int<"s16", 0b0, 0b01>;
1653 def MVE_VABDs32 : MVE_VABD_int<"s32", 0b0, 0b10>;
1654 def MVE_VABDu8 : MVE_VABD_int<"u8", 0b1, 0b00>;
1655 def MVE_VABDu16 : MVE_VABD_int<"u16", 0b1, 0b01>;
1656 def MVE_VABDu32 : MVE_VABD_int<"u32", 0b1, 0b10>;
1657
1658 class MVE_VRHADD size, list pattern=[]>
1659 : MVE_int<"vrhadd", suffix, size, pattern> {
1660
1661 let Inst{28} = U;
1662 let Inst{25-23} = 0b110;
1663 let Inst{16} = 0b0;
1664 let Inst{12-8} = 0b00001;
1665 let Inst{4} = 0b0;
1666 let Inst{0} = 0b0;
1667 }
1668
1669 def MVE_VRHADDs8 : MVE_VRHADD<"s8", 0b0, 0b00>;
1670 def MVE_VRHADDs16 : MVE_VRHADD<"s16", 0b0, 0b01>;
1671 def MVE_VRHADDs32 : MVE_VRHADD<"s32", 0b0, 0b10>;
1672 def MVE_VRHADDu8 : MVE_VRHADD<"u8", 0b1, 0b00>;
1673 def MVE_VRHADDu16 : MVE_VRHADD<"u16", 0b1, 0b01>;
1674 def MVE_VRHADDu32 : MVE_VRHADD<"u32", 0b1, 0b10>;
1675
1676 class MVE_VHADDSUB
1677 bits<2> size, list pattern=[]>
1678 : MVE_int {
1679
1680 let Inst{28} = U;
1681 let Inst{25-23} = 0b110;
1682 let Inst{16} = 0b0;
1683 let Inst{12-10} = 0b000;
1684 let Inst{9} = subtract;
1685 let Inst{8} = 0b0;
1686 let Inst{4} = 0b0;
1687 let Inst{0} = 0b0;
1688 }
1689
1690 class MVE_VHADD size,
1691 list pattern=[]>
1692 : MVE_VHADDSUB<"vhadd", suffix, U, 0b0, size, pattern>;
1693 class MVE_VHSUB size,
1694 list pattern=[]>
1695 : MVE_VHADDSUB<"vhsub", suffix, U, 0b1, size, pattern>;
1696
1697 def MVE_VHADDs8 : MVE_VHADD<"s8", 0b0, 0b00>;
1698 def MVE_VHADDs16 : MVE_VHADD<"s16", 0b0, 0b01>;
1699 def MVE_VHADDs32 : MVE_VHADD<"s32", 0b0, 0b10>;
1700 def MVE_VHADDu8 : MVE_VHADD<"u8", 0b1, 0b00>;
1701 def MVE_VHADDu16 : MVE_VHADD<"u16", 0b1, 0b01>;
1702 def MVE_VHADDu32 : MVE_VHADD<"u32", 0b1, 0b10>;
1703
1704 def MVE_VHSUBs8 : MVE_VHSUB<"s8", 0b0, 0b00>;
1705 def MVE_VHSUBs16 : MVE_VHSUB<"s16", 0b0, 0b01>;
1706 def MVE_VHSUBs32 : MVE_VHSUB<"s32", 0b0, 0b10>;
1707 def MVE_VHSUBu8 : MVE_VHSUB<"u8", 0b1, 0b00>;
1708 def MVE_VHSUBu16 : MVE_VHSUB<"u16", 0b1, 0b01>;
1709 def MVE_VHSUBu32 : MVE_VHSUB<"u32", 0b1, 0b10>;
1710
1711 class MVE_VDUP pattern=[]>
1712 : MVE_p<(outs MQPR:$Qd), (ins rGPR:$Rt), NoItinerary,
1713 "vdup", suffix, "$Qd, $Rt", vpred_r, "", pattern> {
1714 bits<4> Qd;
1715 bits<4> Rt;
1716
1717 let Inst{28} = 0b0;
1718 let Inst{25-23} = 0b101;
1719 let Inst{22} = B;
1720 let Inst{21-20} = 0b10;
1721 let Inst{19-17} = Qd{2-0};
1722 let Inst{16} = 0b0;
1723 let Inst{15-12} = Rt;
1724 let Inst{11-8} = 0b1011;
1725 let Inst{7} = Qd{3};
1726 let Inst{6} = 0b0;
1727 let Inst{5} = E;
1728 let Inst{4-0} = 0b10000;
1729 }
1730
1731 def MVE_VDUP32 : MVE_VDUP<"32", 0b0, 0b0>;
1732 def MVE_VDUP16 : MVE_VDUP<"16", 0b0, 0b1>;
1733 def MVE_VDUP8 : MVE_VDUP<"8", 0b1, 0b0>;
1734
1735 class MVEIntSingleSrc size,
1736 list pattern=[]>
1737 : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qm), NoItinerary,
1738 iname, suffix, "$Qd, $Qm", vpred_r, "", pattern> {
1739 bits<4> Qd;
1740 bits<4> Qm;
1741
1742 let Inst{22} = Qd{3};
1743 let Inst{19-18} = size{1-0};
1744 let Inst{15-13} = Qd{2-0};
1745 let Inst{5} = Qm{3};
1746 let Inst{3-1} = Qm{2-0};
1747 }
1748
1749 class MVE_VCLSCLZ size,
1750 bit count_zeroes, list pattern=[]>
1751 : MVEIntSingleSrc {
1752
1753 let Inst{28} = 0b1;
1754 let Inst{25-23} = 0b111;
1755 let Inst{21-20} = 0b11;
1756 let Inst{17-16} = 0b00;
1757 let Inst{12-8} = 0b00100;
1758 let Inst{7} = count_zeroes;
1759 let Inst{6} = 0b1;
1760 let Inst{4} = 0b0;
1761 let Inst{0} = 0b0;
1762 }
1763
1764 def MVE_VCLSs8 : MVE_VCLSCLZ<"vcls", "s8", 0b00, 0b0>;
1765 def MVE_VCLSs16 : MVE_VCLSCLZ<"vcls", "s16", 0b01, 0b0>;
1766 def MVE_VCLSs32 : MVE_VCLSCLZ<"vcls", "s32", 0b10, 0b0>;
1767
1768 def MVE_VCLZs8 : MVE_VCLSCLZ<"vclz", "i8", 0b00, 0b1>;
1769 def MVE_VCLZs16 : MVE_VCLSCLZ<"vclz", "i16", 0b01, 0b1>;
1770 def MVE_VCLZs32 : MVE_VCLSCLZ<"vclz", "i32", 0b10, 0b1>;
1771
1772 class MVE_VABSNEG_int size, bit negate,
1773 list pattern=[]>
1774 : MVEIntSingleSrc {
1775
1776 let Inst{28} = 0b1;
1777 let Inst{25-23} = 0b111;
1778 let Inst{21-20} = 0b11;
1779 let Inst{17-16} = 0b01;
1780 let Inst{12-8} = 0b00011;
1781 let Inst{7} = negate;
1782 let Inst{6} = 0b1;
1783 let Inst{4} = 0b0;
1784 let Inst{0} = 0b0;
1785 }
1786
1787 def MVE_VABSs8 : MVE_VABSNEG_int<"vabs", "s8", 0b00, 0b0>;
1788 def MVE_VABSs16 : MVE_VABSNEG_int<"vabs", "s16", 0b01, 0b0>;
1789 def MVE_VABSs32 : MVE_VABSNEG_int<"vabs", "s32", 0b10, 0b0>;
1790
1791 def MVE_VNEGs8 : MVE_VABSNEG_int<"vneg", "s8", 0b00, 0b1>;
1792 def MVE_VNEGs16 : MVE_VABSNEG_int<"vneg", "s16", 0b01, 0b1>;
1793 def MVE_VNEGs32 : MVE_VABSNEG_int<"vneg", "s32", 0b10, 0b1>;
1794
1795 class MVE_VQABSNEG size,
1796 bit negate, list pattern=[]>
1797 : MVEIntSingleSrc {
1798
1799 let Inst{28} = 0b1;
1800 let Inst{25-23} = 0b111;
1801 let Inst{21-20} = 0b11;
1802 let Inst{17-16} = 0b00;
1803 let Inst{12-8} = 0b00111;
1804 let Inst{7} = negate;
1805 let Inst{6} = 0b1;
1806 let Inst{4} = 0b0;
1807 let Inst{0} = 0b0;
1808 }
1809
1810 def MVE_VQABSs8 : MVE_VQABSNEG<"vqabs", "s8", 0b00, 0b0>;
1811 def MVE_VQABSs16 : MVE_VQABSNEG<"vqabs", "s16", 0b01, 0b0>;
1812 def MVE_VQABSs32 : MVE_VQABSNEG<"vqabs", "s32", 0b10, 0b0>;
1813
1814 def MVE_VQNEGs8 : MVE_VQABSNEG<"vqneg", "s8", 0b00, 0b1>;
1815 def MVE_VQNEGs16 : MVE_VQABSNEG<"vqneg", "s16", 0b01, 0b1>;
1816 def MVE_VQNEGs32 : MVE_VQABSNEG<"vqneg", "s32", 0b10, 0b1>;
1817
1818 class MVE_mod_imm cmode, bit op,
1819 dag iops, list pattern=[]>
1820 : MVE_p<(outs MQPR:$Qd), iops, NoItinerary, iname, suffix, "$Qd, $imm",
1821 vpred_r, "", pattern> {
1822 bits<13> imm;
1823 bits<4> Qd;
1824
1825 let Inst{28} = imm{7};
1826 let Inst{25-23} = 0b111;
1827 let Inst{22} = Qd{3};
1828 let Inst{21-19} = 0b000;
1829 let Inst{18-16} = imm{6-4};
1830 let Inst{15-13} = Qd{2-0};
1831 let Inst{12} = 0b0;
1832 let Inst{11-8} = cmode{3-0};
1833 let Inst{7-6} = 0b01;
1834 let Inst{5} = op;
1835 let Inst{4} = 0b1;
1836 let Inst{3-0} = imm{3-0};
1837
1838 let DecoderMethod = "DecodeMVEModImmInstruction";
1839 }
1840
1841 let isReMaterializable = 1 in {
1842 let isAsCheapAsAMove = 1 in {
1843 def MVE_VMOVimmi8 : MVE_mod_imm<"vmov", "i8", {1,1,1,0}, 0b0, (ins nImmSplatI8:$imm)>;
1844 def MVE_VMOVimmi16 : MVE_mod_imm<"vmov", "i16", {1,0,?,0}, 0b0, (ins nImmSplatI16:$imm)> {
1845 let Inst{9} = imm{9};
1846 }
1847 def MVE_VMOVimmi32 : MVE_mod_imm<"vmov", "i32", {?,?,?,?}, 0b0, (ins nImmVMOVI32:$imm)> {
1848 let Inst{11-8} = imm{11-8};
1849 }
1850 def MVE_VMOVimmi64 : MVE_mod_imm<"vmov", "i64", {1,1,1,0}, 0b1, (ins nImmSplatI64:$imm)>;
1851 def MVE_VMOVimmf32 : MVE_mod_imm<"vmov", "f32", {1,1,1,1}, 0b0, (ins nImmVMOVF32:$imm)>;
1852 } // let isAsCheapAsAMove = 1
1853
1854 def MVE_VMVNimmi16 : MVE_mod_imm<"vmvn", "i16", {1,0,?,0}, 0b1, (ins nImmSplatI16:$imm)> {
1855 let Inst{9} = imm{9};
1856 }
1857 def MVE_VMVNimmi32 : MVE_mod_imm<"vmvn", "i32", {?,?,?,?}, 0b1, (ins nImmVMOVI32:$imm)> {
1858 let Inst{11-8} = imm{11-8};
1859 }
1860 } // let isReMaterializable = 1
1861
1862 class MVE_VMINMAXA size,
1863 bit bit_12, list pattern=[]>
1864 : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qd_src, MQPR:$Qm),
1865 NoItinerary, iname, suffix, "$Qd, $Qm", vpred_n, "$Qd = $Qd_src",
1866 pattern> {
1867 bits<4> Qd;
1868 bits<4> Qm;
1869
1870 let Inst{28} = 0b0;
1871 let Inst{25-23} = 0b100;
1872 let Inst{22} = Qd{3};
1873 let Inst{21-20} = 0b11;
1874 let Inst{19-18} = size;
1875 let Inst{17-16} = 0b11;
1876 let Inst{15-13} = Qd{2-0};
1877 let Inst{12} = bit_12;
1878 let Inst{11-6} = 0b111010;
1879 let Inst{5} = Qm{3};
1880 let Inst{4} = 0b0;
1881 let Inst{3-1} = Qm{2-0};
1882 let Inst{0} = 0b1;
1883 }
1884
1885 def MVE_VMAXAs8 : MVE_VMINMAXA<"vmaxa", "s8", 0b00, 0b0>;
1886 def MVE_VMAXAs16 : MVE_VMINMAXA<"vmaxa", "s16", 0b01, 0b0>;
1887 def MVE_VMAXAs32 : MVE_VMINMAXA<"vmaxa", "s32", 0b10, 0b0>;
1888
1889 def MVE_VMINAs8 : MVE_VMINMAXA<"vmina", "s8", 0b00, 0b1>;
1890 def MVE_VMINAs16 : MVE_VMINMAXA<"vmina", "s16", 0b01, 0b1>;
1891 def MVE_VMINAs32 : MVE_VMINMAXA<"vmina", "s32", 0b10, 0b1>;
1892
1893 // end of MVE Integer instructions
1894
15231895 class MVE_VPT size, dag iops, string asm, list pattern=[]>
15241896 : MVE_MI<(outs ), iops, NoItinerary, !strconcat("vpt", "${Mk}", ".", suffix), asm, "", pattern> {
15251897 bits<3> fc;
59615961 !(hasMVE() &&
59625962 (Mnemonic == "vmine" ||
59635963 Mnemonic == "vshle" || Mnemonic == "vshlt" || Mnemonic == "vshllt" ||
5964 Mnemonic == "vmvne" || Mnemonic == "vorne"))) {
5964 Mnemonic == "vmvne" || Mnemonic == "vorne" ||
5965 Mnemonic == "vnege" || Mnemonic == "vnegt" ||
5966 Mnemonic.startswith("vq")))) {
59655967 unsigned CC = ARMCondCodeFromString(Mnemonic.substr(Mnemonic.size()-2));
59665968 if (CC != ~0U) {
59675969 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
308308 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
309309 uint64_t Address, const void *Decoder);
310310 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
311 uint64_t Address, const void *Decoder);
312 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst,unsigned Val,
311313 uint64_t Address, const void *Decoder);
312314 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
313315 uint64_t Address, const void *Decoder);
34213423 return S;
34223424 }
34233425
3426 static DecodeStatus
3427 DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn,
3428 uint64_t Address, const void *Decoder) {
3429 DecodeStatus S = MCDisassembler::Success;
3430
3431 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
3432 fieldFromInstruction(Insn, 13, 3));
3433 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
3434 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3435 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3436 imm |= fieldFromInstruction(Insn, 28, 1) << 7;
3437 imm |= cmode << 8;
3438 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3439
3440 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32)
3441 return MCDisassembler::Fail;
3442
3443 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
3444 return MCDisassembler::Fail;
3445
3446 Inst.addOperand(MCOperand::createImm(imm));
3447
3448 Inst.addOperand(MCOperand::createImm(ARMVCC::None));
3449 Inst.addOperand(MCOperand::createReg(0));
3450 Inst.addOperand(MCOperand::createImm(0));
3451
3452 return S;
3453 }
3454
34243455 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
34253456 uint64_t Address, const void *Decoder) {
34263457 DecodeStatus S = MCDisassembler::Success;
0 # RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding %s 2>%t \
1 # RUN: | FileCheck --check-prefix=CHECK %s
2 # RUN: FileCheck --check-prefix=ERROR %s < %t
3
4 # CHECK: vmov.i32 q0, #0x1bff @ encoding: [0x81,0xef,0x5b,0x0c]
5 vmov.i32 q0, #0x1bff
6
7 # CHECK: vmov.i16 q0, #0x5c @ encoding: [0x85,0xef,0x5c,0x08]
8 vmov.i16 q0, #0x5c
9
10 # CHECK: vmov.i8 q0, #0x4c @ encoding: [0x84,0xef,0x5c,0x0e]
11 vmov.i8 q0, #0x4c
12
13 # CHECK: vmov.f32 q0, #-3.625000e+00 @ encoding: [0x80,0xff,0x5d,0x0f]
14 vmov.f32 q0, #-3.625000e+00
15
16 # CHECK: vmov.f32 q0, #1.250000e-01 @ encoding: [0x84,0xef,0x50,0x0f]
17 vmov.f32 q0, #0.125
18
19 # CHECK: vmov.f32 q0, #1.328125e-01 @ encoding: [0x84,0xef,0x51,0x0f]
20 vmov.f32 q0, #0.1328125
21
22 # CHECK: vmov.f32 q0, #3.100000e+01 @ encoding: [0x83,0xef,0x5f,0x0f]
23 vmov.f32 q0, #31.0
24
25 # CHECK: vmov.f32 s16, s1 @ encoding: [0xb0,0xee,0x60,0x8a]
26 vmov.f32 s16, s1
27
28 # CHECK: vmov.f64 d0, d1 @ encoding: [0xb0,0xee,0x41,0x0b]
29 vmov.f64 d0, d1
30
31 # CHECK: vmov.i64 q0, #0xff0000ffffffffff @ encoding: [0x81,0xff,0x7f,0x0e]
32 vmov.i64 q0, #0xff0000ffffffffff
33
34 # ERROR: [[@LINE+1]]:14: error: invalid operand for instruction
35 vmov.i32 q0, #0xabcd
36
37 # ERROR: [[@LINE+1]]:14: error: invalid operand for instruction
38 vmov.i16 q0, #0xabcd
39
40 # ERROR: [[@LINE+1]]:14: error: invalid operand for instruction
41 vmov.i32 q0, #0xabffffff
42
43 # ERROR: [[@LINE+1]]:14: error: invalid operand for instruction
44 vmov.i32 q0, #0xabffffff
45
46 # ERROR: [[@LINE+1]]:14: error: invalid operand for instruction
47 vmov.f32 q0, #0.0625
48
49 # ERROR: [[@LINE+1]]:14: error: invalid operand for instruction
50 vmov.f32 q0, #33.0
51
52 # CHECK: vmul.i8 q0, q0, q3 @ encoding: [0x00,0xef,0x56,0x09]
53 vmul.i8 q0, q0, q3
54
55 # CHECK: vmul.i16 q6, q0, q3 @ encoding: [0x10,0xef,0x56,0xc9]
56 vmul.i16 q6, q0, q3
57
58 # CHECK: vmul.i32 q7, q3, q6 @ encoding: [0x26,0xef,0x5c,0xe9]
59 vmul.i32 q7, q3, q6
60
61 # CHECK: vqrdmulh.s8 q0, q5, q5 @ encoding: [0x0a,0xff,0x4a,0x0b]
62 vqrdmulh.s8 q0, q5, q5
63
64 # CHECK: vqrdmulh.s16 q1, q4, q2 @ encoding: [0x18,0xff,0x44,0x2b]
65 vqrdmulh.s16 q1, q4, q2
66
67 # CHECK: vqrdmulh.s32 q0, q5, q0 @ encoding: [0x2a,0xff,0x40,0x0b]
68 vqrdmulh.s32 q0, q5, q0
69
70 # CHECK: vqdmulh.s8 q0, q4, q5 @ encoding: [0x08,0xef,0x4a,0x0b]
71 vqdmulh.s8 q0, q4, q5
72
73 # CHECK: vqdmulh.s16 q6, q4, q0 @ encoding: [0x18,0xef,0x40,0xcb]
74 vqdmulh.s16 q6, q4, q0
75
76 # CHECK: vqdmulh.s32 q5, q0, q6 @ encoding: [0x20,0xef,0x4c,0xab]
77 vqdmulh.s32 q5, q0, q6
78
79 # CHECK: vsub.i8 q3, q2, q5 @ encoding: [0x04,0xff,0x4a,0x68]
80 vsub.i8 q3, q2, q5
81
82 # CHECK: vsub.i16 q0, q3, q6 @ encoding: [0x16,0xff,0x4c,0x08]
83 vsub.i16 q0, q3, q6
84
85 # CHECK: vsub.i32 q0, q0, q6 @ encoding: [0x20,0xff,0x4c,0x08]
86 vsub.i32 q0, q0, q6
87
88 # CHECK: vadd.i8 q0, q2, q2 @ encoding: [0x04,0xef,0x44,0x08]
89 vadd.i8 q0, q2, q2
90
91 # CHECK: vadd.i16 q2, q2, q1 @ encoding: [0x14,0xef,0x42,0x48]
92 vadd.i16 q2, q2, q1
93
94 # CHECK: vadd.i32 q0, q0, q6 @ encoding: [0x20,0xef,0x4c,0x08]
95 vadd.i32 q0, q0, q6
96
97 # CHECK: vqsub.s8 q1, q6, q0 @ encoding: [0x0c,0xef,0x50,0x22]
98 vqsub.s8 q1, q6, q0
99
100 # CHECK: vqsub.s16 q0, q6, q1 @ encoding: [0x1c,0xef,0x52,0x02]
101 vqsub.s16 q0, q6, q1
102
103 # CHECK: vqsub.s32 q0, q0, q5 @ encoding: [0x20,0xef,0x5a,0x02]
104 vqsub.s32 q0, q0, q5
105
106 # CHECK: vqsub.u8 q0, q2, q6 @ encoding: [0x04,0xff,0x5c,0x02]
107 vqsub.u8 q0, q2, q6
108
109 # CHECK: vqsub.u16 q0, q7, q1 @ encoding: [0x1e,0xff,0x52,0x02]
110 vqsub.u16 q0, q7, q1
111
112 # CHECK: vqsub.u32 q1, q4, q7 @ encoding: [0x28,0xff,0x5e,0x22]
113 vqsub.u32 q1, q4, q7
114
115 # CHECK: vqadd.s8 q0, q1, q2 @ encoding: [0x02,0xef,0x54,0x00]
116 vqadd.s8 q0, q1, q2
117
118 # CHECK: vqadd.s8 q0, q4, q6 @ encoding: [0x08,0xef,0x5c,0x00]
119 vqadd.s8 q0, q4, q6
120
121 # CHECK: vqadd.s16 q0, q5, q5 @ encoding: [0x1a,0xef,0x5a,0x00]
122 vqadd.s16 q0, q5, q5
123
124 # CHECK: vqadd.s32 q0, q0, q4 @ encoding: [0x20,0xef,0x58,0x00]
125 vqadd.s32 q0, q0, q4
126
127 # CHECK: vqadd.u8 q0, q4, q2 @ encoding: [0x08,0xff,0x54,0x00]
128 vqadd.u8 q0, q4, q2
129
130 # CHECK: vqadd.u16 q4, q6, q6 @ encoding: [0x1c,0xff,0x5c,0x80]
131 vqadd.u16 q4, q6, q6
132
133 # CHECK: vqadd.u32 q0, q1, q2 @ encoding: [0x22,0xff,0x54,0x00]
134 vqadd.u32 q0, q1, q2
135
136 # CHECK: vabd.s8 q0, q0, q2 @ encoding: [0x00,0xef,0x44,0x07]
137 vabd.s8 q0, q0, q2
138
139 # CHECK: vabd.s16 q1, q5, q4 @ encoding: [0x1a,0xef,0x48,0x27]
140 vabd.s16 q1, q5, q4
141
142 # CHECK: vabd.s32 q2, q3, q2 @ encoding: [0x26,0xef,0x44,0x47]
143 vabd.s32 q2, q3, q2
144
145 # CHECK: vabd.u8 q1, q6, q4 @ encoding: [0x0c,0xff,0x48,0x27]
146 vabd.u8 q1, q6, q4
147
148 # CHECK: vabd.u16 q0, q6, q2 @ encoding: [0x1c,0xff,0x44,0x07]
149 vabd.u16 q0, q6, q2
150
151 # CHECK: vabd.u32 q0, q7, q4 @ encoding: [0x2e,0xff,0x48,0x07]
152 vabd.u32 q0, q7, q4
153
154 # CHECK: vrhadd.s8 q0, q1, q1 @ encoding: [0x02,0xef,0x42,0x01]
155 vrhadd.s8 q0, q1, q1
156
157 # CHECK: vrhadd.s16 q0, q1, q0 @ encoding: [0x12,0xef,0x40,0x01]
158 vrhadd.s16 q0, q1, q0
159
160 # CHECK: vrhadd.s32 q0, q4, q1 @ encoding: [0x28,0xef,0x42,0x01]
161 vrhadd.s32 q0, q4, q1
162
163 # CHECK: vrhadd.u8 q1, q0, q6 @ encoding: [0x00,0xff,0x4c,0x21]
164 vrhadd.u8 q1, q0, q6
165
166 # CHECK: vrhadd.u16 q2, q2, q5 @ encoding: [0x14,0xff,0x4a,0x41]
167 vrhadd.u16 q2, q2, q5
168
169 # CHECK: vrhadd.u32 q2, q3, q0 @ encoding: [0x26,0xff,0x40,0x41]
170 vrhadd.u32 q2, q3, q0
171
172 # CHECK: vhsub.s8 q0, q0, q2 @ encoding: [0x00,0xef,0x44,0x02]
173 vhsub.s8 q0, q0, q2
174
175 # CHECK: vhsub.s16 q1, q3, q1 @ encoding: [0x16,0xef,0x42,0x22]
176 vhsub.s16 q1, q3, q1
177
178 # CHECK: vhsub.s32 q0, q2, q5 @ encoding: [0x24,0xef,0x4a,0x02]
179 vhsub.s32 q0, q2, q5
180
181 # CHECK: vhsub.u8 q0, q4, q2 @ encoding: [0x08,0xff,0x44,0x02]
182 vhsub.u8 q0, q4, q2
183
184 # CHECK: vhsub.u16 q0, q7, q5 @ encoding: [0x1e,0xff,0x4a,0x02]
185 vhsub.u16 q0, q7, q5
186
187 # CHECK: vhsub.u32 q2, q6, q4 @ encoding: [0x2c,0xff,0x48,0x42]
188 vhsub.u32 q2, q6, q4
189
190 # CHECK: vhadd.s8 q0, q7, q0 @ encoding: [0x0e,0xef,0x40,0x00]
191 vhadd.s8 q0, q7, q0
192
193 # CHECK: vhadd.s16 q4, q0, q2 @ encoding: [0x10,0xef,0x44,0x80]
194 vhadd.s16 q4, q0, q2
195
196 # CHECK: vhadd.s32 q0, q3, q1 @ encoding: [0x26,0xef,0x42,0x00]
197 vhadd.s32 q0, q3, q1
198
199 # CHECK: vhadd.u8 q3, q0, q3 @ encoding: [0x00,0xff,0x46,0x60]
200 vhadd.u8 q3, q0, q3
201
202 # CHECK: vhadd.u16 q0, q1, q3 @ encoding: [0x12,0xff,0x46,0x00]
203 vhadd.u16 q0, q1, q3
204
205 # CHECK: vhadd.u32 q0, q1, q3 @ encoding: [0x22,0xff,0x46,0x00]
206 vhadd.u32 q0, q1, q3
207
208 # CHECK: vdup.8 q6, r8 @ encoding: [0xec,0xee,0x10,0x8b]
209 vdup.8 q6, r8
210
211 # CHECK: vdup.16 q7, lr @ encoding: [0xae,0xee,0x30,0xeb]
212 vdup.16 q7, lr
213
214 # CHECK: vdup.32 q1, r9 @ encoding: [0xa2,0xee,0x10,0x9b]
215 vdup.32 q1, r9
216
217 # CHECK: vpte.i8 eq, q0, q0
218 # CHECK: vdupt.16 q0, r1 @ encoding: [0xa0,0xee,0x30,0x1b]
219 # CHECK: vdupe.16 q0, r1 @ encoding: [0xa0,0xee,0x30,0x1b]
220 vpte.i8 eq, q0, q0
221 vdupt.16 q0, r1
222 vdupe.16 q0, r1
223
224 # CHECK: vcls.s8 q2, q1 @ encoding: [0xb0,0xff,0x42,0x44]
225 vcls.s8 q2, q1
226
227 # CHECK: vcls.s16 q0, q4 @ encoding: [0xb4,0xff,0x48,0x04]
228 vcls.s16 q0, q4
229
230 # CHECK: vcls.s32 q0, q0 @ encoding: [0xb8,0xff,0x40,0x04]
231 vcls.s32 q0, q0
232
233 # CHECK: vclz.i8 q0, q7 @ encoding: [0xb0,0xff,0xce,0x04]
234 vclz.i8 q0, q7
235
236 # CHECK: vclz.i16 q4, q7 @ encoding: [0xb4,0xff,0xce,0x84]
237 vclz.i16 q4, q7
238
239 # CHECK: vclz.i32 q7, q5 @ encoding: [0xb8,0xff,0xca,0xe4]
240 vclz.i32 q7, q5
241
242 # CHECK: vneg.s8 q1, q0 @ encoding: [0xb1,0xff,0xc0,0x23]
243 vneg.s8 q1, q0
244
245 # CHECK: vneg.s16 q0, q1 @ encoding: [0xb5,0xff,0xc2,0x03]
246 vneg.s16 q0, q1
247
248 # CHECK: vneg.s32 q7, q2 @ encoding: [0xb9,0xff,0xc4,0xe3]
249 vneg.s32 q7, q2
250
251 # CHECK: vabs.s8 q1, q1 @ encoding: [0xb1,0xff,0x42,0x23]
252 vabs.s8 q1, q1
253
254 # CHECK: vabs.s16 q0, q2 @ encoding: [0xb5,0xff,0x44,0x03]
255 vabs.s16 q0, q2
256
257 # CHECK: vabs.s32 q0, q7 @ encoding: [0xb9,0xff,0x4e,0x03]
258 vabs.s32 q0, q7
259
260 # CHECK: vqneg.s8 q0, q0 @ encoding: [0xb0,0xff,0xc0,0x07]
261 vqneg.s8 q0, q0
262
263 # CHECK: vqneg.s16 q6, q2 @ encoding: [0xb4,0xff,0xc4,0xc7]
264 vqneg.s16 q6, q2
265
266 # CHECK: vqneg.s32 q7, q2 @ encoding: [0xb8,0xff,0xc4,0xe7]
267 vqneg.s32 q7, q2
268
269 # CHECK: vqabs.s8 q2, q4 @ encoding: [0xb0,0xff,0x48,0x47]
270 vqabs.s8 q2, q4
271
272 # CHECK: vqabs.s16 q0, q2 @ encoding: [0xb4,0xff,0x44,0x07]
273 vqabs.s16 q0, q2
274
275 # CHECK: vqabs.s32 q0, q5 @ encoding: [0xb8,0xff,0x4a,0x07]
276 vqabs.s32 q0, q5
277
278 vpste
279 vnegt.s8 q0, q1
280 vnege.s8 q0, q1
281 # CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
282 # CHECK: vnegt.s8 q0, q1 @ encoding: [0xb1,0xff,0xc2,0x03]
283 # CHECK: vnege.s8 q0, q1 @ encoding: [0xb1,0xff,0xc2,0x03]
284
285 vpst
286 vqaddt.s16 q0, q1, q2
287 # CHECK: vpst @ encoding: [0x71,0xfe,0x4d,0x0f]
288 # CHECK: vqaddt.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x00]
289
290 vpste
291 vqnegt.s8 q0, q1
292 vqnege.s16 q0, q1
293 # CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
294 # CHECK: vqnegt.s8 q0, q1 @ encoding: [0xb0,0xff,0xc2,0x07]
295 # CHECK: vqnege.s16 q0, q1 @ encoding: [0xb4,0xff,0xc2,0x07]
296
297 # CHECK: vmina.s8 q1, q7 @ encoding: [0x33,0xee,0x8f,0x3e]
298 # CHECK-NOFP: vmina.s8 q1, q7 @ encoding: [0x33,0xee,0x8f,0x3e]
299 vmina.s8 q1, q7
300
301 # CHECK: vmina.s16 q1, q4 @ encoding: [0x37,0xee,0x89,0x3e]
302 # CHECK-NOFP: vmina.s16 q1, q4 @ encoding: [0x37,0xee,0x89,0x3e]
303 vmina.s16 q1, q4
304
305 # CHECK: vmina.s32 q0, q7 @ encoding: [0x3b,0xee,0x8f,0x1e]
306 # CHECK-NOFP: vmina.s32 q0, q7 @ encoding: [0x3b,0xee,0x8f,0x1e]
307 vmina.s32 q0, q7
308
309 # CHECK: vmaxa.s8 q0, q7 @ encoding: [0x33,0xee,0x8f,0x0e]
310 # CHECK-NOFP: vmaxa.s8 q0, q7 @ encoding: [0x33,0xee,0x8f,0x0e]
311 vmaxa.s8 q0, q7
312
313 # CHECK: vmaxa.s16 q1, q0 @ encoding: [0x37,0xee,0x81,0x2e]
314 # CHECK-NOFP: vmaxa.s16 q1, q0 @ encoding: [0x37,0xee,0x81,0x2e]
315 vmaxa.s16 q1, q0
316
317 # CHECK: vmaxa.s32 q1, q0 @ encoding: [0x3b,0xee,0x81,0x2e]
318 # CHECK-NOFP: vmaxa.s32 q1, q0 @ encoding: [0x3b,0xee,0x81,0x2e]
319 vmaxa.s32 q1, q0
0 # RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s 2>%t | FileCheck %s
1 # RUN: FileCheck --check-prefix=ERROR < %t %s
2 # RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t
3 # RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s
4
5 # CHECK: vmvn.i32 q0, #0x35 @ encoding: [0x83,0xef,0x75,0x00]
6 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
7 [0x83,0xef,0x75,0x00]
8
9 # CHECK: vmvn.i32 q0, #0x3500 @ encoding: [0x83,0xef,0x75,0x02]
10 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
11 [0x83,0xef,0x75,0x02]
12
13 # CHECK: vmvn.i32 q0, #0x350000 @ encoding: [0x83,0xef,0x75,0x04]
14 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
15 [0x83,0xef,0x75,0x04]
16
17 # CHECK: vmvn.i32 q0, #0x35000000 @ encoding: [0x83,0xef,0x75,0x06]
18 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
19 [0x83,0xef,0x75,0x06]
20
21 # CHECK: vmvn.i16 q0, #0x35 @ encoding: [0x83,0xef,0x75,0x08]
22 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
23 [0x83,0xef,0x75,0x08]
24
25 # CHECK: vmvn.i16 q0, #0x3500 @ encoding: [0x83,0xef,0x75,0x0a]
26 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
27 [0x83,0xef,0x75,0x0a]
28
29 # CHECK: vmvn.i32 q0, #0x35ff @ encoding: [0x83,0xef,0x75,0x0c]
30 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
31 [0x83,0xef,0x75,0x0c]
32
33 # CHECK: vmvn.i32 q0, #0x35ffff @ encoding: [0x83,0xef,0x75,0x0d]
34 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
35 [0x83,0xef,0x75,0x0d]
36
37 # CHECK: vmov.i64 q0, #0xffff00ff00ff @ encoding: [0x83,0xef,0x75,0x0e]
38 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
39 [0x83,0xef,0x75,0x0e]
40
41 # ERROR: [[@LINE+2]]:2: warning: invalid instruction encoding
42 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
43 [0x83,0xef,0x75,0x0f]
44
45 # CHECK: vmov.i32 q0, #0x1bff @ encoding: [0x81,0xef,0x5b,0x0c]
46 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
47 [0x81,0xef,0x5b,0x0c]
48
49 # ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
50 [0xc0,0xef,0x50,0x00]
51
52 # CHECK: vmov.i16 q0, #0x5c @ encoding: [0x85,0xef,0x5c,0x08]
53 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
54 [0x85,0xef,0x5c,0x08]
55
56 # CHECK: vmov.i8 q0, #0x4c @ encoding: [0x84,0xef,0x5c,0x0e]
57 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
58 [0x84,0xef,0x5c,0x0e]
59
60 # CHECK: vmov.f32 q0, #-3.625000e+00 @ encoding: [0x80,0xff,0x5d,0x0f]
61 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
62 [0x80,0xff,0x5d,0x0f]
63
64 # CHECK: vmov.f32 q0, #1.000000e+00 @ encoding: [0x87,0xef,0x50,0x0f]
65 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
66 [0x87,0xef,0x50,0x0f]
67
68 # CHECK: vmov.f32 s16, s1 @ encoding: [0xb0,0xee,0x60,0x8a]
69 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
70 [0xb0,0xee,0x60,0x8a]
71
72 # CHECK: vmov.f64 d0, d1 @ encoding: [0xb0,0xee,0x41,0x0b]
73 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
74 [0xb0,0xee,0x41,0x0b]
75
76 # CHECK: vmov.i64 q0, #0xff0000ffffffffff @ encoding: [0x81,0xff,0x7f,0x0e]
77 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
78 [0x81,0xff,0x7f,0x0e]
79
80 # CHECK: vmul.i8 q0, q0, q3 @ encoding: [0x00,0xef,0x56,0x09]
81 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
82 [0x00,0xef,0x56,0x09]
83
84 # CHECK: vmul.i16 q6, q0, q3 @ encoding: [0x10,0xef,0x56,0xc9]
85 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
86 [0x10,0xef,0x56,0xc9]
87
88 # CHECK: vmul.i32 q7, q3, q6 @ encoding: [0x26,0xef,0x5c,0xe9]
89 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
90 [0x26,0xef,0x5c,0xe9]
91
92 # CHECK: vqrdmulh.s8 q0, q5, q5 @ encoding: [0x0a,0xff,0x4a,0x0b]
93 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
94 [0x0a,0xff,0x4a,0x0b]
95
96 # CHECK: vqrdmulh.s16 q1, q4, q2 @ encoding: [0x18,0xff,0x44,0x2b]
97 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
98 [0x18,0xff,0x44,0x2b]
99
100 # CHECK: vqrdmulh.s32 q0, q5, q0 @ encoding: [0x2a,0xff,0x40,0x0b]
101 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
102 [0x2a,0xff,0x40,0x0b]
103
104 # CHECK: vqdmulh.s8 q0, q4, q5 @ encoding: [0x08,0xef,0x4a,0x0b]
105 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
106 [0x08,0xef,0x4a,0x0b]
107
108 # CHECK: vqdmulh.s16 q6, q4, q0 @ encoding: [0x18,0xef,0x40,0xcb]
109 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
110 [0x18,0xef,0x40,0xcb]
111
112 # CHECK: vqdmulh.s32 q5, q0, q6 @ encoding: [0x20,0xef,0x4c,0xab]
113 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
114 [0x20,0xef,0x4c,0xab]
115
116 # CHECK: vsub.i8 q3, q2, q5 @ encoding: [0x04,0xff,0x4a,0x68]
117 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
118 [0x04,0xff,0x4a,0x68]
119
120 # CHECK: vsub.i16 q0, q3, q6 @ encoding: [0x16,0xff,0x4c,0x08]
121 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
122 [0x16,0xff,0x4c,0x08]
123
124 # CHECK: vsub.i32 q0, q0, q6 @ encoding: [0x20,0xff,0x4c,0x08]
125 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
126 [0x20,0xff,0x4c,0x08]
127
128 # CHECK: vadd.i8 q0, q2, q2 @ encoding: [0x04,0xef,0x44,0x08]
129 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
130 [0x04,0xef,0x44,0x08]
131
132 # CHECK: vadd.i16 q2, q2, q1 @ encoding: [0x14,0xef,0x42,0x48]
133 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
134 [0x14,0xef,0x42,0x48]
135
136 # CHECK: vadd.i32 q0, q0, q6 @ encoding: [0x20,0xef,0x4c,0x08]
137 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
138 [0x20,0xef,0x4c,0x08]
139
140 # CHECK: vqsub.s8 q1, q6, q0 @ encoding: [0x0c,0xef,0x50,0x22]
141 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
142 [0x0c,0xef,0x50,0x22]
143
144 # CHECK: vqsub.s16 q0, q6, q1 @ encoding: [0x1c,0xef,0x52,0x02]
145 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
146 [0x1c,0xef,0x52,0x02]
147
148 # CHECK: vqsub.s32 q0, q0, q5 @ encoding: [0x20,0xef,0x5a,0x02]
149 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
150 [0x20,0xef,0x5a,0x02]
151
152 # CHECK: vqsub.u8 q0, q2, q6 @ encoding: [0x04,0xff,0x5c,0x02]
153 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
154 [0x04,0xff,0x5c,0x02]
155
156 # CHECK: vqsub.u16 q0, q7, q1 @ encoding: [0x1e,0xff,0x52,0x02]
157 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
158 [0x1e,0xff,0x52,0x02]
159
160 # CHECK: vqsub.u32 q1, q4, q7 @ encoding: [0x28,0xff,0x5e,0x22]
161 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
162 [0x28,0xff,0x5e,0x22]
163
164 # CHECK: vqadd.s8 q0, q4, q6 @ encoding: [0x08,0xef,0x5c,0x00]
165 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
166 [0x08,0xef,0x5c,0x00]
167
168 # CHECK: vqadd.s16 q0, q5, q5 @ encoding: [0x1a,0xef,0x5a,0x00]
169 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
170 [0x1a,0xef,0x5a,0x00]
171
172 # CHECK: vqadd.s32 q0, q0, q4 @ encoding: [0x20,0xef,0x58,0x00]
173 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
174 [0x20,0xef,0x58,0x00]
175
176 # CHECK: vqadd.u8 q0, q4, q2 @ encoding: [0x08,0xff,0x54,0x00]
177 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
178 [0x08,0xff,0x54,0x00]
179
180 # CHECK: vqadd.u16 q4, q6, q6 @ encoding: [0x1c,0xff,0x5c,0x80]
181 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
182 [0x1c,0xff,0x5c,0x80]
183
184 # CHECK: vqadd.u32 q0, q1, q2 @ encoding: [0x22,0xff,0x54,0x00]
185 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
186 [0x22,0xff,0x54,0x00]
187
188 # CHECK: vabd.s8 q0, q0, q2 @ encoding: [0x00,0xef,0x44,0x07]
189 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
190 [0x00,0xef,0x44,0x07]
191
192 # CHECK: vabd.s16 q1, q5, q4 @ encoding: [0x1a,0xef,0x48,0x27]
193 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
194 [0x1a,0xef,0x48,0x27]
195
196 # CHECK: vabd.s32 q2, q3, q2 @ encoding: [0x26,0xef,0x44,0x47]
197 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
198 [0x26,0xef,0x44,0x47]
199
200 # CHECK: vabd.u8 q1, q6, q4 @ encoding: [0x0c,0xff,0x48,0x27]
201 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
202 [0x0c,0xff,0x48,0x27]
203
204 # CHECK: vabd.u16 q0, q6, q2 @ encoding: [0x1c,0xff,0x44,0x07]
205 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
206 [0x1c,0xff,0x44,0x07]
207
208 # CHECK: vabd.u32 q0, q7, q4 @ encoding: [0x2e,0xff,0x48,0x07]
209 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
210 [0x2e,0xff,0x48,0x07]
211
212 # CHECK: vrhadd.s8 q0, q1, q1 @ encoding: [0x02,0xef,0x42,0x01]
213 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
214 [0x02,0xef,0x42,0x01]
215
216 # CHECK: vrhadd.s16 q0, q1, q0 @ encoding: [0x12,0xef,0x40,0x01]
217 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
218 [0x12,0xef,0x40,0x01]
219
220 # CHECK: vrhadd.s32 q0, q4, q1 @ encoding: [0x28,0xef,0x42,0x01]
221 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
222 [0x28,0xef,0x42,0x01]
223
224 # CHECK: vrhadd.u8 q1, q0, q6 @ encoding: [0x00,0xff,0x4c,0x21]
225 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
226 [0x00,0xff,0x4c,0x21]
227
228 # CHECK: vrhadd.u16 q2, q2, q5 @ encoding: [0x14,0xff,0x4a,0x41]
229 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
230 [0x14,0xff,0x4a,0x41]
231
232 # CHECK: vrhadd.u32 q2, q3, q0 @ encoding: [0x26,0xff,0x40,0x41]
233 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
234 [0x26,0xff,0x40,0x41]
235
236 # CHECK: vhsub.s8 q0, q0, q2 @ encoding: [0x00,0xef,0x44,0x02]
237 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
238 [0x00,0xef,0x44,0x02]
239
240 # CHECK: vhsub.s16 q1, q3, q1 @ encoding: [0x16,0xef,0x42,0x22]
241 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
242 [0x16,0xef,0x42,0x22]
243
244 # CHECK: vhsub.s32 q0, q2, q5 @ encoding: [0x24,0xef,0x4a,0x02]
245 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
246 [0x24,0xef,0x4a,0x02]
247
248 # CHECK: vhsub.u8 q0, q4, q2 @ encoding: [0x08,0xff,0x44,0x02]
249 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
250 [0x08,0xff,0x44,0x02]
251
252 # CHECK: vhsub.u16 q0, q7, q5 @ encoding: [0x1e,0xff,0x4a,0x02]
253 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
254 [0x1e,0xff,0x4a,0x02]
255
256 # CHECK: vhsub.u32 q2, q6, q4 @ encoding: [0x2c,0xff,0x48,0x42]
257 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
258 [0x2c,0xff,0x48,0x42]
259
260 # CHECK: vhadd.s8 q0, q7, q0 @ encoding: [0x0e,0xef,0x40,0x00]
261 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
262 [0x0e,0xef,0x40,0x00]
263
264 # CHECK: vhadd.s16 q4, q0, q2 @ encoding: [0x10,0xef,0x44,0x80]
265 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
266 [0x10,0xef,0x44,0x80]
267
268 # CHECK: vhadd.s32 q0, q3, q1 @ encoding: [0x26,0xef,0x42,0x00]
269 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
270 [0x26,0xef,0x42,0x00]
271
272 # CHECK: vhadd.u8 q3, q0, q3 @ encoding: [0x00,0xff,0x46,0x60]
273 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
274 [0x00,0xff,0x46,0x60]
275
276 # CHECK: vhadd.u16 q0, q1, q3 @ encoding: [0x12,0xff,0x46,0x00]
277 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
278 [0x12,0xff,0x46,0x00]
279
280 # CHECK: vhadd.u32 q0, q1, q3 @ encoding: [0x22,0xff,0x46,0x00]
281 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
282 [0x22,0xff,0x46,0x00]
283
284 # CHECK: vdup.8 q6, r8 @ encoding: [0xec,0xee,0x10,0x8b]
285 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
286 [0xec,0xee,0x10,0x8b]
287
288 # CHECK: vdup.16 q7, lr @ encoding: [0xae,0xee,0x30,0xeb]
289 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
290 [0xae,0xee,0x30,0xeb]
291
292 # CHECK: vdup.32 q1, r9 @ encoding: [0xa2,0xee,0x10,0x9b]
293 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
294 [0xa2,0xee,0x10,0x9b]
295
296 # CHECK: vpte.i8 eq, q0, q0 @ encoding: [0x41,0xfe,0x00,0x8f]
297 # CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
298 # CHECK: vdupt.16 q0, r1 @ encoding: [0xa0,0xee,0x30,0x1b]
299 # CHECK-NOMVE: [[@LINE+4]]:2: warning: invalid instruction encoding
300 # CHECK: vdupe.16 q0, r1 @ encoding: [0xa0,0xee,0x30,0x1b]
301 # CHECK-NOMVE: [[@LINE+3]]:2: warning: invalid instruction encoding
302 [0x41,0xfe,0x00,0x8f]
303 [0xa0,0xee,0x30,0x1b]
304 [0xa0,0xee,0x30,0x1b]
305
306 # CHECK: vcls.s8 q2, q1 @ encoding: [0xb0,0xff,0x42,0x44]
307 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
308 [0xb0,0xff,0x42,0x44]
309
310 # CHECK: vcls.s16 q0, q4 @ encoding: [0xb4,0xff,0x48,0x04]
311 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
312 [0xb4,0xff,0x48,0x04]
313
314 # CHECK: vcls.s32 q0, q0 @ encoding: [0xb8,0xff,0x40,0x04]
315 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
316 [0xb8,0xff,0x40,0x04]
317
318 # CHECK: vclz.i8 q0, q7 @ encoding: [0xb0,0xff,0xce,0x04]
319 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
320 [0xb0,0xff,0xce,0x04]
321
322 # CHECK: vclz.i16 q4, q7 @ encoding: [0xb4,0xff,0xce,0x84]
323 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
324 [0xb4,0xff,0xce,0x84]
325
326 # CHECK: vclz.i32 q7, q5 @ encoding: [0xb8,0xff,0xca,0xe4]
327 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
328 [0xb8,0xff,0xca,0xe4]
329
330 # CHECK: vneg.s8 q1, q0 @ encoding: [0xb1,0xff,0xc0,0x23]
331 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
332 [0xb1,0xff,0xc0,0x23]
333
334 # CHECK: vneg.s16 q0, q1 @ encoding: [0xb5,0xff,0xc2,0x03]
335 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
336 [0xb5,0xff,0xc2,0x03]
337
338 # CHECK: vneg.s32 q7, q2 @ encoding: [0xb9,0xff,0xc4,0xe3]
339 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
340 [0xb9,0xff,0xc4,0xe3]
341
342 # CHECK: vabs.s8 q1, q1 @ encoding: [0xb1,0xff,0x42,0x23]
343 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
344 [0xb1,0xff,0x42,0x23]
345
346 # CHECK: vabs.s16 q0, q2 @ encoding: [0xb5,0xff,0x44,0x03]
347 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
348 [0xb5,0xff,0x44,0x03]
349
350 # CHECK: vabs.s32 q0, q7 @ encoding: [0xb9,0xff,0x4e,0x03]
351 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
352 [0xb9,0xff,0x4e,0x03]
353
354 # CHECK: vqneg.s8 q0, q0 @ encoding: [0xb0,0xff,0xc0,0x07]
355 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
356 [0xb0,0xff,0xc0,0x07]
357
358 # CHECK: vqneg.s16 q6, q2 @ encoding: [0xb4,0xff,0xc4,0xc7]
359 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
360 [0xb4,0xff,0xc4,0xc7]
361
362 # CHECK: vqneg.s32 q7, q2 @ encoding: [0xb8,0xff,0xc4,0xe7]
363 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
364 [0xb8,0xff,0xc4,0xe7]
365
366 # CHECK: vqabs.s8 q2, q4 @ encoding: [0xb0,0xff,0x48,0x47]
367 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
368 [0xb0,0xff,0x48,0x47]
369
370 # CHECK: vqabs.s16 q0, q2 @ encoding: [0xb4,0xff,0x44,0x07]
371 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
372 [0xb4,0xff,0x44,0x07]
373
374 # CHECK: vqabs.s32 q0, q5 @ encoding: [0xb8,0xff,0x4a,0x07]
375 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
376 [0xb8,0xff,0x4a,0x07]
377
378 # CHECK: vmina.s8 q1, q7 @ encoding: [0x33,0xee,0x8f,0x3e]
379 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
380 [0x33,0xee,0x8f,0x3e]
381
382 # CHECK: vmina.s16 q1, q4 @ encoding: [0x37,0xee,0x89,0x3e]
383 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
384 [0x37,0xee,0x89,0x3e]
385
386 # CHECK: vmina.s32 q0, q7 @ encoding: [0x3b,0xee,0x8f,0x1e]
387 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
388 [0x3b,0xee,0x8f,0x1e]
389
390 # CHECK: vmaxa.s8 q0, q7 @ encoding: [0x33,0xee,0x8f,0x0e]
391 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
392 [0x33,0xee,0x8f,0x0e]
393
394 # CHECK: vmaxa.s16 q1, q0 @ encoding: [0x37,0xee,0x81,0x2e]
395 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
396 [0x37,0xee,0x81,0x2e]
397
398 # CHECK: vmaxa.s32 q1, q0 @ encoding: [0x3b,0xee,0x81,0x2e]
399 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
400 [0x3b,0xee,0x81,0x2e]