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Merging r214463: ------------------------------------------------------------------------ r214463 | thomas.stellard | 2014-07-31 20:32:28 -0400 (Thu, 31 Jul 2014) | 7 lines R600/SI: Fix incorrect commute operation in shrink instructions pass We were commuting the instruction by still shrinking it using the original opcode. NOTE: This is a candidate for the 3.5 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_35@214894 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 5 years ago
4 changed file(s) with 57 addition(s) and 3 deletion(s). Raw diff Collapse all Expand all
573573 return false;
574574
575575 return RI.regClassCanUseImmediate(OpInfo.RegClass);
576 }
577
578 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
579 return AMDGPU::getVOPe32(Opcode) != -1;
576580 }
577581
578582 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
108108 bool isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
109109 const MachineOperand &MO) const;
110110
111 /// \brief Return true if this 64-bit VALU instruction has a 32-bit encoding.
112 /// This function will return false if you pass it a 32-bit instruction.
113 bool hasVALU32BitEncoding(unsigned Opcode) const;
114
111115 bool verifyInstruction(const MachineInstr *MI,
112116 StringRef &ErrInfo) const override;
113117
124124 Next = std::next(I);
125125 MachineInstr &MI = *I;
126126
127 int Op32 = AMDGPU::getVOPe32(MI.getOpcode());
128
129 if (Op32 == -1)
127 if (!TII->hasVALU32BitEncoding(MI.getOpcode()))
130128 continue;
131129
132130 if (!canShrink(MI, TII, TRI, MRI)) {
136134 !canShrink(MI, TII, TRI, MRI))
137135 continue;
138136 }
137
138 int Op32 = AMDGPU::getVOPe32(MI.getOpcode());
139
140 // Op32 could be -1 here if we started with an instruction that had a
141 // a 32-bit encoding and then commuted it to an instruction that did not.
142 if (Op32 == -1)
143 continue;
139144
140145 if (TII->isVOPC(Op32)) {
141146 unsigned DstReg = MI.getOperand(0).getReg();
0 ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
1 ; XXX: This testis for a bug in the SIShrinkInstruction pass and it will be
2 ; relevant once we are selecting 64-bit instructions. We are
3 ; currently selecting mostly 32-bit instruction, so the
4 ; SIShrinkInstructions pass isn't doing much.
5 ; XFAIL: *
6
7 ; Test that we correctly commute a sub instruction
8 ; FUNC-LABEL: @sub_rev
9 ; SI-NOT: V_SUB_I32_e32 v{{[0-9]+}}, s
10 ; SI: V_SUBREV_I32_e32 v{{[0-9]+}}, s
11
12 ; ModuleID = 'vop-shrink.ll'
13
14 define void @sub_rev(i32 addrspace(1)* %out, <4 x i32> %sgpr, i32 %cond) {
15 entry:
16 %vgpr = call i32 @llvm.r600.read.tidig.x() #1
17 %tmp = icmp eq i32 %cond, 0
18 br i1 %tmp, label %if, label %else
19
20 if: ; preds = %entry
21 %tmp1 = getelementptr i32 addrspace(1)* %out, i32 1
22 %tmp2 = extractelement <4 x i32> %sgpr, i32 1
23 store i32 %tmp2, i32 addrspace(1)* %out
24 br label %endif
25
26 else: ; preds = %entry
27 %tmp3 = extractelement <4 x i32> %sgpr, i32 2
28 %tmp4 = sub i32 %vgpr, %tmp3
29 store i32 %tmp4, i32 addrspace(1)* %out
30 br label %endif
31
32 endif: ; preds = %else, %if
33 ret void
34 }
35
36 ; Function Attrs: nounwind readnone
37 declare i32 @llvm.r600.read.tidig.x() #0
38
39 attributes #0 = { nounwind readnone }
40 attributes #1 = { readnone }