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[RISCV][NFC] Split out emitSelectPseudo from EmitInstrWithCustomInserter It's cleaner and more consistent to have a separate helper function here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355772 91177308-0d34-0410-b5e6-96231b3b80d8 Alex Bradbury 1 year, 8 months ago
1 changed file(s) with 19 addition(s) and 16 deletion(s). Raw diff Collapse all Expand all
786786 return BB;
787787 }
788788
789 MachineBasicBlock *
790 RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
791 MachineBasicBlock *BB) const {
792 switch (MI.getOpcode()) {
793 default:
794 llvm_unreachable("Unexpected instr type to insert");
795 case RISCV::Select_GPR_Using_CC_GPR:
796 case RISCV::Select_FPR32_Using_CC_GPR:
797 case RISCV::Select_FPR64_Using_CC_GPR:
798 break;
799 case RISCV::BuildPairF64Pseudo:
800 return emitBuildPairF64Pseudo(MI, BB);
801 case RISCV::SplitF64Pseudo:
802 return emitSplitF64Pseudo(MI, BB);
803 }
804
789 static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
790 MachineBasicBlock *BB) {
805791 // To "insert" a SELECT instruction, we actually have to insert the triangle
806792 // control-flow pattern. The incoming instruction knows the destination vreg
807793 // to set, the condition code register to branch on, the true/false values to
859845
860846 MI.eraseFromParent(); // The pseudo instruction is gone now.
861847 return TailMBB;
848 }
849
850 MachineBasicBlock *
851 RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
852 MachineBasicBlock *BB) const {
853 switch (MI.getOpcode()) {
854 default:
855 llvm_unreachable("Unexpected instr type to insert");
856 case RISCV::Select_GPR_Using_CC_GPR:
857 case RISCV::Select_FPR32_Using_CC_GPR:
858 case RISCV::Select_FPR64_Using_CC_GPR:
859 return emitSelectPseudo(MI, BB);
860 case RISCV::BuildPairF64Pseudo:
861 return emitBuildPairF64Pseudo(MI, BB);
862 case RISCV::SplitF64Pseudo:
863 return emitSplitF64Pseudo(MI, BB);
864 }
862865 }
863866
864867 // Calling Convention Implementation.