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[x86][SSE] Add widenSubVector helper. NFCI. Helper function to insert a subvector into the bottom elements of a larger zero/undef vector with the same scalar type. I've converted a couple of INSERT_SUBVECTOR calls to use it, there are plenty more although in some cases I was worried it might make the code more ambiguous. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327236 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim 2 years ago
1 changed file(s) with 17 addition(s) and 9 deletion(s). Raw diff Collapse all Expand all
50785078 SelectionDAG &DAG, const SDLoc &dl) {
50795079 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
50805080 return insertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
5081 }
5082
5083 /// Widen a vector to a larger size with the same scalar type, with the new
5084 /// elements either zero or undef.
5085 static SDValue widenSubVector(MVT VT, SDValue Vec, bool ZeroNewElements,
5086 const X86Subtarget &Subtarget, SelectionDAG &DAG,
5087 const SDLoc &dl) {
5088 assert(Vec.getValueSizeInBits() < VT.getSizeInBits() &&
5089 Vec.getValueType().getScalarType() == VT.getScalarType() &&
5090 "Unsupported vector widening type");
5091 SDValue Res = ZeroNewElements ? getZeroVector(VT, Subtarget, DAG, dl)
5092 : DAG.getUNDEF(VT);
5093 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, VT, Res, Vec,
5094 DAG.getIntPtrConstant(0, dl));
50815095 }
50825096
50835097 // Helper for splitting operands of a binary operation to legal target size and
79297943 if (SrcVec.getValueSizeInBits() > VT.getSizeInBits())
79307944 return SDValue();
79317945 else if (SrcVec.getValueSizeInBits() < VT.getSizeInBits())
7932 SrcVec =
7933 DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(SrcVec), VT, DAG.getUNDEF(VT),
7934 SrcVec, DAG.getIntPtrConstant(0, SDLoc(SrcVec)));
7946 SrcVec = widenSubVector(VT, SrcVec, false, Subtarget, DAG, SDLoc(SrcVec));
79357947
79367948 auto ScaleIndices = [&DAG](SDValue Idx, uint64_t Scale) {
79377949 assert(isPowerOf2_64(Scale) && "Illegal variable permute shuffle scale");
86118623 // of a node with instruction that zeroes all upper (irrelevant) bits of the
86128624 // output register, mark it as legal and catch the pattern in instruction
86138625 // selection to avoid emitting extra instructions (for zeroing upper bits).
8614 if (SDValue Promoted = isTypePromotionOfi1ZeroUpBits(Op)) {
8615 SDValue ZeroC = DAG.getIntPtrConstant(0, dl);
8616 SDValue AllZeros = getZeroVector(ResVT, Subtarget, DAG, dl);
8617 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, AllZeros, Promoted,
8618 ZeroC);
8619 }
8626 if (SDValue Promoted = isTypePromotionOfi1ZeroUpBits(Op))
8627 return widenSubVector(ResVT, Promoted, true, Subtarget, DAG, dl);
86208628
86218629 unsigned NumZero = 0;
86228630 unsigned NumNonZero = 0;