llvm.org GIT mirror llvm / ccdb9c9
Fix broken CHECK lines. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199016 91177308-0d34-0410-b5e6-96231b3b80d8 Benjamin Kramer 5 years ago
26 changed file(s) with 43 addition(s) and 42 deletion(s). Raw diff Collapse all Expand all
1717
1818 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
1919
20 ; CHECK [[TAGA]] = metadata !{metadata [[TYPEA:!.*]], metadata [[TYPEA]], i64 0}
21 ; CHECK [[TYPEA]] = metadata !{metadata !"A", metadata !{{.*}}}
20 ; CHECK: [[TAGA]] = metadata !{metadata [[TYPEA:!.*]], metadata [[TYPEA]], i64 0}
21 ; CHECK: [[TYPEA]] = metadata !{metadata !"A", metadata !{{.*}}}
2222 !0 = metadata !{metadata !"tbaa root", null}
2323 !1 = metadata !{metadata !3, metadata !3, i64 0}
2424 !2 = metadata !{metadata !4, metadata !4, i64 0}
5252 ; CHECK: ![[ID0]] = metadata !{i32 662302, i32 26, metadata ![[ID1]], null}
5353 ; CHECK: ![[ID1]] = metadata !{i32 4, metadata !"foo"}
5454 ; CHECK: ![[ID2]] = metadata !{metadata !"bar"}
55 ; CHECK; ![[ID3]] = metadata !{metadata !"foo"}
55 ; CHECK: ![[ID3]] = metadata !{metadata !"foo"}
11 ; RUN: llc < %s -mtriple=armv7-apple-ios -O0 | FileCheck %s -check-prefix=ARM
22 ; RUN: llc < %s -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s -check-prefix=THUMBTWO
33 ; RUN: llc < %s -mtriple=thumbv6-apple-ios | FileCheck %s -check-prefix=THUMBONE
4 ; RUN llc < %s -mtriple=armv4-apple-ios | FileCheck %s -check-prefix=ARMV4
4 ; RUN: llc < %s -mtriple=armv4-apple-ios | FileCheck %s -check-prefix=ARMV4
55
66 define void @test1(i32* %ptr, i32 %val1) {
77 ; ARM: test1
188188 %div = sdiv i32 %a, %b
189189 ; EABI: __aeabi_idivmod
190190 ; EABI: mov [[div:r[0-9]+]], r0
191 ; GNU __aeabi_idiv
191 ; GNU: __aeabi_idiv
192192 ; GNU: mov [[sum:r[0-9]+]], r0
193193 ; DARWIN: ___divsi3
194194 ; DARWIN: mov [[sum:r[0-9]+]], r0
4242 ; STATIC-MIPS16-1: li $[[R1_16:[0-9]+]], %hi($tmp[[TI_16:[0-9]+]])
4343 ; STATIC-MIPS16-1: sll ${{[0-9]+}}, $[[R1_16]], 16
4444 ; STATIC-MIPS16-2: li ${{[0-9]+}}, %lo($tmp{{[0-9]+}})
45 ; STATIC-MIPS16-1 jal dummy
46 ; STATIC-MIPS16-2 jal dummy
45 ; STATIC-MIPS16-1: jal dummy
46 ; STATIC-MIPS16-2: jal dummy
4747
4848 define void @f() nounwind {
4949 entry:
1414 entry:
1515 store i32 -559023410, i32* @i, align 4
1616 %0 = load i32* @b, align 4
17 ; no-load-relax lw ${{[0-9]+}}, $CPI0_1 # 16 bit inst
17 ; no-load-relax: lw ${{[0-9]+}}, $CPI0_1 # 16 bit inst
1818 %tobool = icmp ne i32 %0, 0
1919 br i1 %tobool, label %if.then, label %if.else
2020 ; no-load-relax: beqz ${{[0-9]+}}, $BB0_3
0 ; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck %s
11
22 define void @use_gep_address_space([1024 x i32] addrspace(3)* %array) nounwind {
3 ; CHECK-LABEL @use_gep_address_space:
3 ; CHECK-LABEL: @use_gep_address_space:
44 ; CHECK: S_ADD_I32
55 %p = getelementptr [1024 x i32] addrspace(3)* %array, i16 0, i16 16
66 store i32 99, i32 addrspace(3)* %p
8686 ; CHECK-LABEL: @local_global_alias
8787 ; CHECK: LDS_READ_RET
8888 ; CHECK-NOT: ALU clause
89 ; CHECK MOV * T{{[0-9]\.[XYZW]}}, OQAP
89 ; CHECK: MOV * T{{[0-9]\.[XYZW]}}, OQAP
9090 define void @local_global_alias(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
9191 entry:
9292 %0 = getelementptr inbounds [2 x i32] addrspace(3)* @local_mem, i32 0, i32 0
0 ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
11
2 ;CHECK_LABEL: @test1
2 ;CHECK-LABEL: @test1
33 ;CHECK: TBUFFER_STORE_FORMAT_XYZW {{v\[[0-9]+:[0-9]+\]}}, 32, -1, 0, -1, 0, 14, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0
44 define void @test1(i32 %a1, i32 %vaddr) {
55 %vdata = insertelement <4 x i32> undef, i32 %a1, i32 0
99 ret void
1010 }
1111
12 ;CHECK_LABEL: @test2
12 ;CHECK-LABEL: @test2
1313 ;CHECK: TBUFFER_STORE_FORMAT_XYZ {{v\[[0-9]+:[0-9]+\]}}, 24, -1, 0, -1, 0, 13, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0
1414 define void @test2(i32 %a1, i32 %vaddr) {
1515 %vdata = insertelement <4 x i32> undef, i32 %a1, i32 0
1919 ret void
2020 }
2121
22 ;CHECK_LABEL: @test3
22 ;CHECK-LABEL: @test3
2323 ;CHECK: TBUFFER_STORE_FORMAT_XY {{v\[[0-9]+:[0-9]+\]}}, 16, -1, 0, -1, 0, 11, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0
2424 define void @test3(i32 %a1, i32 %vaddr) {
2525 %vdata = insertelement <2 x i32> undef, i32 %a1, i32 0
2929 ret void
3030 }
3131
32 ;CHECK_LABEL: @test4
32 ;CHECK-LABEL: @test4
3333 ;CHECK: TBUFFER_STORE_FORMAT_X {{v[0-9]+}}, 8, -1, 0, -1, 0, 4, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0
3434 define void @test4(i32 %vdata, i32 %vaddr) {
3535 call void @llvm.SI.tbuffer.store.i32(<16 x i8> undef, i32 %vdata,
1616 ; CI-CHECK-NEXT: .long 32768
1717
1818 ; EG-CHECK: LDS_WRITE
19 ; SI-CHECK_NOT: S_WQM_B64
19 ; SI-CHECK-NOT: S_WQM_B64
2020 ; SI-CHECK: DS_WRITE_B32 0
2121
2222 ; GROUP_BARRIER must be the last instruction in a clause
7676 ; loads and stores should be lowered to copies, so there shouldn't be any
7777 ; MOVA instructions.
7878
79 ; R600-CHECK-LABLE: @direct_loop
79 ; R600-CHECK-LABEL: @direct_loop
8080 ; R600-CHECK-NOT: MOVA_INT
8181 ; SI-CHECK-LABEL: @direct_loop
8282 ; SI-CHECK-NOT: V_MOVREL
55
66 ; CHECK: @test
77 ; CHECK: Fetch clause
8 ; CHECK_VTX_READ_32 [[IN0:T[0-9]+\.X]], [[IN0]], 0
8 ; CHECK: VTX_READ_32 [[IN0:T[0-9]+\.X]], [[IN0]], 0
99 ; CHECK: Fetch clause
10 ; CHECK_VTX_READ_32 [[IN1:T[0-9]+\.X]], [[IN1]], 0
10 ; CHECK: VTX_READ_32 [[IN1:T[0-9]+\.X]], [[IN1]], 0
1111 define void @test(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* addrspace(1)* nocapture %in0) {
1212 entry:
1313 %0 = load i32 addrspace(1)* addrspace(1)* %in0
44 declare i32 @llvm.ctpop.i32(i32)
55
66 ; V8-LABEL: test
7 ; V8-NOT : popc
7 ; V8-NOT: popc
88
99 ; V9-LABEL: test
1010 ; V9: srl %o0, 0, %o0
0 ; RUN: llc < %s -mtriple=thumb-apple-darwin | FileCheck %s
11
22 define i32 @f1(float %X, float %Y) {
3 ; CHECK-LABEL _f1:
3 ; CHECK-LABEL: _f1:
44 ; CHECK: bne
55 ; CHECK: .data_region
66 ; CHECK: .long ___unordsf2
1010 }
1111
1212 define i32 @f2(float %X, float %Y) {
13 ; CHECK-LABEL _f2:
13 ; CHECK-LABEL: _f2:
1414 ; CHECK: beq
1515 ; CHECK: .data_region
1616 ; CHECK: .long ___unordsf2
55 ; the destination address. It's callee-saved in AAPCS.
66 define arm_aapcscc void @test(i32 %a) nounwind {
77 ; CHECK-LABEL: test:
8 ; CHECK-NOT bx r9
8 ; CHECK-NOT: bx r9
99 %tmp = load void ()** @foo, align 4
1010 tail call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r12}"() nounwind
1111 tail call arm_aapcscc void %tmp() nounwind
184184 }
185185
186186 ; CHECK-LABEL: @fptosi02
187 ; CHECK vcvttss2si {{.*}} encoding: [0x62
187 ; CHECK: vcvttss2si {{.*}} encoding: [0x62
188188 ; CHECK: ret
189189 define i32 @fptosi02(float %a) nounwind {
190190 %b = fptosi float %a to i32
192192 }
193193
194194 ; CHECK-LABEL: @fptoui02
195 ; CHECK vcvttss2usi {{.*}} encoding: [0x62
195 ; CHECK: vcvttss2usi {{.*}} encoding: [0x62
196196 ; CHECK: ret
197197 define i32 @fptoui02(float %a) nounwind {
198198 %b = fptoui float %a to i32
200200 }
201201
202202 ; CHECK-LABEL: @uitofp02
203 ; CHECK vcvtusi2ss
203 ; CHECK: vcvtusi2ss
204204 ; CHECK: ret
205205 define float @uitofp02(i32 %a) nounwind {
206206 %b = uitofp i32 %a to float
208208 }
209209
210210 ; CHECK-LABEL: @uitofp03
211 ; CHECK vcvtusi2sd
211 ; CHECK: vcvtusi2sd
212212 ; CHECK: ret
213213 define double @uitofp03(i32 %a) nounwind {
214214 %b = uitofp i32 %a to double
1717
1818
1919 ; CHECK-LABEL: zext_16x8_to_16x32
20 ; CHECK; vpmovzxbd {{.*}}%zmm
20 ; CHECK: vpmovzxbd {{.*}}%zmm
2121 ; CHECK: ret
2222 define <16 x i32> @zext_16x8_to_16x32(<16 x i8> %i) nounwind readnone {
2323 %x = zext <16 x i8> %i to <16 x i32>
2525 }
2626
2727 ; CHECK-LABEL: sext_16x8_to_16x32
28 ; CHECK; vpmovsxbd {{.*}}%zmm
28 ; CHECK: vpmovsxbd {{.*}}%zmm
2929 ; CHECK: ret
3030 define <16 x i32> @sext_16x8_to_16x32(<16 x i8> %i) nounwind readnone {
3131 %x = sext <16 x i8> %i to <16 x i32>
3434
3535
3636 ; CHECK-LABEL: zext_16x16_to_16x32
37 ; CHECK; vpmovzxwd {{.*}}%zmm
37 ; CHECK: vpmovzxwd {{.*}}%zmm
3838 ; CHECK: ret
3939 define <16 x i32> @zext_16x16_to_16x32(<16 x i16> %i) nounwind readnone {
4040 %x = zext <16 x i16> %i to <16 x i32>
4242 }
4343
4444 ; CHECK-LABEL: zext_8x16_to_8x64
45 ; CHECK; vpmovzxwq
45 ; CHECK: vpmovzxwq
4646 ; CHECK: ret
4747 define <8 x i64> @zext_8x16_to_8x64(<8 x i16> %i) nounwind readnone {
4848 %x = zext <8 x i16> %i to <8 x i64>
131131 define <16 x i16> @trunc_v16i32_to_v16i16(<16 x i32> %x) {
132132 %1 = trunc <16 x i32> %x to <16 x i16>
133133 ret <16 x i16> %1
134 }
134 }
44 declare void @use(<2 x double>)
55
66 ; CHECK-LABEL: @test
7 ; CHECK callq round
7 ; CHECK: callq round
88
99 ; Function Attrs: nounwind uwtable
1010 define void @test() {
0 ; RUN: llc < %s -march=xcore | FileCheck %s
1 ; RUN: llc < %s -march=xcore -disable-fp-elim | FileCheck %s -check-prefix=CHECKFP
12
23 declare i8* @llvm.frameaddress(i32) nounwind readnone
34 declare i8* @llvm.returnaddress(i32) nounwind
140141 ; CHECKFP: ldaw r10, sp[0]
141142 ; CHECKFP: stw r4, r10[7]
142143 ; CHECKFP: stw r5, r10[6]
143 ; CHECKFP: stw r6, r10[5]`
144 ; CHECKFP: stw r6, r10[5]
144145 ; CHECKFP: stw r7, r10[4]
145146 ; CHECKFP: stw r8, r10[3]
146147 ; CHECKFP: stw r9, r10[2]
None ; RUN: opt -memdep -gvn -disable-output
0 ; RUN: opt -memdep -gvn -disable-output < %s
11
22 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
33 target triple = "x86_64-apple-darwin10.0"
0 ;RUN: opt -S %s -indvars | FileCheck %s
11
2 ; CHECK-LABEL-LABEL: @foo(
2 ; CHECK-LABEL: @foo(
33 ; CHECK-NOT: %lftr.wideiv = trunc i32 %indvars.iv.next to i16
44 ; CHECK: %exitcond = icmp ne i32 %indvars.iv.next, 512
55 define void @foo() #0 {
1919 }
2020
2121 ; Check that post-incrementing the backedge taken count does not overflow.
22 ; CHECK-LABEL-LABEL: @postinc(
22 ; CHECK-LABEL: @postinc(
2323 ; CHECK: icmp eq i32 %indvars.iv.next, 256
2424 define i32 @postinc() #0 {
2525 entry:
3535 %input_1.addr.1 = phi <3 x i32> [ undef, %entry ], [ %dec43, %for.body ]
3636 br i1 undef, label %for.end, label %for.body
3737
38 ; CHECK extractelement
38 ; CHECK: extractelement
3939 for.body:
4040 %dec43 = add <3 x i32> %input_1.addr.1,
4141 %sub44 = sub <3 x i32> zeroinitializer, %dec43
33 ; out of the loop.
44 ; CHECK: load i32* %p
55 ; CHECK: for.body:
6 ; CHECK; load volatile i32* %q
6 ; CHECK: load volatile i32* %q
77
88 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
99
1212 ; CHECK: %lsr.iv = phi i32 [ %lsr.iv.next, %test2.loop ], [ -16777216, %entry ]
1313 ; CHECK: %lsr.iv.next = add nsw i32 %lsr.iv, 16777216
1414 ;
15 ; CHECK=LABEL: for.end:
15 ; CHECK-LABEL: for.end:
1616 ; CHECK: %sub.cond.us = sub nsw i32 %inc1115.us, %sub.us
1717 ; CHECK: %sext.us = mul i32 %lsr.iv.next, %sub.cond.us
1818 ; CHECK: %f = ashr i32 %sext.us, 24
7474 ; PR17532
7575
7676 ; CHECK-LABEL: i8_loop
77 ; CHECK; icmp eq i32 {{.*}}, 256
77 ; CHECK: icmp eq i32 {{.*}}, 256
7878 define i32 @i8_loop() nounwind readnone ssp uwtable {
7979 br label %1
8080
9191 }
9292
9393 ; CHECK-LABEL: i16_loop
94 ; CHECK; icmp eq i32 {{.*}}, 65536
94 ; CHECK: icmp eq i32 {{.*}}, 65536
9595
9696 define i32 @i16_loop() nounwind readnone ssp uwtable {
9797 br label %1
220220 ; CHECK: load x86_fp80*
221221 ; CHECK: load x86_fp80*
222222 ; CHECK-NOT: insertelement <2 x x86_fp80>
223 ; CHECK_NOT: insertelement <2 x x86_fp80>
223 ; CHECK-NOT: insertelement <2 x x86_fp80>
224224 br i1 undef, label %then, label %end
225225
226226 then: