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Merging r368572: ------------------------------------------------------------------------ r368572 | lenary | 2019-08-12 15:51:00 +0200 (Mon, 12 Aug 2019) | 18 lines [RISCV] Fix ICE in isDesirableToCommuteWithShift Summary: Ana Pazos reported a bug where we were not checking that an APInt would fit into 64-bits before calling `getSExtValue()`. This caused asserts when compiling large constants, such as i128s, as happens when compiling compiler-rt. This patch adds a testcase and makes the callback less error-prone. Reviewers: apazos, asb, luismarques Reviewed By: luismarques Subscribers: hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66081 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_90@368674 91177308-0d34-0410-b5e6-96231b3b80d8 Hans Wennborg 1 year, 3 months ago
2 changed file(s) with 44 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
10061006 // We can materialise `c1 << c2` into an add immediate, so it's "free",
10071007 // and the combine should happen, to potentially allow further combines
10081008 // later.
1009 if (isLegalAddImmediate(ShiftedC1Int.getSExtValue()))
1009 if (ShiftedC1Int.getMinSignedBits() <= 64 &&
1010 isLegalAddImmediate(ShiftedC1Int.getSExtValue()))
10101011 return true;
10111012
10121013 // We can materialise `c1` in an add immediate, so it's "free", and the
10131014 // combine should be prevented.
1014 if (isLegalAddImmediate(C1Int.getSExtValue()))
1015 if (C1Int.getMinSignedBits() <= 64 &&
1016 isLegalAddImmediate(C1Int.getSExtValue()))
10151017 return false;
10161018
10171019 // Neither constant will fit into an immediate, so find materialisation
9090 %2 = shl i24 %1, 12
9191 ret i24 %2
9292 }
93
94 define i128 @add_wide_operand(i128 %a) nounwind {
95 ; RV32I-LABEL: add_wide_operand:
96 ; RV32I: # %bb.0:
97 ; RV32I-NEXT: lw a2, 0(a1)
98 ; RV32I-NEXT: srli a3, a2, 29
99 ; RV32I-NEXT: lw a4, 4(a1)
100 ; RV32I-NEXT: slli a5, a4, 3
101 ; RV32I-NEXT: or a6, a5, a3
102 ; RV32I-NEXT: srli a4, a4, 29
103 ; RV32I-NEXT: lw a5, 8(a1)
104 ; RV32I-NEXT: slli a3, a5, 3
105 ; RV32I-NEXT: or a3, a3, a4
106 ; RV32I-NEXT: slli a2, a2, 3
107 ; RV32I-NEXT: sw a2, 0(a0)
108 ; RV32I-NEXT: sw a3, 8(a0)
109 ; RV32I-NEXT: sw a6, 4(a0)
110 ; RV32I-NEXT: srli a2, a5, 29
111 ; RV32I-NEXT: lw a1, 12(a1)
112 ; RV32I-NEXT: slli a1, a1, 3
113 ; RV32I-NEXT: or a1, a1, a2
114 ; RV32I-NEXT: lui a2, 128
115 ; RV32I-NEXT: add a1, a1, a2
116 ; RV32I-NEXT: sw a1, 12(a0)
117 ; RV32I-NEXT: ret
118 ;
119 ; RV64I-LABEL: add_wide_operand:
120 ; RV64I: # %bb.0:
121 ; RV64I-NEXT: slli a1, a1, 3
122 ; RV64I-NEXT: srli a2, a0, 61
123 ; RV64I-NEXT: or a1, a1, a2
124 ; RV64I-NEXT: addi a2, zero, 1
125 ; RV64I-NEXT: slli a2, a2, 51
126 ; RV64I-NEXT: add a1, a1, a2
127 ; RV64I-NEXT: slli a0, a0, 3
128 ; RV64I-NEXT: ret
129 %1 = add i128 %a, 5192296858534827628530496329220096
130 %2 = shl i128 %1, 3
131 ret i128 %2
132 }