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[x86] Allow address-size overrides for STOS[BWLQ] (PR9385) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199804 91177308-0d34-0410-b5e6-96231b3b80d8 David Woodhouse 6 years ago
17 changed file(s) with 241 addition(s) and 45 deletion(s). Raw diff Collapse all Expand all
551551 }
552552
553553 X86Operand *DefaultMemSIOperand(SMLoc Loc);
554 X86Operand *DefaultMemDIOperand(SMLoc Loc);
554555 X86Operand *ParseOperand();
555556 X86Operand *ParseATTOperand();
556557 X86Operand *ParseIntelOperand();
939940 }
940941 bool isSrcIdx64() const {
941942 return isMem64() && isSrcIdx();
943 }
944
945 bool isDstIdx() const {
946 return !getMemIndexReg() && getMemScale() == 1 &&
947 (getMemSegReg() == 0 || getMemSegReg() == X86::ES) &&
948 (getMemBaseReg() == X86::RDI || getMemBaseReg() == X86::EDI ||
949 getMemBaseReg() == X86::DI) && isa(getMemDisp()) &&
950 cast(getMemDisp())->getValue() == 0;
951 }
952 bool isDstIdx8() const {
953 return isMem8() && isDstIdx();
954 }
955 bool isDstIdx16() const {
956 return isMem16() && isDstIdx();
957 }
958 bool isDstIdx32() const {
959 return isMem32() && isDstIdx();
960 }
961 bool isDstIdx64() const {
962 return isMem64() && isDstIdx();
942963 }
943964
944965 bool isMemOffs8() const {
10381059 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
10391060 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
10401061 }
1062 void addDstIdxOperands(MCInst &Inst, unsigned N) const {
1063 assert((N == 1) && "Invalid number of operands!");
1064 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
1065 }
10411066
10421067 void addMemOffsOperands(MCInst &Inst, unsigned N) const {
10431068 assert((N == 2) && "Invalid number of operands!");
12581283 X86Operand *X86AsmParser::DefaultMemSIOperand(SMLoc Loc) {
12591284 unsigned basereg =
12601285 is64BitMode() ? X86::RSI : (is32BitMode() ? X86::ESI : X86::SI);
1286 const MCExpr *Disp = MCConstantExpr::Create(0, getContext());
1287 return X86Operand::CreateMem(/*SegReg=*/0, Disp, /*BaseReg=*/basereg,
1288 /*IndexReg=*/0, /*Scale=*/1, Loc, Loc, 0);
1289 }
1290
1291 X86Operand *X86AsmParser::DefaultMemDIOperand(SMLoc Loc) {
1292 unsigned basereg =
1293 is64BitMode() ? X86::RDI : (is32BitMode() ? X86::EDI : X86::DI);
12611294 const MCExpr *Disp = MCConstantExpr::Create(0, getContext());
12621295 return X86Operand::CreateMem(/*SegReg=*/0, Disp, /*BaseReg=*/basereg,
12631296 /*IndexReg=*/0, /*Scale=*/1, Loc, Loc, 0);
23192352 Name == "lodsl" || Name == "lodsd" || Name == "lodsq"))
23202353 Operands.push_back(DefaultMemSIOperand(NameLoc));
23212354
2322 // Transform "stos[bwl] {%al,%ax,%eax,%rax},%es:(%edi)" into "stos[bwl]"
2323 if (Name.startswith("stos") && Operands.size() == 3 &&
2355 // Transform "stos[bwlq]" into "stos[bwlq] ($DIREG)" for appropriate
2356 // values of $DIREG according to the mode. It would be nice if this
2357 // could be achieved with InstAlias in the tables.
2358 if (Name.startswith("stos") && Operands.size() == 1 &&
23242359 (Name == "stos" || Name == "stosb" || Name == "stosw" ||
2325 Name == "stosl" || (is64BitMode() && Name == "stosq"))) {
2326 X86Operand *Op1 = static_cast(Operands[1]);
2327 X86Operand *Op2 = static_cast(Operands[2]);
2328 if (isDstOp(*Op2) && Op1->isReg()) {
2329 const char *ins;
2330 unsigned reg = Op1->getReg();
2331 bool isStos = Name == "stos";
2332 if (reg == X86::AL && (isStos || Name == "stosb"))
2333 ins = "stosb";
2334 else if (reg == X86::AX && (isStos || Name == "stosw"))
2335 ins = "stosw";
2336 else if (reg == X86::EAX && (isStos || Name == "stosl"))
2337 ins = "stosl";
2338 else if (reg == X86::RAX && (isStos || Name == "stosq"))
2339 ins = "stosq";
2340 else
2341 ins = NULL;
2342 if (ins != NULL) {
2343 Operands.pop_back();
2344 Operands.pop_back();
2345 delete Op1;
2346 delete Op2;
2347 if (Name != ins)
2348 static_cast(Operands[0])->setTokenValue(ins);
2349 }
2350 }
2351 }
2360 Name == "stosl" || Name == "stosd" || Name == "stosq"))
2361 Operands.push_back(DefaultMemDIOperand(NameLoc));
23522362
23532363 // FIXME: Hack to handle recognize s{hr,ar,hl} $1, . Canonicalize to
23542364 // "shift ".
252252 MCOperand segmentReg;
253253 segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]);
254254 mcInst.addOperand(segmentReg);
255 return false;
256 }
257
258 /// translateDstIndex - Appends a destination index operand to an MCInst.
259 ///
260 /// @param mcInst - The MCInst to append to.
261 /// @param operand - The operand, as stored in the descriptor table.
262 /// @param insn - The internal instruction.
263
264 static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn) {
265 unsigned baseRegNo;
266
267 if (insn.mode == MODE_64BIT)
268 baseRegNo = insn.prefixPresent[0x67] ? X86::EDI : X86::RDI;
269 else if (insn.mode == MODE_32BIT)
270 baseRegNo = insn.prefixPresent[0x67] ? X86::DI : X86::EDI;
271 else if (insn.mode == MODE_16BIT)
272 baseRegNo = insn.prefixPresent[0x67] ? X86::EDI : X86::DI;
273 MCOperand baseReg = MCOperand::CreateReg(baseRegNo);
274 mcInst.addOperand(baseReg);
255275 return false;
256276 }
257277
718738 return false;
719739 case ENCODING_SI:
720740 return translateSrcIndex(mcInst, insn);
741 case ENCODING_DI:
742 return translateDstIndex(mcInst, insn);
721743 case ENCODING_RB:
722744 case ENCODING_RW:
723745 case ENCODING_RD:
16821682 switch (x86OperandSets[insn->spec->operands][index].encoding) {
16831683 case ENCODING_NONE:
16841684 case ENCODING_SI:
1685 case ENCODING_DI:
16851686 break;
16861687 case ENCODING_REG:
16871688 case ENCODING_RM:
409409 "opcode byte") \
410410 ENUM_ENTRY(ENCODING_DUP, "Duplicate of another operand; ID is encoded " \
411411 "in type") \
412 ENUM_ENTRY(ENCODING_SI, "Source index; encoded in OpSize/Adsize prefix")
412 ENUM_ENTRY(ENCODING_SI, "Source index; encoded in OpSize/Adsize prefix") \
413 ENUM_ENTRY(ENCODING_DI, "Destination index; encoded in prefixes")
413414
414415 #define ENUM_ENTRY(n, d) n,
415416 typedef enum {
464465 ENUM_ENTRY(TYPE_SRCIDX16, "2-byte memory at source index") \
465466 ENUM_ENTRY(TYPE_SRCIDX32, "4-byte memory at source index") \
466467 ENUM_ENTRY(TYPE_SRCIDX64, "8-byte memory at source index") \
468 ENUM_ENTRY(TYPE_DSTIDX8, "1-byte memory at destination index") \
469 ENUM_ENTRY(TYPE_DSTIDX16, "2-byte memory at destination index") \
470 ENUM_ENTRY(TYPE_DSTIDX32, "4-byte memory at destination index") \
471 ENUM_ENTRY(TYPE_DSTIDX64, "8-byte memory at destination index") \
467472 ENUM_ENTRY(TYPE_MOFFS8, "1-byte memory offset (relative to segment " \
468473 "base)") \
469474 ENUM_ENTRY(TYPE_MOFFS16, "2-byte") \
244244 O << markup(">");
245245 }
246246
247 void X86ATTInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
248 raw_ostream &O) {
249 O << markup("
250
251 O << "%es:(";
252 printOperand(MI, Op, O);
253 O << ")";
254
255 O << markup(">");
256 }
257
247258 void X86ATTInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
248259 raw_ostream &O) {
249260 const MCOperand &DispSpec = MI->getOperand(Op);
4242 void printAVXCC(const MCInst *MI, unsigned Op, raw_ostream &OS);
4343 void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
4444 void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
45 void printDstIdx(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
4546 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
4647 void printRoundingControl(const MCInst *MI, unsigned Op, raw_ostream &OS);
4748
101102 void printSrcIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
102103 printSrcIdx(MI, OpNo, O);
103104 }
105 void printDstIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
106 printDstIdx(MI, OpNo, O);
107 }
108 void printDstIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
109 printDstIdx(MI, OpNo, O);
110 }
111 void printDstIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
112 printDstIdx(MI, OpNo, O);
113 }
114 void printDstIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
115 printDstIdx(MI, OpNo, O);
116 }
104117 void printMemOffs8(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
105118 printMemOffset(MI, OpNo, O);
106119 }
225225 O << ']';
226226 }
227227
228 void X86IntelInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
229 raw_ostream &O) {
230 // DI accesses are always ES-based.
231 O << "es:[";
232 printOperand(MI, Op, O);
233 O << ']';
234 }
235
228236 void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
229237 raw_ostream &O) {
230238 const MCOperand &DispSpec = MI->getOperand(Op);
4040 void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
4141 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O);
4242 void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O);
43 void printDstIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O);
4344 void printRoundingControl(const MCInst *MI, unsigned Op, raw_ostream &OS);
4445
4546 void printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
117118 O << "qword ptr ";
118119 printSrcIdx(MI, OpNo, O);
119120 }
121 void printDstIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
122 O << "byte ptr ";
123 printDstIdx(MI, OpNo, O);
124 }
125 void printDstIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
126 O << "word ptr ";
127 printDstIdx(MI, OpNo, O);
128 }
129 void printDstIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
130 O << "dword ptr ";
131 printDstIdx(MI, OpNo, O);
132 }
133 void printDstIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
134 O << "qword ptr ";
135 printDstIdx(MI, OpNo, O);
136 }
120137 void printMemOffs8(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
121138 O << "byte ptr ";
122139 printMemOffset(MI, OpNo, O);
261261 /// RawFrmSrc - This form is for instructions that use the source index
262262 /// register SI/ESI/RSI with a possible segment override.
263263 RawFrmSrc = 8,
264
265 /// RawFrmDst - This form is for instructions that use the destination index
266 /// register DI/EDI/ESI.
267 RawFrmDst = 9,
264268
265269 /// MRM[0-7][rm] - These forms are used to represent instructions that use
266270 /// a Mod/RM byte, and use the middle field to hold extended opcode
616620 case X86II::RawFrmImm16:
617621 case X86II::RawFrmMemOffs:
618622 case X86II::RawFrmSrc:
623 case X86II::RawFrmDst:
619624 return -1;
620625 case X86II::MRMDestMem:
621626 return 0;
13261326 (is32BitMode() && siReg == X86::SI))
13271327 EmitByte(0x67, CurByte, OS);
13281328 CurOp += 2; // Consume operands.
1329 EmitByte(BaseOpcode, CurByte, OS);
1330 break;
1331 }
1332 case X86II::RawFrmDst: {
1333 unsigned siReg = MI.getOperand(0).getReg();
1334 // Emit OpSize prefix as needed.
1335 if ((!is32BitMode() && siReg == X86::EDI) ||
1336 (is32BitMode() && siReg == X86::DI))
1337 EmitByte(0x67, CurByte, OS);
1338 ++CurOp; // Consume operand.
13291339 EmitByte(BaseOpcode, CurByte, OS);
13301340 break;
13311341 }
2121 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
2222 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
2323 def MRMSrcMem : Format<6>; def RawFrmMemOffs : Format<7>;
24 def RawFrmSrc : Format<8>;
24 def RawFrmSrc : Format<8>; def RawFrmDst : Format<9>;
2525 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
2626 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
2727 def MRM6r : Format<22>; def MRM7r : Format<23>;
464464 let RenderMethod = "addSrcIdxOperands";
465465 let SuperClasses = [X86Mem64AsmOperand];
466466 }
467 def X86DstIdx8Operand : AsmOperandClass {
468 let Name = "DstIdx8";
469 let RenderMethod = "addDstIdxOperands";
470 let SuperClasses = [X86Mem8AsmOperand];
471 }
472 def X86DstIdx16Operand : AsmOperandClass {
473 let Name = "DstIdx16";
474 let RenderMethod = "addDstIdxOperands";
475 let SuperClasses = [X86Mem16AsmOperand];
476 }
477 def X86DstIdx32Operand : AsmOperandClass {
478 let Name = "DstIdx32";
479 let RenderMethod = "addDstIdxOperands";
480 let SuperClasses = [X86Mem32AsmOperand];
481 }
482 def X86DstIdx64Operand : AsmOperandClass {
483 let Name = "DstIdx64";
484 let RenderMethod = "addDstIdxOperands";
485 let SuperClasses = [X86Mem64AsmOperand];
486 }
467487 def X86MemOffs8AsmOperand : AsmOperandClass {
468488 let Name = "MemOffs8";
469489 let RenderMethod = "addMemOffsOperands";
501521 let ParserMatchClass = X86SrcIdx64Operand;
502522 let MIOperandInfo = (ops ptr_rc, i8imm);
503523 let PrintMethod = "printSrcIdx64"; }
524 def dstidx8 : Operand {
525 let ParserMatchClass = X86DstIdx8Operand;
526 let MIOperandInfo = (ops ptr_rc);
527 let PrintMethod = "printDstIdx8"; }
528 def dstidx16 : Operand {
529 let ParserMatchClass = X86DstIdx16Operand;
530 let MIOperandInfo = (ops ptr_rc);
531 let PrintMethod = "printDstIdx16"; }
532 def dstidx32 : Operand {
533 let ParserMatchClass = X86DstIdx32Operand;
534 let MIOperandInfo = (ops ptr_rc);
535 let PrintMethod = "printDstIdx32"; }
536 def dstidx64 : Operand {
537 let ParserMatchClass = X86DstIdx64Operand;
538 let MIOperandInfo = (ops ptr_rc);
539 let PrintMethod = "printDstIdx64"; }
504540 def offset8 : Operand {
505541 let ParserMatchClass = X86MemOffs8AsmOperand;
506542 let MIOperandInfo = (ops i64imm, i8imm);
11081144
11091145 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
11101146 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
1111 def STOSB : I<0xAA, RawFrm, (outs), (ins), "stosb", [], IIC_STOS>;
1147 def STOSB : I<0xAA, RawFrmDst, (outs dstidx8:$dst), (ins),
1148 "stosb\t{%al, $dst|$dst, al}", [], IIC_STOS>;
11121149 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
1113 def STOSW : I<0xAB, RawFrm, (outs), (ins), "stosw", [], IIC_STOS>, OpSize;
1150 def STOSW : I<0xAB, RawFrmDst, (outs dstidx16:$dst), (ins),
1151 "stosw\t{%ax, $dst|$dst, ax}", [], IIC_STOS>, OpSize;
11141152 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
1115 def STOSL : I<0xAB, RawFrm, (outs), (ins), "stos{l|d}", [], IIC_STOS>, OpSize16;
1153 def STOSL : I<0xAB, RawFrmDst, (outs dstidx32:$dst), (ins),
1154 "stos{l|d}\t{%eax, $dst|$dst, eax}", [], IIC_STOS>, OpSize16;
11161155 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
1117 def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", [], IIC_STOS>;
1156 def STOSQ : RI<0xAB, RawFrmDst, (outs dstidx64:$dst), (ins),
1157 "stosq\t{%rax, $dst|$dst, rax}", [], IIC_STOS>;
11181158
11191159 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scasb", [], IIC_SCAS>;
11201160 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scasw", [], IIC_SCAS>, OpSize;
23792419 def : InstAlias<"lods {$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>;
23802420 def : InstAlias<"lods {$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
23812421
2422 // stos aliases. Accept the source being omitted because it's implicit in
2423 // the mnemonic, or the mnemonic suffix being omitted because it's implicit
2424 // in the source.
2425 def : InstAlias<"stosb $dst", (STOSB dstidx8:$dst), 0>;
2426 def : InstAlias<"stosw $dst", (STOSW dstidx16:$dst), 0>;
2427 def : InstAlias<"stos{l|d} $dst", (STOSL dstidx32:$dst), 0>;
2428 def : InstAlias<"stosq $dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2429 def : InstAlias<"stos {%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>;
2430 def : InstAlias<"stos {%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>;
2431 def : InstAlias<"stos {%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>;
2432 def : InstAlias<"stos {%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2433
23822434 // div and idiv aliases for explicit A register.
23832435 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>;
23842436 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>;
4343 // 64: lodsw (%esi), %ax # encoding: [0x66,0x67,0xad]
4444 // 32: lodsw (%esi), %ax # encoding: [0x66,0xad]
4545 // 16: lodsw (%esi), %ax # encoding: [0x67,0xad]
46
47 stosw
48 // 64: stosw %ax, %es:(%rdi) # encoding: [0x66,0xab]
49 // 32: stosw %ax, %es:(%edi) # encoding: [0x66,0xab]
50 // 16: stosw %ax, %es:(%di) # encoding: [0xab]
51
52 stos %eax, (%edi)
53 // 64: stosl %eax, %es:(%edi) # encoding: [0x67,0xab]
54 // 32: stosl %eax, %es:(%edi) # encoding: [0xab]
55 // 16: stosl %eax, %es:(%edi) # encoding: [0x66,0x67,0xab]
56
57 stosb %al, %fs:(%edi)
58 // ERR64: invalid operand for instruction
59 // ERR32: invalid operand for instruction
60 // ERR16: invalid operand for instruction
61
62 stosb %al, %es:(%edi)
63 // 64: stosb %al, %es:(%edi) # encoding: [0x67,0xaa]
64 // 32: stosb %al, %es:(%edi) # encoding: [0xaa]
65 // 16: stosb %al, %es:(%edi) # encoding: [0x67,0xaa]
66
67 stosq
68 // 64: stosq %rax, %es:(%rdi) # encoding: [0x48,0xab]
69 // ERR32: 64-bit
70 // ERR16: 64-bit
71
72 stos %rax, (%edi)
73 // 64: stosq %rax, %es:(%edi) # encoding: [0x48,0x67,0xab]
74 // ERR32: only available in 64-bit mode
75 // ERR16: only available in 64-bit mode
877877 lods %ds:(%si), %eax
878878 lods (%si), %eax
879879
880 // CHECK: stosb # encoding: [0xaa]
880 // CHECK: stosb %al, %es:(%di) # encoding: [0xaa]
881881 // CHECK: stosb
882882 // CHECK: stosb
883883 stosb
884884 stosb %al, %es:(%di)
885885 stos %al, %es:(%di)
886886
887 // CHECK: stosw # encoding: [0xab]
887 // CHECK: stosw %ax, %es:(%di) # encoding: [0xab]
888888 // CHECK: stosw
889889 // CHECK: stosw
890890 stosw
891891 stosw %ax, %es:(%di)
892892 stos %ax, %es:(%di)
893893
894 // CHECK: stosl # encoding: [0x66,0xab]
894 // CHECK: stosl %eax, %es:(%di) # encoding: [0x66,0xab]
895895 // CHECK: stosl
896896 // CHECK: stosl
897897 stosl
953953 lods %ds:(%esi), %eax
954954 lods (%esi), %eax
955955
956 // CHECK: stosb # encoding: [0xaa]
956 // CHECK: stosb %al, %es:(%edi) # encoding: [0xaa]
957957 // CHECK: stosb
958958 // CHECK: stosb
959959 stosb
960960 stosb %al, %es:(%edi)
961961 stos %al, %es:(%edi)
962962
963 // CHECK: stosw # encoding: [0x66,0xab]
963 // CHECK: stosw %ax, %es:(%edi) # encoding: [0x66,0xab]
964964 // CHECK: stosw
965965 // CHECK: stosw
966966 stosw
967967 stosw %ax, %es:(%edi)
968968 stos %ax, %es:(%edi)
969969
970 // CHECK: stosl # encoding: [0xab]
970 // CHECK: stosl %eax, %es:(%edi) # encoding: [0xab]
971971 // CHECK: stosl
972972 // CHECK: stosl
973973 stosl
11591159 lods %ds:(%rsi), %rax
11601160 lods (%rsi), %rax
11611161
1162 // CHECK: stosb # encoding: [0xaa]
1162 // CHECK: stosb %al, %es:(%rdi) # encoding: [0xaa]
11631163 // CHECK: stosb
11641164 // CHECK: stosb
11651165 stosb
11661166 stosb %al, %es:(%rdi)
11671167 stos %al, %es:(%rdi)
11681168
1169 // CHECK: stosw # encoding: [0x66,0xab]
1169 // CHECK: stosw %ax, %es:(%rdi) # encoding: [0x66,0xab]
11701170 // CHECK: stosw
11711171 // CHECK: stosw
11721172 stosw
11731173 stosw %ax, %es:(%rdi)
11741174 stos %ax, %es:(%rdi)
11751175
1176 // CHECK: stosl # encoding: [0xab]
1176 // CHECK: stosl %eax, %es:(%rdi) # encoding: [0xab]
11771177 // CHECK: stosl
11781178 // CHECK: stosl
11791179 stosl
11801180 stosl %eax, %es:(%rdi)
11811181 stos %eax, %es:(%rdi)
11821182
1183 // CHECK: stosq # encoding: [0x48,0xab]
1183 // CHECK: stosq %rax, %es:(%rdi) # encoding: [0x48,0xab]
11841184 // CHECK: stosq
11851185 // CHECK: stosq
11861186 stosq
6060 MRMSrcMem = 6,
6161 RawFrmMemOffs = 7,
6262 RawFrmSrc = 8,
63 RawFrmDst = 9,
6364 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
6465 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
6566 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
633634 case X86Local::RawFrmSrc:
634635 HANDLE_OPERAND(relocation);
635636 return;
637 case X86Local::RawFrmDst:
638 HANDLE_OPERAND(relocation);
639 return;
636640 case X86Local::RawFrm:
637641 // Operand 1 (optional) is an address or immediate.
638642 // Operand 2 (optional) is an immediate.
12691273 TYPE("srcidx16", TYPE_SRCIDX16)
12701274 TYPE("srcidx32", TYPE_SRCIDX32)
12711275 TYPE("srcidx64", TYPE_SRCIDX64)
1276 TYPE("dstidx8", TYPE_DSTIDX8)
1277 TYPE("dstidx16", TYPE_DSTIDX16)
1278 TYPE("dstidx32", TYPE_DSTIDX32)
1279 TYPE("dstidx64", TYPE_DSTIDX64)
12721280 TYPE("offset8", TYPE_MOFFS8)
12731281 TYPE("offset16", TYPE_MOFFS16)
12741282 TYPE("offset32", TYPE_MOFFS32)
14851493 ENCODING("srcidx16", ENCODING_SI)
14861494 ENCODING("srcidx32", ENCODING_SI)
14871495 ENCODING("srcidx64", ENCODING_SI)
1496 ENCODING("dstidx8", ENCODING_DI)
1497 ENCODING("dstidx16", ENCODING_DI)
1498 ENCODING("dstidx32", ENCODING_DI)
1499 ENCODING("dstidx64", ENCODING_DI)
14881500 errs() << "Unhandled relocation encoding " << s << "\n";
14891501 llvm_unreachable("Unhandled relocation encoding");
14901502 }