llvm.org GIT mirror llvm / cc07d71
add support for the prefetch/prefetchw instructions, move femms into the right file. The assembler supports all the 3dnow instructions now, but not the "3dnowa" ones. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115468 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 10 years ago
3 changed file(s) with 30 addition(s) and 13 deletion(s). Raw diff Collapse all Expand all
1515
1616 class I3DNow o, Format F, dag outs, dag ins, string asm,
1717 list pattern>
18 : I, TB, Requires<[Has3DNow]>,
19 Has3DNow0F0FOpcode {
20 // FIXME: The disassembler doesn't support 3DNow! yet.
18 : I, TB, Requires<[Has3DNow]> {
19 }
20
21 class I3DNow_binop o, Format F, dag ins, string Mnemonic>
22 : I
23 !strconcat(Mnemonic, "\t{$src2, $dst|$dst, $src2}"), []>,
24 TB, Requires<[Has3DNow]>, Has3DNow0F0FOpcode {
25 // FIXME: The disassembler doesn't support Has3DNow0F0FOpcode yet.
2126 let isAsmParserOnly = 1;
2227 }
2328
2530 let Constraints = "$src1 = $dst" in {
2631 // MMXI_binop_rm_int - Simple MMX binary operator based on intrinsic.
2732 // When this is cleaned up, remove the FIXME from X86RecognizableInstr.cpp.
28 multiclass I3DNow_binop_rm opc, string Mnemonic> {
29 def rr : I3DNow
30 (ins VR64:$src1, VR64:$src2),
31 !strconcat(Mnemonic, "\t{$src2, $dst|$dst, $src2}"), []>;
32 def rm : I3DNow
33 (ins VR64:$src1, i64mem:$src2),
34 !strconcat(Mnemonic, "\t{$src2, $dst|$dst, $src2}"), []>;
33 multiclass I3DNow_binop_rm opc, string Mn> {
34 def rr : I3DNow_binop;
35 def rm : I3DNow_binop;
3536 }
3637 }
3738
5657 defm PMULHRW : I3DNow_binop_rm<0xB7, "pmulhrw">;
5758
5859
60 def FEMMS : I3DNow<0x0E, RawFrm, (outs), (ins), "femms", [(int_x86_mmx_femms)]>;
61
62 def PREFETCH : I3DNow<0x0D, MRM0m, (outs), (ins i32mem:$addr),
63 "prefetch $addr", []>;
64
65 // FIXME: Diassembler gets a bogus decode conflict.
66 let isAsmParserOnly = 1 in {
67 def PREFETCHW : I3DNow<0x0D, MRM1m, (outs), (ins i16mem:$addr),
68 "prefetchw $addr", []>;
69 }
5970
6071
6172 // TODO: Add support for the "3DNowA" instructions.
120120 }
121121
122122 //===----------------------------------------------------------------------===//
123 // MMX EMMS & FEMMS Instructions
123 // MMX EMMS Instruction
124124 //===----------------------------------------------------------------------===//
125125
126126 def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms",
127127 [(int_x86_mmx_emms)]>;
128 def MMX_FEMMS : MMXI<0x0E, RawFrm, (outs), (ins), "femms",
129 [(int_x86_mmx_femms)]>;
130128
131129 //===----------------------------------------------------------------------===//
132130 // MMX Scalar Instructions
6565 // CHECK: pmulhrw %mm2, %mm1 # encoding: [0x0f,0x0f,0xca,0xb7]
6666 pmulhrw %mm2, %mm1
6767
68
69 // CHECK: femms # encoding: [0x0f,0x0e]
70 femms
71
72 // CHECK: prefetch (%rax) # encoding: [0x0f,0x0d,0x00]
73 // CHECK: prefetchw (%rax) # encoding: [0x0f,0x0d,0x08]
74 prefetch (%rax)
75 prefetchw (%rax)