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[GlobalISel][X86] Fixing failures after https://reviews.llvm.org/D37775 The patch essentially makes sure that X86CallLowering adds proper G_COPY/G_TRUNC and G_ANYEXT/G_COPY when we are doing lowering of arguments/returns for floating point values passed on registers. Tests are updated accordingly Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D42287 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324665 91177308-0d34-0410-b5e6-96231b3b80d8 Alexander Ivchenko 2 years ago
21 changed file(s) with 1179 addition(s) and 693 deletion(s). Raw diff Collapse all Expand all
125125 void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
126126 CCValAssign &VA) override {
127127 MIB.addUse(PhysReg, RegState::Implicit);
128 unsigned ExtReg = extendRegister(ValVReg, VA);
128
129 unsigned ExtReg;
130 // If we are copying the value to a physical register with the
131 // size larger than the size of the value itself - build AnyExt
132 // to the size of the register first and only then do the copy.
133 // The example of that would be copying from s32 to xmm0, for which
134 // case ValVT == LocVT == MVT::f32. If LocSize and ValSize are not equal
135 // we expect normal extendRegister mechanism to work.
136 unsigned PhysRegSize =
137 MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI);
138 unsigned ValSize = VA.getValVT().getSizeInBits();
139 unsigned LocSize = VA.getLocVT().getSizeInBits();
140 if (PhysRegSize > ValSize && LocSize == ValSize) {
141 assert((PhysRegSize == 128 || PhysRegSize == 80) && "We expect that to be 128 bit");
142 auto MIB = MIRBuilder.buildAnyExt(LLT::scalar(PhysRegSize), ValVReg);
143 ExtReg = MIB->getOperand(0).getReg();
144 } else
145 ExtReg = extendRegister(ValVReg, VA);
146
129147 MIRBuilder.buildCopy(PhysReg, ExtReg);
130148 }
131149
228246 void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
229247 CCValAssign &VA) override {
230248 markPhysRegUsed(PhysReg);
249
231250 switch (VA.getLocInfo()) {
232 default:
251 default: {
252 // If we are copying the value from a physical register with the
253 // size larger than the size of the value itself - build the copy
254 // of the phys reg first and then build the truncation of that copy.
255 // The example of that would be copying from xmm0 to s32, for which
256 // case ValVT == LocVT == MVT::f32. If LocSize and ValSize are not equal
257 // we expect this to be handled in SExt/ZExt/AExt case.
258 unsigned PhysRegSize =
259 MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI);
260 unsigned ValSize = VA.getValVT().getSizeInBits();
261 unsigned LocSize = VA.getLocVT().getSizeInBits();
262 if (PhysRegSize > ValSize && LocSize == ValSize) {
263 auto Copy = MIRBuilder.buildCopy(LLT::scalar(PhysRegSize), PhysReg);
264 MIRBuilder.buildTrunc(ValVReg, Copy);
265 return;
266 }
267
233268 MIRBuilder.buildCopy(ValVReg, PhysReg);
234269 break;
270 }
235271 case CCValAssign::LocInfo::SExt:
236272 case CCValAssign::LocInfo::ZExt:
237273 case CCValAssign::LocInfo::AExt: {
103103 MachineFunction &MF) const;
104104 bool selectCondBranch(MachineInstr &I, MachineRegisterInfo &MRI,
105105 MachineFunction &MF) const;
106 bool selectTurnIntoCOPY(MachineInstr &I, MachineRegisterInfo &MRI,
107 const unsigned DstReg,
108 const TargetRegisterClass *DstRC,
109 const unsigned SrcReg,
110 const TargetRegisterClass *SrcRC) const;
106111 bool materializeFP(MachineInstr &I, MachineRegisterInfo &MRI,
107112 MachineFunction &MF) const;
108113 bool selectImplicitDefOrPHI(MachineInstr &I, MachineRegisterInfo &MRI) const;
639644 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
640645 }
641646
647 // Helper function for selectTrunc and selectAnyext.
648 // Returns true if DstRC lives on a floating register class and
649 // SrcRC lives on a 128-bit vector class.
650 static bool canTurnIntoCOPY(const TargetRegisterClass *DstRC,
651 const TargetRegisterClass *SrcRC) {
652 return (DstRC == &X86::FR32RegClass || DstRC == &X86::FR32XRegClass ||
653 DstRC == &X86::FR64RegClass || DstRC == &X86::FR64XRegClass) &&
654 (SrcRC == &X86::VR128RegClass || SrcRC == &X86::VR128XRegClass);
655 }
656
657 bool X86InstructionSelector::selectTurnIntoCOPY(
658 MachineInstr &I, MachineRegisterInfo &MRI, const unsigned DstReg,
659 const TargetRegisterClass *DstRC, const unsigned SrcReg,
660 const TargetRegisterClass *SrcRC) const {
661
662 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
663 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
664 DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
665 << " operand\n");
666 return false;
667 }
668 I.setDesc(TII.get(X86::COPY));
669 return true;
670 }
671
642672 bool X86InstructionSelector::selectTrunc(MachineInstr &I,
643673 MachineRegisterInfo &MRI,
644674 MachineFunction &MF) const {
658688 return false;
659689 }
660690
691 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB);
692 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB);
693
694 if (!DstRC || !SrcRC)
695 return false;
696
697 // If that's truncation of the value that lives on the vector class and goes
698 // into the floating class, just replace it with copy, as we are able to
699 // select it as a regular move.
700 if (canTurnIntoCOPY(DstRC, SrcRC))
701 return selectTurnIntoCOPY(I, MRI, DstReg, DstRC, SrcReg, SrcRC);
702
661703 if (DstRB.getID() != X86::GPRRegBankID)
662 return false;
663
664 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB);
665 if (!DstRC)
666 return false;
667
668 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB);
669 if (!SrcRC)
670704 return false;
671705
672706 unsigned SubIdx;
764798 assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
765799 "G_ANYEXT incorrect operand size");
766800
767 if (DstRB.getID() != X86::GPRRegBankID)
768 return false;
769
770801 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB);
771802 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB);
803
804 // If that's ANY_EXT of the value that lives on the floating class and goes
805 // into the vector class, just replace it with copy, as we are able to select
806 // it as a regular move.
807 if (canTurnIntoCOPY(SrcRC, DstRC))
808 return selectTurnIntoCOPY(I, MRI, SrcReg, SrcRC, DstReg, DstRC);
809
810 if (DstRB.getID() != X86::GPRRegBankID)
811 return false;
772812
773813 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
774814 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
9191 const LLT s16 = LLT::scalar(16);
9292 const LLT s32 = LLT::scalar(32);
9393 const LLT s64 = LLT::scalar(64);
94 const LLT s128 = LLT::scalar(128);
9495
9596 for (auto Ty : {p0, s1, s8, s16, s32})
9697 setAction({G_IMPLICIT_DEF, Ty}, Legal);
135136 setAction({G_SEXT, Ty}, Legal);
136137 setAction({G_ANYEXT, Ty}, Legal);
137138 }
139 setAction({G_ANYEXT, s128}, Legal);
138140
139141 // Comparison
140142 setAction({G_ICMP, s1}, Legal);
7272 return PMI_GPR32;
7373 case 64:
7474 return PMI_GPR64;
75 case 128:
76 return PMI_VEC128;
7577 break;
7678 default:
7779 llvm_unreachable("Unsupported register size.");
8284 return PMI_FP32;
8385 case 64:
8486 return PMI_FP64;
87 case 128:
88 return PMI_VEC128;
8589 default:
8690 llvm_unreachable("Unsupported register size.");
8791 }
189193 // Instruction having only floating-point operands (all scalars in VECRReg)
190194 getInstrPartialMappingIdxs(MI, MRI, /* isFP */ true, OpRegBankIdx);
191195 break;
196 case TargetOpcode::G_TRUNC:
197 case TargetOpcode::G_ANYEXT: {
198 auto &Op0 = MI.getOperand(0);
199 auto &Op1 = MI.getOperand(1);
200 const LLT Ty0 = MRI.getType(Op0.getReg());
201 const LLT Ty1 = MRI.getType(Op1.getReg());
202
203 bool isFPTrunc = (Ty0.getSizeInBits() == 32 || Ty0.getSizeInBits() == 64) &&
204 Ty1.getSizeInBits() == 128 && Opc == TargetOpcode::G_TRUNC;
205 bool isFPAnyExt =
206 Ty0.getSizeInBits() == 128 &&
207 (Ty1.getSizeInBits() == 32 || Ty1.getSizeInBits() == 64) &&
208 Opc == TargetOpcode::G_ANYEXT;
209
210 getInstrPartialMappingIdxs(MI, MRI, /* isFP */ isFPTrunc || isFPAnyExt,
211 OpRegBankIdx);
212 } break;
192213 default:
193214 // Track the bank of each register, use NotFP mapping (all scalars in GPRs)
194215 getInstrPartialMappingIdxs(MI, MRI, /* isFP */ false, OpRegBankIdx);
399399 ; X64-NEXT: pushq %rax
400400 ; X64-NEXT: .cfi_def_cfa_offset 16
401401 ; X64-NEXT: movq (%rdi), %rdi
402 ; X64-NEXT: movq (%rsi), %rcx
402 ; X64-NEXT: movq (%rsi), %rax
403 ; X64-NEXT: movq %rax, %xmm0
403404 ; X64-NEXT: movb $1, %al
404 ; X64-NEXT: movq %rcx, %xmm0
405405 ; X64-NEXT: callq variadic_callee
406406 ; X64-NEXT: popq %rax
407407 ; X64-NEXT: retq
221221 ; X32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.1, align 0)
222222 ; X32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
223223 ; X32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 4 from %fixed-stack.0, align 0)
224 ; X32: $fp0 = COPY [[LOAD1]](s32)
224 ; X32: [[ANYEXT:%[0-9]+]]:_(s80) = G_ANYEXT [[LOAD1]](s32)
225 ; X32: $fp0 = COPY [[ANYEXT]](s80)
225226 ; X32: RET 0, implicit $fp0
226227 ; X64-LABEL: name: test_float_args
227228 ; X64: bb.1 (%ir-block.0):
228229 ; X64: liveins: $xmm0, $xmm1
229 ; X64: [[COPY:%[0-9]+]]:_(s32) = COPY $xmm0
230 ; X64: [[COPY1:%[0-9]+]]:_(s32) = COPY $xmm1
231 ; X64: $xmm0 = COPY [[COPY1]](s32)
230 ; X64: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
231 ; X64: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128)
232 ; X64: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
233 ; X64: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128)
234 ; X64: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[TRUNC1]](s32)
235 ; X64: $xmm0 = COPY [[ANYEXT]](s128)
232236 ; X64: RET 0, implicit $xmm0
233237 ret float %arg2
234238 }
240244 ; X32: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 8 from %fixed-stack.1, align 0)
241245 ; X32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
242246 ; X32: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 8 from %fixed-stack.0, align 0)
243 ; X32: $fp0 = COPY [[LOAD1]](s64)
247 ; X32: [[ANYEXT:%[0-9]+]]:_(s80) = G_ANYEXT [[LOAD1]](s64)
248 ; X32: $fp0 = COPY [[ANYEXT]](s80)
244249 ; X32: RET 0, implicit $fp0
245250 ; X64-LABEL: name: test_double_args
246251 ; X64: bb.1 (%ir-block.0):
247252 ; X64: liveins: $xmm0, $xmm1
248 ; X64: [[COPY:%[0-9]+]]:_(s64) = COPY $xmm0
249 ; X64: [[COPY1:%[0-9]+]]:_(s64) = COPY $xmm1
250 ; X64: $xmm0 = COPY [[COPY1]](s64)
253 ; X64: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
254 ; X64: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128)
255 ; X64: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
256 ; X64: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128)
257 ; X64: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[TRUNC1]](s64)
258 ; X64: $xmm0 = COPY [[ANYEXT]](s128)
251259 ; X64: RET 0, implicit $xmm0
252260 ret double %arg2
253261 }
683691 ; X64: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[COPY1]](p0) :: (load 8 from %ir.val_ptr)
684692 ; X64: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp
685693 ; X64: $rdi = COPY [[LOAD]](p0)
686 ; X64: $xmm0 = COPY [[LOAD1]](s64)
694 ; X64: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[LOAD1]](s64)
695 ; X64: $xmm0 = COPY [[ANYEXT]](s128)
687696 ; X64: $al = MOV8ri 1
688697 ; X64: CALL64pcrel32 @variadic_callee, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $xmm0, implicit $al
689698 ; X64: ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp
2121 - { id: 0, class: _, preferred-register: '' }
2222 - { id: 1, class: _, preferred-register: '' }
2323 - { id: 2, class: _, preferred-register: '' }
24 - { id: 3, class: _, preferred-register: '' }
25 - { id: 4, class: _, preferred-register: '' }
26 - { id: 5, class: _, preferred-register: '' }
2427 liveins:
2528 fixedStack:
2629 stack:
3033 liveins: $xmm0, $xmm1
3134
3235 ; CHECK-LABEL: name: test_fadd_float
33 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $xmm0
34 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $xmm1
35 ; CHECK: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]]
36 ; CHECK: $xmm0 = COPY [[FADD]](s32)
36 ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
37 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128)
38 ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
39 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128)
40 ; CHECK: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[TRUNC]], [[TRUNC1]]
41 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FADD]](s32)
42 ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
3743 ; CHECK: RET 0, implicit $xmm0
38 %0(s32) = COPY $xmm0
39 %1(s32) = COPY $xmm1
40 %2(s32) = G_FADD %0, %1
41 $xmm0 = COPY %2(s32)
44 %2:_(s128) = COPY $xmm0
45 %0:_(s32) = G_TRUNC %2(s128)
46 %3:_(s128) = COPY $xmm1
47 %1:_(s32) = G_TRUNC %3(s128)
48 %4:_(s32) = G_FADD %0, %1
49 %5:_(s128) = G_ANYEXT %4(s32)
50 $xmm0 = COPY %5(s128)
4251 RET 0, implicit $xmm0
4352
4453 ...
5160 - { id: 0, class: _, preferred-register: '' }
5261 - { id: 1, class: _, preferred-register: '' }
5362 - { id: 2, class: _, preferred-register: '' }
63 - { id: 3, class: _, preferred-register: '' }
64 - { id: 4, class: _, preferred-register: '' }
65 - { id: 5, class: _, preferred-register: '' }
5466 liveins:
5567 fixedStack:
5668 stack:
6072 liveins: $xmm0, $xmm1
6173
6274 ; CHECK-LABEL: name: test_fadd_double
63 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $xmm0
64 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $xmm1
65 ; CHECK: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[COPY1]]
66 ; CHECK: $xmm0 = COPY [[FADD]](s64)
75 ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
76 ; CHECK: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128)
77 ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
78 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128)
79 ; CHECK: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[TRUNC]], [[TRUNC1]]
80 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FADD]](s64)
81 ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
6782 ; CHECK: RET 0, implicit $xmm0
68 %0(s64) = COPY $xmm0
69 %1(s64) = COPY $xmm1
70 %2(s64) = G_FADD %0, %1
71 $xmm0 = COPY %2(s64)
83 %2:_(s128) = COPY $xmm0
84 %0:_(s64) = G_TRUNC %2(s128)
85 %3:_(s128) = COPY $xmm1
86 %1:_(s64) = G_TRUNC %3(s128)
87 %4:_(s64) = G_FADD %0, %1
88 %5:_(s128) = G_ANYEXT %4(s64)
89 $xmm0 = COPY %5(s128)
7290 RET 0, implicit $xmm0
7391
7492 ...
2121 - { id: 0, class: _, preferred-register: '' }
2222 - { id: 1, class: _, preferred-register: '' }
2323 - { id: 2, class: _, preferred-register: '' }
24 - { id: 3, class: _, preferred-register: '' }
25 - { id: 4, class: _, preferred-register: '' }
26 - { id: 5, class: _, preferred-register: '' }
2427 liveins:
2528 fixedStack:
2629 stack:
3033 liveins: $xmm0, $xmm1
3134
3235 ; CHECK-LABEL: name: test_fdiv_float
33 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $xmm0
34 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $xmm1
35 ; CHECK: [[FDIV:%[0-9]+]]:_(s32) = G_FDIV [[COPY]], [[COPY1]]
36 ; CHECK: $xmm0 = COPY [[FDIV]](s32)
36 ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
37 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128)
38 ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
39 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128)
40 ; CHECK: [[FDIV:%[0-9]+]]:_(s32) = G_FDIV [[TRUNC]], [[TRUNC1]]
41 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FDIV]](s32)
42 ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
3743 ; CHECK: RET 0, implicit $xmm0
38 %0(s32) = COPY $xmm0
39 %1(s32) = COPY $xmm1
40 %2(s32) = G_FDIV %0, %1
41 $xmm0 = COPY %2(s32)
44 %2:_(s128) = COPY $xmm0
45 %0:_(s32) = G_TRUNC %2(s128)
46 %3:_(s128) = COPY $xmm1
47 %1:_(s32) = G_TRUNC %3(s128)
48 %4:_(s32) = G_FDIV %0, %1
49 %5:_(s128) = G_ANYEXT %4(s32)
50 $xmm0 = COPY %5(s128)
4251 RET 0, implicit $xmm0
4352
4453 ...
5160 - { id: 0, class: _, preferred-register: '' }
5261 - { id: 1, class: _, preferred-register: '' }
5362 - { id: 2, class: _, preferred-register: '' }
63 - { id: 3, class: _, preferred-register: '' }
64 - { id: 4, class: _, preferred-register: '' }
65 - { id: 5, class: _, preferred-register: '' }
5466 liveins:
5567 fixedStack:
5668 stack:
6072 liveins: $xmm0, $xmm1
6173
6274 ; CHECK-LABEL: name: test_fdiv_double
63 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $xmm0
64 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $xmm1
65 ; CHECK: [[FDIV:%[0-9]+]]:_(s64) = G_FDIV [[COPY]], [[COPY1]]
66 ; CHECK: $xmm0 = COPY [[FDIV]](s64)
75 ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
76 ; CHECK: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128)
77 ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
78 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128)
79 ; CHECK: [[FDIV:%[0-9]+]]:_(s64) = G_FDIV [[TRUNC]], [[TRUNC1]]
80 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FDIV]](s64)
81 ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
6782 ; CHECK: RET 0, implicit $xmm0
68 %0(s64) = COPY $xmm0
69 %1(s64) = COPY $xmm1
70 %2(s64) = G_FDIV %0, %1
71 $xmm0 = COPY %2(s64)
83 %2:_(s128) = COPY $xmm0
84 %0:_(s64) = G_TRUNC %2(s128)
85 %3:_(s128) = COPY $xmm1
86 %1:_(s64) = G_TRUNC %3(s128)
87 %4:_(s64) = G_FDIV %0, %1
88 %5:_(s128) = G_ANYEXT %4(s64)
89 $xmm0 = COPY %5(s128)
7290 RET 0, implicit $xmm0
7391
7492 ...
2121 - { id: 0, class: _, preferred-register: '' }
2222 - { id: 1, class: _, preferred-register: '' }
2323 - { id: 2, class: _, preferred-register: '' }
24 - { id: 3, class: _, preferred-register: '' }
25 - { id: 4, class: _, preferred-register: '' }
26 - { id: 5, class: _, preferred-register: '' }
2427 liveins:
2528 fixedStack:
2629 stack:
3033 liveins: $xmm0, $xmm1
3134
3235 ; CHECK-LABEL: name: test_fmul_float
33 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $xmm0
34 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $xmm1
35 ; CHECK: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]]
36 ; CHECK: $xmm0 = COPY [[FMUL]](s32)
36 ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
37 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128)
38 ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
39 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128)
40 ; CHECK: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[TRUNC]], [[TRUNC1]]
41 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FMUL]](s32)
42 ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
3743 ; CHECK: RET 0, implicit $xmm0
38 %0(s32) = COPY $xmm0
39 %1(s32) = COPY $xmm1
40 %2(s32) = G_FMUL %0, %1
41 $xmm0 = COPY %2(s32)
44 %2:_(s128) = COPY $xmm0
45 %0:_(s32) = G_TRUNC %2(s128)
46 %3:_(s128) = COPY $xmm1
47 %1:_(s32) = G_TRUNC %3(s128)
48 %4:_(s32) = G_FMUL %0, %1
49 %5:_(s128) = G_ANYEXT %4(s32)
50 $xmm0 = COPY %5(s128)
4251 RET 0, implicit $xmm0
4352
4453 ...
5160 - { id: 0, class: _, preferred-register: '' }
5261 - { id: 1, class: _, preferred-register: '' }
5362 - { id: 2, class: _, preferred-register: '' }
63 - { id: 3, class: _, preferred-register: '' }
64 - { id: 4, class: _, preferred-register: '' }
65 - { id: 5, class: _, preferred-register: '' }
5466 liveins:
5567 fixedStack:
5668 stack:
6072 liveins: $xmm0, $xmm1
6173
6274 ; CHECK-LABEL: name: test_fmul_double
63 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $xmm0
64 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $xmm1
65 ; CHECK: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[COPY1]]
66 ; CHECK: $xmm0 = COPY [[FMUL]](s64)
75 ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
76 ; CHECK: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128)
77 ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
78 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128)
79 ; CHECK: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[TRUNC]], [[TRUNC1]]
80 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FMUL]](s64)
81 ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
6782 ; CHECK: RET 0, implicit $xmm0
68 %0(s64) = COPY $xmm0
69 %1(s64) = COPY $xmm1
70 %2(s64) = G_FMUL %0, %1
71 $xmm0 = COPY %2(s64)
83 %2:_(s128) = COPY $xmm0
84 %0:_(s64) = G_TRUNC %2(s128)
85 %3:_(s128) = COPY $xmm1
86 %1:_(s64) = G_TRUNC %3(s128)
87 %4:_(s64) = G_FMUL %0, %1
88 %5:_(s128) = G_ANYEXT %4(s64)
89 $xmm0 = COPY %5(s128)
7290 RET 0, implicit $xmm0
7391
7492 ...
1616 registers:
1717 - { id: 0, class: _, preferred-register: '' }
1818 - { id: 1, class: _, preferred-register: '' }
19 - { id: 2, class: _, preferred-register: '' }
20 - { id: 3, class: _, preferred-register: '' }
1921 body: |
2022 bb.1.entry:
2123 liveins: $xmm0
2224
2325 ; ALL-LABEL: name: test
24 ; ALL: [[COPY:%[0-9]+]]:_(s32) = COPY $xmm0
25 ; ALL: [[FPEXT:%[0-9]+]]:_(s64) = G_FPEXT [[COPY]](s32)
26 ; ALL: $xmm0 = COPY [[FPEXT]](s64)
26 ; ALL: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
27 ; ALL: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128)
28 ; ALL: [[FPEXT:%[0-9]+]]:_(s64) = G_FPEXT [[TRUNC]](s32)
29 ; ALL: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FPEXT]](s64)
30 ; ALL: $xmm0 = COPY [[ANYEXT]](s128)
2731 ; ALL: RET 0, implicit $xmm0
28 %0(s32) = COPY $xmm0
29 %1(s64) = G_FPEXT %0(s32)
30 $xmm0 = COPY %1(s64)
32 %1:_(s128) = COPY $xmm0
33 %0:_(s32) = G_TRUNC %1(s128)
34 %2:_(s64) = G_FPEXT %0(s32)
35 %3:_(s128) = G_ANYEXT %2(s64)
36 $xmm0 = COPY %3(s128)
3137 RET 0, implicit $xmm0
3238
3339 ...
2121 - { id: 0, class: _, preferred-register: '' }
2222 - { id: 1, class: _, preferred-register: '' }
2323 - { id: 2, class: _, preferred-register: '' }
24 - { id: 3, class: _, preferred-register: '' }
25 - { id: 4, class: _, preferred-register: '' }
26 - { id: 5, class: _, preferred-register: '' }
2427 liveins:
2528 fixedStack:
2629 stack:
3033 liveins: $xmm0, $xmm1
3134
3235 ; CHECK-LABEL: name: test_fsub_float
33 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $xmm0
34 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $xmm1
35 ; CHECK: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[COPY1]]
36 ; CHECK: $xmm0 = COPY [[FSUB]](s32)
36 ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
37 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128)
38 ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
39 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128)
40 ; CHECK: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[TRUNC]], [[TRUNC1]]
41 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FSUB]](s32)
42 ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
3743 ; CHECK: RET 0, implicit $xmm0
38 %0(s32) = COPY $xmm0
39 %1(s32) = COPY $xmm1
40 %2(s32) = G_FSUB %0, %1
41 $xmm0 = COPY %2(s32)
44 %2:_(s128) = COPY $xmm0
45 %0:_(s32) = G_TRUNC %2(s128)
46 %3:_(s128) = COPY $xmm1
47 %1:_(s32) = G_TRUNC %3(s128)
48 %4:_(s32) = G_FSUB %0, %1
49 %5:_(s128) = G_ANYEXT %4(s32)
50 $xmm0 = COPY %5(s128)
4251 RET 0, implicit $xmm0
4352
4453 ...
5160 - { id: 0, class: _, preferred-register: '' }
5261 - { id: 1, class: _, preferred-register: '' }
5362 - { id: 2, class: _, preferred-register: '' }
63 - { id: 3, class: _, preferred-register: '' }
64 - { id: 4, class: _, preferred-register: '' }
65 - { id: 5, class: _, preferred-register: '' }
5466 liveins:
5567 fixedStack:
5668 stack:
6072 liveins: $xmm0, $xmm1
6173
6274 ; CHECK-LABEL: name: test_fsub_double
63 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $xmm0
64 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $xmm1
65 ; CHECK: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[COPY1]]
66 ; CHECK: $xmm0 = COPY [[FSUB]](s64)
75 ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
76 ; CHECK: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128)
77 ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
78 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128)
79 ; CHECK: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[TRUNC]], [[TRUNC1]]
80 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FSUB]](s64)
81 ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
6782 ; CHECK: RET 0, implicit $xmm0
68 %0(s64) = COPY $xmm0
69 %1(s64) = COPY $xmm1
70 %2(s64) = G_FSUB %0, %1
71 $xmm0 = COPY %2(s64)
83 %2:_(s128) = COPY $xmm0
84 %0:_(s64) = G_TRUNC %2(s128)
85 %3:_(s128) = COPY $xmm1
86 %1:_(s64) = G_TRUNC %3(s128)
87 %4:_(s64) = G_FSUB %0, %1
88 %5:_(s128) = G_ANYEXT %4(s64)
89 $xmm0 = COPY %5(s128)
7290 RET 0, implicit $xmm0
7391
7492 ...
472472
473473 body: |
474474 ; ALL-LABEL: name: test_float
475 ; ALL: bb.0.{{[a-zA-Z0-9]+}}:
476 ; ALL: successors: %bb.1(0x40000000), %bb.2(0x40000000)
475 ; ALL: bb.0.entry:
476 ; ALL: successors: %bb.2(0x40000000), %bb.1(0x40000000)
477477 ; ALL: liveins: $edi, $xmm0, $xmm1
478478 ; ALL: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
479 ; ALL: [[COPY1:%[0-9]+]]:_(s32) = COPY $xmm0
480 ; ALL: [[COPY2:%[0-9]+]]:_(s32) = COPY $xmm1
481 ; ALL: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
482 ; ALL: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
483 ; ALL: G_BRCOND [[ICMP]](s1), %bb.1
484 ; ALL: G_BR %bb.2
485 ; ALL: bb.1.cond.true:
486 ; ALL: successors: %bb.3(0x80000000)
487 ; ALL: G_BR %bb.3
488 ; ALL: bb.2.cond.false:
489 ; ALL: successors: %bb.3(0x80000000)
490 ; ALL: bb.3.cond.end:
491 ; ALL: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY1]](s32), %bb.1, [[COPY2]](s32), %bb.2
492 ; ALL: $xmm0 = COPY [[PHI]](s32)
479 ; ALL: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm0
480 ; ALL: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128)
481 ; ALL: [[COPY2:%[0-9]+]]:_(s128) = COPY $xmm1
482 ; ALL: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s128)
483 ; ALL: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
484 ; ALL: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
485 ; ALL: G_BRCOND [[ICMP]](s1), %bb.2
486 ; ALL: bb.1.cond.false:
487 ; ALL: successors: %bb.2(0x80000000)
488 ; ALL: bb.2.cond.end:
489 ; ALL: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[TRUNC1]](s32), %bb.1, [[TRUNC]](s32), %bb.0
490 ; ALL: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[PHI]](s32)
491 ; ALL: $xmm0 = COPY [[ANYEXT]](s128)
493492 ; ALL: RET 0, implicit $xmm0
494493 bb.1.entry:
495 successors: %bb.2(0x40000000), %bb.3(0x40000000)
494 successors: %bb.3(0x40000000), %bb.2(0x40000000)
496495 liveins: $edi, $xmm0, $xmm1
497496
498 %0(s32) = COPY $edi
499 %1(s32) = COPY $xmm0
500 %2(s32) = COPY $xmm1
501 %3(s32) = G_CONSTANT i32 0
502 %4(s1) = G_ICMP intpred(sgt), %0(s32), %3
503 G_BRCOND %4(s1), %bb.2
504 G_BR %bb.3
505
506 bb.2.cond.true:
507 successors: %bb.4(0x80000000)
508
509 G_BR %bb.4
510
511 bb.3.cond.false:
512 successors: %bb.4(0x80000000)
513
514
515 bb.4.cond.end:
516 %5(s32) = G_PHI %1(s32), %bb.2, %2(s32), %bb.3
517 $xmm0 = COPY %5(s32)
497 %0:_(s32) = COPY $edi
498 %3:_(s128) = COPY $xmm0
499 %1:_(s32) = G_TRUNC %3(s128)
500 %4:_(s128) = COPY $xmm1
501 %2:_(s32) = G_TRUNC %4(s128)
502 %5:_(s32) = G_CONSTANT i32 0
503 %6:_(s1) = G_ICMP intpred(sgt), %0(s32), %5
504 G_BRCOND %6(s1), %bb.3
505
506 bb.2.cond.false:
507 successors: %bb.3(0x80000000)
508
509
510 bb.3.cond.end:
511 %7:_(s32) = G_PHI %2(s32), %bb.2, %1(s32), %bb.1
512 %8:_(s128) = G_ANYEXT %7(s32)
513 $xmm0 = COPY %8(s128)
518514 RET 0, implicit $xmm0
519515
520516 ...
531527 - { id: 3, class: _, preferred-register: '' }
532528 - { id: 4, class: _, preferred-register: '' }
533529 - { id: 5, class: _, preferred-register: '' }
530 - { id: 6, class: _, preferred-register: '' }
531 - { id: 7, class: _, preferred-register: '' }
532 - { id: 8, class: _, preferred-register: '' }
534533 liveins:
535534 fixedStack:
536535 stack:
540539
541540 body: |
542541 ; ALL-LABEL: name: test_double
543 ; ALL: bb.0.{{[a-zA-Z0-9]+}}:
544 ; ALL: successors: %bb.1(0x40000000), %bb.2(0x40000000)
542 ; ALL: bb.0.entry:
543 ; ALL: successors: %bb.2(0x40000000), %bb.1(0x40000000)
545544 ; ALL: liveins: $edi, $xmm0, $xmm1
546545 ; ALL: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
547 ; ALL: [[COPY1:%[0-9]+]]:_(s64) = COPY $xmm0
548 ; ALL: [[COPY2:%[0-9]+]]:_(s64) = COPY $xmm1
549 ; ALL: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
550 ; ALL: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
551 ; ALL: G_BRCOND [[ICMP]](s1), %bb.1
552 ; ALL: G_BR %bb.2
553 ; ALL: bb.1.cond.true:
554 ; ALL: successors: %bb.3(0x80000000)
555 ; ALL: G_BR %bb.3
556 ; ALL: bb.2.cond.false:
557 ; ALL: successors: %bb.3(0x80000000)
558 ; ALL: bb.3.cond.end:
559 ; ALL: [[PHI:%[0-9]+]]:_(s64) = G_PHI [[COPY1]](s64), %bb.1, [[COPY2]](s64), %bb.2
560 ; ALL: $xmm0 = COPY [[PHI]](s64)
546 ; ALL: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm0
547 ; ALL: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128)
548 ; ALL: [[COPY2:%[0-9]+]]:_(s128) = COPY $xmm1
549 ; ALL: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY2]](s128)
550 ; ALL: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
551 ; ALL: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
552 ; ALL: G_BRCOND [[ICMP]](s1), %bb.2
553 ; ALL: bb.1.cond.false:
554 ; ALL: successors: %bb.2(0x80000000)
555 ; ALL: bb.2.cond.end:
556 ; ALL: [[PHI:%[0-9]+]]:_(s64) = G_PHI [[TRUNC1]](s64), %bb.1, [[TRUNC]](s64), %bb.0
557 ; ALL: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[PHI]](s64)
558 ; ALL: $xmm0 = COPY [[ANYEXT]](s128)
561559 ; ALL: RET 0, implicit $xmm0
562560 bb.1.entry:
563 successors: %bb.2(0x40000000), %bb.3(0x40000000)
561 successors: %bb.3(0x40000000), %bb.2(0x40000000)
564562 liveins: $edi, $xmm0, $xmm1
565563
566 %0(s32) = COPY $edi
567 %1(s64) = COPY $xmm0
568 %2(s64) = COPY $xmm1
569 %3(s32) = G_CONSTANT i32 0
570 %4(s1) = G_ICMP intpred(sgt), %0(s32), %3
571 G_BRCOND %4(s1), %bb.2
572 G_BR %bb.3
573
574 bb.2.cond.true:
575 successors: %bb.4(0x80000000)
576
577 G_BR %bb.4
578
579 bb.3.cond.false:
580 successors: %bb.4(0x80000000)
581
582
583 bb.4.cond.end:
584 %5(s64) = G_PHI %1(s64), %bb.2, %2(s64), %bb.3
585 $xmm0 = COPY %5(s64)
564 %0:_(s32) = COPY $edi
565 %3:_(s128) = COPY $xmm0
566 %1:_(s64) = G_TRUNC %3(s128)
567 %4:_(s128) = COPY $xmm1
568 %2:_(s64) = G_TRUNC %4(s128)
569 %5:_(s32) = G_CONSTANT i32 0
570 %6:_(s1) = G_ICMP intpred(sgt), %0(s32), %5
571 G_BRCOND %6(s1), %bb.3
572
573 bb.2.cond.false:
574 successors: %bb.3(0x80000000)
575
576
577 bb.3.cond.end:
578 %7:_(s64) = G_PHI %2(s64), %bb.2, %1(s64), %bb.1
579 %8:_(s128) = G_ANYEXT %7(s64)
580 $xmm0 = COPY %8(s128)
586581 RET 0, implicit $xmm0
587582
588583 ...
446446 - { id: 0, class: _ }
447447 - { id: 1, class: _ }
448448 - { id: 2, class: _ }
449 - { id: 3, class: _ }
450 - { id: 4, class: _ }
451 - { id: 5, class: _ }
449452 body: |
450453 bb.1 (%ir-block.0):
451454 liveins: $xmm0, $xmm1
452455
453456 ; FAST-LABEL: name: test_add_float
454457 ; FAST: liveins: $xmm0, $xmm1
455 ; FAST: [[COPY:%[0-9]+]]:vecr(s32) = COPY $xmm0
456 ; FAST: [[COPY1:%[0-9]+]]:vecr(s32) = COPY $xmm1
457 ; FAST: [[FADD:%[0-9]+]]:vecr(s32) = G_FADD [[COPY]], [[COPY1]]
458 ; FAST: $xmm0 = COPY [[FADD]](s32)
458 ; FAST: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
459 ; FAST: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128)
460 ; FAST: [[COPY1:%[0-9]+]]:vecr(s128) = COPY $xmm1
461 ; FAST: [[TRUNC1:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY1]](s128)
462 ; FAST: [[FADD:%[0-9]+]]:vecr(s32) = G_FADD [[TRUNC]], [[TRUNC1]]
463 ; FAST: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[FADD]](s32)
464 ; FAST: $xmm0 = COPY [[ANYEXT]](s128)
459465 ; FAST: RET 0, implicit $xmm0
460466 ; GREEDY-LABEL: name: test_add_float
461467 ; GREEDY: liveins: $xmm0, $xmm1
462 ; GREEDY: [[COPY:%[0-9]+]]:vecr(s32) = COPY $xmm0
463 ; GREEDY: [[COPY1:%[0-9]+]]:vecr(s32) = COPY $xmm1
464 ; GREEDY: [[FADD:%[0-9]+]]:vecr(s32) = G_FADD [[COPY]], [[COPY1]]
465 ; GREEDY: $xmm0 = COPY [[FADD]](s32)
468 ; GREEDY: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
469 ; GREEDY: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128)
470 ; GREEDY: [[COPY1:%[0-9]+]]:vecr(s128) = COPY $xmm1
471 ; GREEDY: [[TRUNC1:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY1]](s128)
472 ; GREEDY: [[FADD:%[0-9]+]]:vecr(s32) = G_FADD [[TRUNC]], [[TRUNC1]]
473 ; GREEDY: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[FADD]](s32)
474 ; GREEDY: $xmm0 = COPY [[ANYEXT]](s128)
466475 ; GREEDY: RET 0, implicit $xmm0
467 %0(s32) = COPY $xmm0
468 %1(s32) = COPY $xmm1
469 %2(s32) = G_FADD %0, %1
470 $xmm0 = COPY %2(s32)
476 %2:_(s128) = COPY $xmm0
477 %0:_(s32) = G_TRUNC %2(s128)
478 %3:_(s128) = COPY $xmm1
479 %1:_(s32) = G_TRUNC %3(s128)
480 %4:_(s32) = G_FADD %0, %1
481 %5:_(s128) = G_ANYEXT %4(s32)
482 $xmm0 = COPY %5(s128)
471483 RET 0, implicit $xmm0
472484
473485 ...
482494 - { id: 0, class: _ }
483495 - { id: 1, class: _ }
484496 - { id: 2, class: _ }
497 - { id: 3, class: _ }
498 - { id: 4, class: _ }
499 - { id: 5, class: _ }
485500 body: |
486501 bb.1 (%ir-block.0):
487502 liveins: $xmm0, $xmm1
488503
489504 ; FAST-LABEL: name: test_add_double
490505 ; FAST: liveins: $xmm0, $xmm1
491 ; FAST: [[COPY:%[0-9]+]]:vecr(s64) = COPY $xmm0
492 ; FAST: [[COPY1:%[0-9]+]]:vecr(s64) = COPY $xmm1
493 ; FAST: [[FADD:%[0-9]+]]:vecr(s64) = G_FADD [[COPY]], [[COPY1]]
494 ; FAST: $xmm0 = COPY [[FADD]](s64)
506 ; FAST: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
507 ; FAST: [[TRUNC:%[0-9]+]]:vecr(s64) = G_TRUNC [[COPY]](s128)
508 ; FAST: [[COPY1:%[0-9]+]]:vecr(s128) = COPY $xmm1
509 ; FAST: [[TRUNC1:%[0-9]+]]:vecr(s64) = G_TRUNC [[COPY1]](s128)
510 ; FAST: [[FADD:%[0-9]+]]:vecr(s64) = G_FADD [[TRUNC]], [[TRUNC1]]
511 ; FAST: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[FADD]](s64)
512 ; FAST: $xmm0 = COPY [[ANYEXT]](s128)
495513 ; FAST: RET 0, implicit $xmm0
496514 ; GREEDY-LABEL: name: test_add_double
497515 ; GREEDY: liveins: $xmm0, $xmm1
498 ; GREEDY: [[COPY:%[0-9]+]]:vecr(s64) = COPY $xmm0
499 ; GREEDY: [[COPY1:%[0-9]+]]:vecr(s64) = COPY $xmm1
500 ; GREEDY: [[FADD:%[0-9]+]]:vecr(s64) = G_FADD [[COPY]], [[COPY1]]
501 ; GREEDY: $xmm0 = COPY [[FADD]](s64)
516 ; GREEDY: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
517 ; GREEDY: [[TRUNC:%[0-9]+]]:vecr(s64) = G_TRUNC [[COPY]](s128)
518 ; GREEDY: [[COPY1:%[0-9]+]]:vecr(s128) = COPY $xmm1
519 ; GREEDY: [[TRUNC1:%[0-9]+]]:vecr(s64) = G_TRUNC [[COPY1]](s128)
520 ; GREEDY: [[FADD:%[0-9]+]]:vecr(s64) = G_FADD [[TRUNC]], [[TRUNC1]]
521 ; GREEDY: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[FADD]](s64)
522 ; GREEDY: $xmm0 = COPY [[ANYEXT]](s128)
502523 ; GREEDY: RET 0, implicit $xmm0
503 %0(s64) = COPY $xmm0
504 %1(s64) = COPY $xmm1
505 %2(s64) = G_FADD %0, %1
506 $xmm0 = COPY %2(s64)
524 %2:_(s128) = COPY $xmm0
525 %0:_(s64) = G_TRUNC %2(s128)
526 %3:_(s128) = COPY $xmm1
527 %1:_(s64) = G_TRUNC %3(s128)
528 %4:_(s64) = G_FADD %0, %1
529 %5:_(s128) = G_ANYEXT %4(s64)
530 $xmm0 = COPY %5(s128)
507531 RET 0, implicit $xmm0
508532
509533 ...
841865 ; FAST-LABEL: name: test_load_float
842866 ; FAST: [[COPY:%[0-9]+]]:gpr(p0) = COPY $rdi
843867 ; FAST: [[LOAD:%[0-9]+]]:gpr(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.p1)
844 ; FAST: $xmm0 = COPY [[LOAD]](s32)
868 ; FAST: [[COPY1:%[0-9]+]]:vecr(s32) = COPY [[LOAD]](s32)
869 ; FAST: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[COPY1]](s32)
870 ; FAST: $xmm0 = COPY [[ANYEXT]](s128)
845871 ; FAST: RET 0, implicit $xmm0
846872 ; GREEDY-LABEL: name: test_load_float
847873 ; GREEDY: [[COPY:%[0-9]+]]:gpr(p0) = COPY $rdi
848874 ; GREEDY: [[LOAD:%[0-9]+]]:gpr(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.p1)
849 ; GREEDY: $xmm0 = COPY [[LOAD]](s32)
875 ; GREEDY: [[COPY1:%[0-9]+]]:vecr(s32) = COPY [[LOAD]](s32)
876 ; GREEDY: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[COPY1]](s32)
877 ; GREEDY: $xmm0 = COPY [[ANYEXT]](s128)
850878 ; GREEDY: RET 0, implicit $xmm0
851 %0(p0) = COPY $rdi
852 %1(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1)
853 $xmm0 = COPY %1(s32)
879 %0:_(p0) = COPY $rdi
880 %1:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1)
881 %2:_(s128) = G_ANYEXT %1(s32)
882 $xmm0 = COPY %2(s128)
854883 RET 0, implicit $xmm0
855884
856885 ...
870899 ; FAST-LABEL: name: test_load_double
871900 ; FAST: [[COPY:%[0-9]+]]:gpr(p0) = COPY $rdi
872901 ; FAST: [[LOAD:%[0-9]+]]:gpr(s64) = G_LOAD [[COPY]](p0) :: (load 8 from %ir.p1)
873 ; FAST: $xmm0 = COPY [[LOAD]](s64)
902 ; FAST: [[COPY1:%[0-9]+]]:vecr(s64) = COPY [[LOAD]](s64)
903 ; FAST: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[COPY1]](s64)
904 ; FAST: $xmm0 = COPY [[ANYEXT]](s128)
874905 ; FAST: RET 0, implicit $xmm0
875906 ; GREEDY-LABEL: name: test_load_double
876907 ; GREEDY: [[COPY:%[0-9]+]]:gpr(p0) = COPY $rdi
877908 ; GREEDY: [[LOAD:%[0-9]+]]:gpr(s64) = G_LOAD [[COPY]](p0) :: (load 8 from %ir.p1)
878 ; GREEDY: $xmm0 = COPY [[LOAD]](s64)
909 ; GREEDY: [[COPY1:%[0-9]+]]:vecr(s64) = COPY [[LOAD]](s64)
910 ; GREEDY: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[COPY1]](s64)
911 ; GREEDY: $xmm0 = COPY [[ANYEXT]](s128)
879912 ; GREEDY: RET 0, implicit $xmm0
880 %0(p0) = COPY $rdi
881 %1(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1)
882 $xmm0 = COPY %1(s64)
913 %0:_(p0) = COPY $rdi
914 %1:_(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1)
915 %2:_(s128) = G_ANYEXT %1(s64)
916 $xmm0 = COPY %2(s128)
883917 RET 0, implicit $xmm0
884918
885919 ...
9931027 liveins: $rdi, $xmm0
9941028
9951029 ; FAST-LABEL: name: test_store_float
996 ; FAST: [[COPY:%[0-9]+]]:vecr(s32) = COPY $xmm0
1030 ; FAST: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
1031 ; FAST: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128)
9971032 ; FAST: [[COPY1:%[0-9]+]]:gpr(p0) = COPY $rdi
998 ; FAST: [[COPY2:%[0-9]+]]:gpr(s32) = COPY [[COPY]](s32)
1033 ; FAST: [[COPY2:%[0-9]+]]:gpr(s32) = COPY [[TRUNC]](s32)
9991034 ; FAST: G_STORE [[COPY2]](s32), [[COPY1]](p0) :: (store 4 into %ir.p1)
10001035 ; FAST: $rax = COPY [[COPY1]](p0)
10011036 ; FAST: RET 0, implicit $rax
10021037 ; GREEDY-LABEL: name: test_store_float
1003 ; GREEDY: [[COPY:%[0-9]+]]:vecr(s32) = COPY $xmm0
1038 ; GREEDY: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
1039 ; GREEDY: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128)
10041040 ; GREEDY: [[COPY1:%[0-9]+]]:gpr(p0) = COPY $rdi
1005 ; GREEDY: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store 4 into %ir.p1)
1041 ; GREEDY: G_STORE [[TRUNC]](s32), [[COPY1]](p0) :: (store 4 into %ir.p1)
10061042 ; GREEDY: $rax = COPY [[COPY1]](p0)
10071043 ; GREEDY: RET 0, implicit $rax
1008 %0(s32) = COPY $xmm0
1009 %1(p0) = COPY $rdi
1010
1011
1012
1044 %2:_(s128) = COPY $xmm0
1045 %0:_(s32) = G_TRUNC %2(s128)
1046 %1:_(p0) = COPY $rdi
10131047 G_STORE %0(s32), %1(p0) :: (store 4 into %ir.p1)
10141048 $rax = COPY %1(p0)
10151049 RET 0, implicit $rax
10321066 liveins: $rdi, $xmm0
10331067
10341068 ; FAST-LABEL: name: test_store_double
1035 ; FAST: [[COPY:%[0-9]+]]:vecr(s64) = COPY $xmm0
1069 ; FAST: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
1070 ; FAST: [[TRUNC:%[0-9]+]]:vecr(s64) = G_TRUNC [[COPY]](s128)
10361071 ; FAST: [[COPY1:%[0-9]+]]:gpr(p0) = COPY $rdi
1037 ; FAST: [[COPY2:%[0-9]+]]:gpr(s64) = COPY [[COPY]](s64)
1072 ; FAST: [[COPY2:%[0-9]+]]:gpr(s64) = COPY [[TRUNC]](s64)
10381073 ; FAST: G_STORE [[COPY2]](s64), [[COPY1]](p0) :: (store 8 into %ir.p1)
10391074 ; FAST: $rax = COPY [[COPY1]](p0)
10401075 ; FAST: RET 0, implicit $rax
10411076 ; GREEDY-LABEL: name: test_store_double
1042 ; GREEDY: [[COPY:%[0-9]+]]:vecr(s64) = COPY $xmm0
1077 ; GREEDY: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
1078 ; GREEDY: [[TRUNC:%[0-9]+]]:vecr(s64) = G_TRUNC [[COPY]](s128)
10431079 ; GREEDY: [[COPY1:%[0-9]+]]:gpr(p0) = COPY $rdi
1044 ; GREEDY: G_STORE [[COPY]](s64), [[COPY1]](p0) :: (store 8 into %ir.p1)
1080 ; GREEDY: G_STORE [[TRUNC]](s64), [[COPY1]](p0) :: (store 8 into %ir.p1)
10451081 ; GREEDY: $rax = COPY [[COPY1]](p0)
10461082 ; GREEDY: RET 0, implicit $rax
1047 %0(s64) = COPY $xmm0
1048 %1(p0) = COPY $rdi
1049
1050
1051
1052
1083 %2:_(s128) = COPY $xmm0
1084 %0:_(s64) = G_TRUNC %2(s128)
1085 %1:_(p0) = COPY $rdi
10531086 G_STORE %0(s64), %1(p0) :: (store 8 into %ir.p1)
10541087 $rax = COPY %1(p0)
10551088 RET 0, implicit $rax
15101543 legalized: true
15111544 regBankSelected: false
15121545 registers:
1513 - { id: 0, class: _, preferred-register: '' }
1546 - { id: 1, class: _, preferred-register: '' }
15141547 liveins:
15151548 fixedStack:
15161549 stack:
15181551 body: |
15191552 bb.1 (%ir-block.0):
15201553 ; FAST-LABEL: name: test_undef3
1521 ; FAST: [[DEF:%[0-9]+]]:gpr(s32) = G_IMPLICIT_DEF
1522 ; FAST: $xmm0 = COPY [[DEF]](s32)
1554 ; FAST: [[DEF:%[0-9]+]]:vecr(s128) = G_IMPLICIT_DEF
1555 ; FAST: $xmm0 = COPY [[DEF]](s128)
15231556 ; FAST: RET 0, implicit $xmm0
15241557 ; GREEDY-LABEL: name: test_undef3
1525 ; GREEDY: [[DEF:%[0-9]+]]:gpr(s32) = G_IMPLICIT_DEF
1526 ; GREEDY: $xmm0 = COPY [[DEF]](s32)
1558 ; GREEDY: [[DEF:%[0-9]+]]:vecr(s128) = G_IMPLICIT_DEF
1559 ; GREEDY: $xmm0 = COPY [[DEF]](s128)
15271560 ; GREEDY: RET 0, implicit $xmm0
1528 %0(s32) = G_IMPLICIT_DEF
1529 $xmm0 = COPY %0(s32)
1561 %1(s128) = G_IMPLICIT_DEF
1562 $xmm0 = COPY %1(s128)
15301563 RET 0, implicit $xmm0
15311564
15321565 ...
15391572 - { id: 0, class: _, preferred-register: '' }
15401573 - { id: 1, class: _, preferred-register: '' }
15411574 - { id: 2, class: _, preferred-register: '' }
1575 - { id: 3, class: _, preferred-register: '' }
1576 - { id: 4, class: _, preferred-register: '' }
15421577 liveins:
15431578 fixedStack:
15441579 stack:
15481583 liveins: $xmm0
15491584
15501585 ; FAST-LABEL: name: test_undef4
1551 ; FAST: [[COPY:%[0-9]+]]:vecr(s32) = COPY $xmm0
1586 ; FAST: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
1587 ; FAST: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128)
15521588 ; FAST: [[DEF:%[0-9]+]]:gpr(s32) = G_IMPLICIT_DEF
15531589 ; FAST: [[COPY1:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32)
1554 ; FAST: [[FADD:%[0-9]+]]:vecr(s32) = G_FADD [[COPY]], [[COPY1]]
1555 ; FAST: $xmm0 = COPY [[FADD]](s32)
1590 ; FAST: [[FADD:%[0-9]+]]:vecr(s32) = G_FADD [[TRUNC]], [[COPY1]]
1591 ; FAST: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[FADD]](s32)
1592 ; FAST: $xmm0 = COPY [[ANYEXT]](s128)
15561593 ; FAST: RET 0, implicit $xmm0
15571594 ; GREEDY-LABEL: name: test_undef4
1558 ; GREEDY: [[COPY:%[0-9]+]]:vecr(s32) = COPY $xmm0
1595 ; GREEDY: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
1596 ; GREEDY: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128)
15591597 ; GREEDY: [[DEF:%[0-9]+]]:gpr(s32) = G_IMPLICIT_DEF
15601598 ; GREEDY: [[COPY1:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32)
1561 ; GREEDY: [[FADD:%[0-9]+]]:vecr(s32) = G_FADD [[COPY]], [[COPY1]]
1562 ; GREEDY: $xmm0 = COPY [[FADD]](s32)
1599 ; GREEDY: [[FADD:%[0-9]+]]:vecr(s32) = G_FADD [[TRUNC]], [[COPY1]]
1600 ; GREEDY: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[FADD]](s32)
1601 ; GREEDY: $xmm0 = COPY [[ANYEXT]](s128)
15631602 ; GREEDY: RET 0, implicit $xmm0
1564 %0(s32) = COPY $xmm0
1565 %1(s32) = G_IMPLICIT_DEF
1566 %2(s32) = G_FADD %0, %1
1567 $xmm0 = COPY %2(s32)
1603 %1:_(s128) = COPY $xmm0
1604 %0:_(s32) = G_TRUNC %1(s128)
1605 %2:_(s32) = G_IMPLICIT_DEF
1606 %3:_(s32) = G_FADD %0, %2
1607 %4:_(s128) = G_ANYEXT %3(s32)
1608 $xmm0 = COPY %4(s128)
15681609 RET 0, implicit $xmm0
15691610
15701611 ...
16641705 body: |
16651706 ; FAST-LABEL: name: test_float
16661707 ; FAST: bb.0.entry:
1667 ; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000)
1708 ; FAST: successors: %bb.2(0x40000000), %bb.1(0x40000000)
16681709 ; FAST: liveins: $edi, $xmm0, $xmm1
16691710 ; FAST: [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi
1670 ; FAST: [[COPY1:%[0-9]+]]:vecr(s32) = COPY $xmm0
1671 ; FAST: [[COPY2:%[0-9]+]]:vecr(s32) = COPY $xmm1
1711 ; FAST: [[COPY1:%[0-9]+]]:vecr(s128) = COPY $xmm0
1712 ; FAST: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY1]](s128)
1713 ; FAST: [[COPY2:%[0-9]+]]:vecr(s128) = COPY $xmm1
1714 ; FAST: [[TRUNC1:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY2]](s128)
16721715 ; FAST: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
16731716 ; FAST: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
1674 ; FAST: G_BRCOND [[ICMP]](s1), %bb.1
1675 ; FAST: G_BR %bb.2
1676 ; FAST: bb.1.cond.true:
1677 ; FAST: successors: %bb.3(0x80000000)
1678 ; FAST: G_BR %bb.3
1679 ; FAST: bb.2.cond.false:
1680 ; FAST: successors: %bb.3(0x80000000)
1681 ; FAST: bb.3.cond.end:
1682 ; FAST: [[PHI:%[0-9]+]]:vecr(s32) = G_PHI [[COPY1]](s32), %bb.1, [[COPY2]](s32), %bb.2
1683 ; FAST: $xmm0 = COPY [[PHI]](s32)
1717 ; FAST: G_BRCOND [[ICMP]](s1), %bb.2
1718 ; FAST: bb.1.cond.false:
1719 ; FAST: successors: %bb.2(0x80000000)
1720 ; FAST: bb.2.cond.end:
1721 ; FAST: [[PHI:%[0-9]+]]:vecr(s32) = G_PHI [[TRUNC1]](s32), %bb.1, [[TRUNC]](s32), %bb.0
1722 ; FAST: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[PHI]](s32)
1723 ; FAST: $xmm0 = COPY [[ANYEXT]](s128)
16841724 ; FAST: RET 0, implicit $xmm0
16851725 ; GREEDY-LABEL: name: test_float
16861726 ; GREEDY: bb.0.entry:
1687 ; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)
1727 ; GREEDY: successors: %bb.2(0x40000000), %bb.1(0x40000000)
16881728 ; GREEDY: liveins: $edi, $xmm0, $xmm1
16891729 ; GREEDY: [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi
1690 ; GREEDY: [[COPY1:%[0-9]+]]:vecr(s32) = COPY $xmm0
1691 ; GREEDY: [[COPY2:%[0-9]+]]:vecr(s32) = COPY $xmm1
1730 ; GREEDY: [[COPY1:%[0-9]+]]:vecr(s128) = COPY $xmm0
1731 ; GREEDY: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY1]](s128)
1732 ; GREEDY: [[COPY2:%[0-9]+]]:vecr(s128) = COPY $xmm1
1733 ; GREEDY: [[TRUNC1:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY2]](s128)
16921734 ; GREEDY: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
16931735 ; GREEDY: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
1694 ; GREEDY: G_BRCOND [[ICMP]](s1), %bb.1
1695 ; GREEDY: G_BR %bb.2
1696 ; GREEDY: bb.1.cond.true:
1697 ; GREEDY: successors: %bb.3(0x80000000)
1698 ; GREEDY: G_BR %bb.3
1699 ; GREEDY: bb.2.cond.false:
1700 ; GREEDY: successors: %bb.3(0x80000000)
1701 ; GREEDY: bb.3.cond.end:
1702 ; GREEDY: [[PHI:%[0-9]+]]:vecr(s32) = G_PHI [[COPY1]](s32), %bb.1, [[COPY2]](s32), %bb.2
1703 ; GREEDY: $xmm0 = COPY [[PHI]](s32)
1736 ; GREEDY: G_BRCOND [[ICMP]](s1), %bb.2
1737 ; GREEDY: bb.1.cond.false:
1738 ; GREEDY: successors: %bb.2(0x80000000)
1739 ; GREEDY: bb.2.cond.end:
1740 ; GREEDY: [[PHI:%[0-9]+]]:vecr(s32) = G_PHI [[TRUNC1]](s32), %bb.1, [[TRUNC]](s32), %bb.0
1741 ; GREEDY: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[PHI]](s32)
1742 ; GREEDY: $xmm0 = COPY [[ANYEXT]](s128)
17041743 ; GREEDY: RET 0, implicit $xmm0
1705 bb.0.entry:
1706 successors: %bb.1(0x40000000), %bb.2(0x40000000)
1744 bb.1.entry:
1745 successors: %bb.3(0x40000000), %bb.2(0x40000000)
17071746 liveins: $edi, $xmm0, $xmm1
17081747
1709 %0(s32) = COPY $edi
1710 %1(s32) = COPY $xmm0
1711 %2(s32) = COPY $xmm1
1712 %3(s32) = G_CONSTANT i32 0
1713 %4(s1) = G_ICMP intpred(sgt), %0(s32), %3
1714 G_BRCOND %4(s1), %bb.1
1715 G_BR %bb.2
1716
1717 bb.1.cond.true:
1718 successors: %bb.3(0x80000000)
1719
1720 G_BR %bb.3
1748 %0:_(s32) = COPY $edi
1749 %3:_(s128) = COPY $xmm0
1750 %1:_(s32) = G_TRUNC %3(s128)
1751 %4:_(s128) = COPY $xmm1
1752 %2:_(s32) = G_TRUNC %4(s128)
1753 %5:_(s32) = G_CONSTANT i32 0
1754 %6:_(s1) = G_ICMP intpred(sgt), %0(s32), %5
1755 G_BRCOND %6(s1), %bb.3
17211756
17221757 bb.2.cond.false:
17231758 successors: %bb.3(0x80000000)
17241759
1760
17251761 bb.3.cond.end:
1726 %5(s32) = G_PHI %1(s32), %bb.1, %2(s32), %bb.2
1727 $xmm0 = COPY %5(s32)
1762 %7:_(s32) = G_PHI %2(s32), %bb.2, %1(s32), %bb.1
1763 %8:_(s128) = G_ANYEXT %7(s32)
1764 $xmm0 = COPY %8(s128)
17281765 RET 0, implicit $xmm0
17291766
17301767 ...
17411778 liveins: $xmm0
17421779
17431780 ; FAST-LABEL: name: test_fpext
1744 ; FAST: [[COPY:%[0-9]+]]:vecr(s32) = COPY $xmm0
1745 ; FAST: [[FPEXT:%[0-9]+]]:vecr(s64) = G_FPEXT [[COPY]](s32)
1746 ; FAST: $xmm0 = COPY [[FPEXT]](s64)
1781 ; FAST: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
1782 ; FAST: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128)
1783 ; FAST: [[FPEXT:%[0-9]+]]:vecr(s64) = G_FPEXT [[TRUNC]](s32)
1784 ; FAST: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[FPEXT]](s64)
1785 ; FAST: $xmm0 = COPY [[ANYEXT]](s128)
17471786 ; FAST: RET 0, implicit $xmm0
17481787 ; GREEDY-LABEL: name: test_fpext
1749 ; GREEDY: [[COPY:%[0-9]+]]:vecr(s32) = COPY $xmm0
1750 ; GREEDY: [[FPEXT:%[0-9]+]]:vecr(s64) = G_FPEXT [[COPY]](s32)
1751 ; GREEDY: $xmm0 = COPY [[FPEXT]](s64)
1788 ; GREEDY: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
1789 ; GREEDY: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128)
1790 ; GREEDY: [[FPEXT:%[0-9]+]]:vecr(s64) = G_FPEXT [[TRUNC]](s32)
1791 ; GREEDY: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[FPEXT]](s64)
1792 ; GREEDY: $xmm0 = COPY [[ANYEXT]](s128)
17521793 ; GREEDY: RET 0, implicit $xmm0
1753 %0(s32) = COPY $xmm0
1754 %1(s64) = G_FPEXT %0(s32)
1755 $xmm0 = COPY %1(s64)
1794 %1:_(s128) = COPY $xmm0
1795 %0:_(s32) = G_TRUNC %1(s128)
1796 %2:_(s64) = G_FPEXT %0(s32)
1797 %3:_(s128) = G_ANYEXT %2(s64)
1798 $xmm0 = COPY %3(s128)
17561799 RET 0, implicit $xmm0
17571800
17581801 ...
2525 - { id: 0, class: vecr, preferred-register: '' }
2626 - { id: 1, class: vecr, preferred-register: '' }
2727 - { id: 2, class: vecr, preferred-register: '' }
28 - { id: 3, class: vecr, preferred-register: '' }
29 - { id: 4, class: vecr, preferred-register: '' }
30 - { id: 5, class: vecr, preferred-register: '' }
2831 liveins:
2932 fixedStack:
3033 stack:
3639 liveins: $xmm0, $xmm1
3740
3841 ; SSE-LABEL: name: test_fadd_float
39 ; SSE: [[COPY:%[0-9]+]]:fr32 = COPY $xmm0
40 ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY $xmm1
41 ; SSE: [[ADDSSrr:%[0-9]+]]:fr32 = ADDSSrr [[COPY]], [[COPY1]]
42 ; SSE: $xmm0 = COPY [[ADDSSrr]]
42 ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
43 ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
44 ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
45 ; SSE: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
46 ; SSE: [[ADDSSrr:%[0-9]+]]:fr32 = ADDSSrr [[COPY1]], [[COPY3]]
47 ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY [[ADDSSrr]]
48 ; SSE: $xmm0 = COPY [[COPY4]]
4349 ; SSE: RET 0, implicit $xmm0
4450 ; AVX-LABEL: name: test_fadd_float
45 ; AVX: [[COPY:%[0-9]+]]:fr32 = COPY $xmm0
46 ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY $xmm1
47 ; AVX: [[VADDSSrr:%[0-9]+]]:fr32 = VADDSSrr [[COPY]], [[COPY1]]
48 ; AVX: $xmm0 = COPY [[VADDSSrr]]
51 ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
52 ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
53 ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
54 ; AVX: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
55 ; AVX: [[VADDSSrr:%[0-9]+]]:fr32 = VADDSSrr [[COPY1]], [[COPY3]]
56 ; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY [[VADDSSrr]]
57 ; AVX: $xmm0 = COPY [[COPY4]]
4958 ; AVX: RET 0, implicit $xmm0
5059 ; AVX512F-LABEL: name: test_fadd_float
51 ; AVX512F: [[COPY:%[0-9]+]]:fr32x = COPY $xmm0
52 ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY $xmm1
53 ; AVX512F: [[VADDSSZrr:%[0-9]+]]:fr32x = VADDSSZrr [[COPY]], [[COPY1]]
54 ; AVX512F: $xmm0 = COPY [[VADDSSZrr]]
60 ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
61 ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
62 ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
63 ; AVX512F: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]]
64 ; AVX512F: [[VADDSSZrr:%[0-9]+]]:fr32x = VADDSSZrr [[COPY1]], [[COPY3]]
65 ; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY [[VADDSSZrr]]
66 ; AVX512F: $xmm0 = COPY [[COPY4]]
5567 ; AVX512F: RET 0, implicit $xmm0
5668 ; AVX512VL-LABEL: name: test_fadd_float
57 ; AVX512VL: [[COPY:%[0-9]+]]:fr32x = COPY $xmm0
58 ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY $xmm1
59 ; AVX512VL: [[VADDSSZrr:%[0-9]+]]:fr32x = VADDSSZrr [[COPY]], [[COPY1]]
60 ; AVX512VL: $xmm0 = COPY [[VADDSSZrr]]
69 ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
70 ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
71 ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
72 ; AVX512VL: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]]
73 ; AVX512VL: [[VADDSSZrr:%[0-9]+]]:fr32x = VADDSSZrr [[COPY1]], [[COPY3]]
74 ; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY [[VADDSSZrr]]
75 ; AVX512VL: $xmm0 = COPY [[COPY4]]
6176 ; AVX512VL: RET 0, implicit $xmm0
62 %0(s32) = COPY $xmm0
63 %1(s32) = COPY $xmm1
64 %2(s32) = G_FADD %0, %1
65 $xmm0 = COPY %2(s32)
77 %2:vecr(s128) = COPY $xmm0
78 %0:vecr(s32) = G_TRUNC %2(s128)
79 %3:vecr(s128) = COPY $xmm1
80 %1:vecr(s32) = G_TRUNC %3(s128)
81 %4:vecr(s32) = G_FADD %0, %1
82 %5:vecr(s128) = G_ANYEXT %4(s32)
83 $xmm0 = COPY %5(s128)
6684 RET 0, implicit $xmm0
6785
6886 ...
7694 - { id: 0, class: vecr, preferred-register: '' }
7795 - { id: 1, class: vecr, preferred-register: '' }
7896 - { id: 2, class: vecr, preferred-register: '' }
97 - { id: 3, class: vecr, preferred-register: '' }
98 - { id: 4, class: vecr, preferred-register: '' }
99 - { id: 5, class: vecr, preferred-register: '' }
79100 liveins:
80101 fixedStack:
81102 stack:
87108 liveins: $xmm0, $xmm1
88109
89110 ; SSE-LABEL: name: test_fadd_double
90 ; SSE: [[COPY:%[0-9]+]]:fr64 = COPY $xmm0
91 ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY $xmm1
92 ; SSE: [[ADDSDrr:%[0-9]+]]:fr64 = ADDSDrr [[COPY]], [[COPY1]]
93 ; SSE: $xmm0 = COPY [[ADDSDrr]]
111 ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
112 ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
113 ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
114 ; SSE: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
115 ; SSE: [[ADDSDrr:%[0-9]+]]:fr64 = ADDSDrr [[COPY1]], [[COPY3]]
116 ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY [[ADDSDrr]]
117 ; SSE: $xmm0 = COPY [[COPY4]]
94118 ; SSE: RET 0, implicit $xmm0
95119 ; AVX-LABEL: name: test_fadd_double
96 ; AVX: [[COPY:%[0-9]+]]:fr64 = COPY $xmm0
97 ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY $xmm1
98 ; AVX: [[VADDSDrr:%[0-9]+]]:fr64 = VADDSDrr [[COPY]], [[COPY1]]
99 ; AVX: $xmm0 = COPY [[VADDSDrr]]
120 ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
121 ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
122 ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
123 ; AVX: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
124 ; AVX: [[VADDSDrr:%[0-9]+]]:fr64 = VADDSDrr [[COPY1]], [[COPY3]]
125 ; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY [[VADDSDrr]]
126 ; AVX: $xmm0 = COPY [[COPY4]]
100127 ; AVX: RET 0, implicit $xmm0
101128 ; AVX512F-LABEL: name: test_fadd_double
102 ; AVX512F: [[COPY:%[0-9]+]]:fr64x = COPY $xmm0
103 ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY $xmm1
104 ; AVX512F: [[VADDSDZrr:%[0-9]+]]:fr64x = VADDSDZrr [[COPY]], [[COPY1]]
105 ; AVX512F: $xmm0 = COPY [[VADDSDZrr]]
129 ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
130 ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
131 ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
132 ; AVX512F: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]]
133 ; AVX512F: [[VADDSDZrr:%[0-9]+]]:fr64x = VADDSDZrr [[COPY1]], [[COPY3]]
134 ; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY [[VADDSDZrr]]
135 ; AVX512F: $xmm0 = COPY [[COPY4]]
106136 ; AVX512F: RET 0, implicit $xmm0
107137 ; AVX512VL-LABEL: name: test_fadd_double
108 ; AVX512VL: [[COPY:%[0-9]+]]:fr64x = COPY $xmm0
109 ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY $xmm1
110 ; AVX512VL: [[VADDSDZrr:%[0-9]+]]:fr64x = VADDSDZrr [[COPY]], [[COPY1]]
111 ; AVX512VL: $xmm0 = COPY [[VADDSDZrr]]
138 ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
139 ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
140 ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
141 ; AVX512VL: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]]
142 ; AVX512VL: [[VADDSDZrr:%[0-9]+]]:fr64x = VADDSDZrr [[COPY1]], [[COPY3]]
143 ; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY [[VADDSDZrr]]
144 ; AVX512VL: $xmm0 = COPY [[COPY4]]
112145 ; AVX512VL: RET 0, implicit $xmm0
113 %0(s64) = COPY $xmm0
114 %1(s64) = COPY $xmm1
115 %2(s64) = G_FADD %0, %1
116 $xmm0 = COPY %2(s64)
146 %2:vecr(s128) = COPY $xmm0
147 %0:vecr(s64) = G_TRUNC %2(s128)
148 %3:vecr(s128) = COPY $xmm1
149 %1:vecr(s64) = G_TRUNC %3(s128)
150 %4:vecr(s64) = G_FADD %0, %1
151 %5:vecr(s128) = G_ANYEXT %4(s64)
152 $xmm0 = COPY %5(s128)
117153 RET 0, implicit $xmm0
118154
119155 ...
2929 bb.1.entry:
3030 ; CHECK_NOPIC64-LABEL: name: test_float
3131 ; CHECK_NOPIC64: [[MOVSSrm:%[0-9]+]]:fr32 = MOVSSrm $rip, 1, $noreg, %const.0, $noreg
32 ; CHECK_NOPIC64: $xmm0 = COPY [[MOVSSrm]]
32 ; CHECK_NOPIC64: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSSrm]]
33 ; CHECK_NOPIC64: $xmm0 = COPY [[COPY]]
3334 ; CHECK_NOPIC64: RET 0, implicit $xmm0
3435 ; CHECK_LARGE64-LABEL: name: test_float
3536 ; CHECK_LARGE64: [[MOV64ri:%[0-9]+]]:gr64 = MOV64ri %const.0
3637 ; CHECK_LARGE64: [[MOVSSrm:%[0-9]+]]:fr32 = MOVSSrm [[MOV64ri]], 1, $noreg, 0, $noreg :: (load 8 from constant-pool, align 32)
37 ; CHECK_LARGE64: $xmm0 = COPY [[MOVSSrm]]
38 ; CHECK_LARGE64: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSSrm]]
39 ; CHECK_LARGE64: $xmm0 = COPY [[COPY]]
3840 ; CHECK_LARGE64: RET 0, implicit $xmm0
3941 ; CHECK_SMALL32-LABEL: name: test_float
4042 ; CHECK_SMALL32: [[MOVSSrm:%[0-9]+]]:fr32 = MOVSSrm $noreg, 1, $noreg, %const.0, $noreg
41 ; CHECK_SMALL32: $xmm0 = COPY [[MOVSSrm]]
43 ; CHECK_SMALL32: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSSrm]]
44 ; CHECK_SMALL32: $xmm0 = COPY [[COPY]]
4245 ; CHECK_SMALL32: RET 0, implicit $xmm0
4346 ; CHECK_LARGE32-LABEL: name: test_float
4447 ; CHECK_LARGE32: [[MOVSSrm:%[0-9]+]]:fr32 = MOVSSrm $noreg, 1, $noreg, %const.0, $noreg
45 ; CHECK_LARGE32: $xmm0 = COPY [[MOVSSrm]]
48 ; CHECK_LARGE32: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSSrm]]
49 ; CHECK_LARGE32: $xmm0 = COPY [[COPY]]
4650 ; CHECK_LARGE32: RET 0, implicit $xmm0
4751 ; CHECK_PIC64-LABEL: name: test_float
4852 ; CHECK_PIC64: [[MOVSSrm:%[0-9]+]]:fr32 = MOVSSrm $rip, 1, $noreg, %const.0, $noreg
49 ; CHECK_PIC64: $xmm0 = COPY [[MOVSSrm]]
53 ; CHECK_PIC64: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSSrm]]
54 ; CHECK_PIC64: $xmm0 = COPY [[COPY]]
5055 ; CHECK_PIC64: RET 0, implicit $xmm0
51 %0(s32) = G_FCONSTANT float 5.500000e+00
52 $xmm0 = COPY %0(s32)
56 %0:vecr(s32) = G_FCONSTANT float 5.500000e+00
57 %1:vecr(s128) = G_ANYEXT %0(s32)
58 $xmm0 = COPY %1(s128)
5359 RET 0, implicit $xmm0
5460
5561 ...
7076 bb.1.entry:
7177 ; CHECK_NOPIC64-LABEL: name: test_double
7278 ; CHECK_NOPIC64: [[MOVSDrm:%[0-9]+]]:fr64 = MOVSDrm $rip, 1, $noreg, %const.0, $noreg
73 ; CHECK_NOPIC64: $xmm0 = COPY [[MOVSDrm]]
79 ; CHECK_NOPIC64: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSDrm]]
80 ; CHECK_NOPIC64: $xmm0 = COPY [[COPY]]
7481 ; CHECK_NOPIC64: RET 0, implicit $xmm0
7582 ; CHECK_LARGE64-LABEL: name: test_double
7683 ; CHECK_LARGE64: [[MOV64ri:%[0-9]+]]:gr64 = MOV64ri %const.0
7784 ; CHECK_LARGE64: [[MOVSDrm:%[0-9]+]]:fr64 = MOVSDrm [[MOV64ri]], 1, $noreg, 0, $noreg :: (load 8 from constant-pool, align 64)
78 ; CHECK_LARGE64: $xmm0 = COPY [[MOVSDrm]]
85 ; CHECK_LARGE64: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSDrm]]
86 ; CHECK_LARGE64: $xmm0 = COPY [[COPY]]
7987 ; CHECK_LARGE64: RET 0, implicit $xmm0
8088 ; CHECK_SMALL32-LABEL: name: test_double
8189 ; CHECK_SMALL32: [[MOVSDrm:%[0-9]+]]:fr64 = MOVSDrm $noreg, 1, $noreg, %const.0, $noreg
82 ; CHECK_SMALL32: $xmm0 = COPY [[MOVSDrm]]
90 ; CHECK_SMALL32: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSDrm]]
91 ; CHECK_SMALL32: $xmm0 = COPY [[COPY]]
8392 ; CHECK_SMALL32: RET 0, implicit $xmm0
8493 ; CHECK_LARGE32-LABEL: name: test_double
8594 ; CHECK_LARGE32: [[MOVSDrm:%[0-9]+]]:fr64 = MOVSDrm $noreg, 1, $noreg, %const.0, $noreg
86 ; CHECK_LARGE32: $xmm0 = COPY [[MOVSDrm]]
95 ; CHECK_LARGE32: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSDrm]]
96 ; CHECK_LARGE32: $xmm0 = COPY [[COPY]]
8797 ; CHECK_LARGE32: RET 0, implicit $xmm0
8898 ; CHECK_PIC64-LABEL: name: test_double
8999 ; CHECK_PIC64: [[MOVSDrm:%[0-9]+]]:fr64 = MOVSDrm $rip, 1, $noreg, %const.0, $noreg
90 ; CHECK_PIC64: $xmm0 = COPY [[MOVSDrm]]
100 ; CHECK_PIC64: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSDrm]]
101 ; CHECK_PIC64: $xmm0 = COPY [[COPY]]
91102 ; CHECK_PIC64: RET 0, implicit $xmm0
92 %0(s64) = G_FCONSTANT double 5.500000e+00
93 $xmm0 = COPY %0(s64)
103 %0:vecr(s64) = G_FCONSTANT double 5.500000e+00
104 %1:vecr(s128) = G_ANYEXT %0(s64)
105 $xmm0 = COPY %1(s128)
94106 RET 0, implicit $xmm0
95107
96108 ...
2525 - { id: 0, class: vecr, preferred-register: '' }
2626 - { id: 1, class: vecr, preferred-register: '' }
2727 - { id: 2, class: vecr, preferred-register: '' }
28 - { id: 3, class: vecr, preferred-register: '' }
29 - { id: 4, class: vecr, preferred-register: '' }
30 - { id: 5, class: vecr, preferred-register: '' }
2831 liveins:
2932 fixedStack:
3033 stack:
3639 liveins: $xmm0, $xmm1
3740
3841 ; SSE-LABEL: name: test_fdiv_float
39 ; SSE: [[COPY:%[0-9]+]]:fr32 = COPY $xmm0
40 ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY $xmm1
41 ; SSE: [[DIVSSrr:%[0-9]+]]:fr32 = DIVSSrr [[COPY]], [[COPY1]]
42 ; SSE: $xmm0 = COPY [[DIVSSrr]]
42 ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
43 ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
44 ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
45 ; SSE: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
46 ; SSE: [[DIVSSrr:%[0-9]+]]:fr32 = DIVSSrr [[COPY1]], [[COPY3]]
47 ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY [[DIVSSrr]]
48 ; SSE: $xmm0 = COPY [[COPY4]]
4349 ; SSE: RET 0, implicit $xmm0
4450 ; AVX-LABEL: name: test_fdiv_float
45 ; AVX: [[COPY:%[0-9]+]]:fr32 = COPY $xmm0
46 ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY $xmm1
47 ; AVX: [[VDIVSSrr:%[0-9]+]]:fr32 = VDIVSSrr [[COPY]], [[COPY1]]
48 ; AVX: $xmm0 = COPY [[VDIVSSrr]]
51 ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
52 ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
53 ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
54 ; AVX: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
55 ; AVX: [[VDIVSSrr:%[0-9]+]]:fr32 = VDIVSSrr [[COPY1]], [[COPY3]]
56 ; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY [[VDIVSSrr]]
57 ; AVX: $xmm0 = COPY [[COPY4]]
4958 ; AVX: RET 0, implicit $xmm0
5059 ; AVX512F-LABEL: name: test_fdiv_float
51 ; AVX512F: [[COPY:%[0-9]+]]:fr32x = COPY $xmm0
52 ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY $xmm1
53 ; AVX512F: [[VDIVSSZrr:%[0-9]+]]:fr32x = VDIVSSZrr [[COPY]], [[COPY1]]
54 ; AVX512F: $xmm0 = COPY [[VDIVSSZrr]]
60 ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
61 ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
62 ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
63 ; AVX512F: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]]
64 ; AVX512F: [[VDIVSSZrr:%[0-9]+]]:fr32x = VDIVSSZrr [[COPY1]], [[COPY3]]
65 ; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY [[VDIVSSZrr]]
66 ; AVX512F: $xmm0 = COPY [[COPY4]]
5567 ; AVX512F: RET 0, implicit $xmm0
5668 ; AVX512VL-LABEL: name: test_fdiv_float
57 ; AVX512VL: [[COPY:%[0-9]+]]:fr32x = COPY $xmm0
58 ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY $xmm1
59 ; AVX512VL: [[VDIVSSZrr:%[0-9]+]]:fr32x = VDIVSSZrr [[COPY]], [[COPY1]]
60 ; AVX512VL: $xmm0 = COPY [[VDIVSSZrr]]
69 ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
70 ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
71 ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
72 ; AVX512VL: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]]
73 ; AVX512VL: [[VDIVSSZrr:%[0-9]+]]:fr32x = VDIVSSZrr [[COPY1]], [[COPY3]]
74 ; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY [[VDIVSSZrr]]
75 ; AVX512VL: $xmm0 = COPY [[COPY4]]
6176 ; AVX512VL: RET 0, implicit $xmm0
62 %0(s32) = COPY $xmm0
63 %1(s32) = COPY $xmm1
64 %2(s32) = G_FDIV %0, %1
65 $xmm0 = COPY %2(s32)
77 %2:vecr(s128) = COPY $xmm0
78 %0:vecr(s32) = G_TRUNC %2(s128)
79 %3:vecr(s128) = COPY $xmm1
80 %1:vecr(s32) = G_TRUNC %3(s128)
81 %4:vecr(s32) = G_FDIV %0, %1
82 %5:vecr(s128) = G_ANYEXT %4(s32)
83 $xmm0 = COPY %5(s128)
6684 RET 0, implicit $xmm0
6785
6886 ...
7694 - { id: 0, class: vecr, preferred-register: '' }
7795 - { id: 1, class: vecr, preferred-register: '' }
7896 - { id: 2, class: vecr, preferred-register: '' }
97 - { id: 3, class: vecr, preferred-register: '' }
98 - { id: 4, class: vecr, preferred-register: '' }
99 - { id: 5, class: vecr, preferred-register: '' }
79100 liveins:
80101 fixedStack:
81102 stack:
87108 liveins: $xmm0, $xmm1
88109
89110 ; SSE-LABEL: name: test_fdiv_double
90 ; SSE: [[COPY:%[0-9]+]]:fr64 = COPY $xmm0
91 ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY $xmm1
92 ; SSE: [[DIVSDrr:%[0-9]+]]:fr64 = DIVSDrr [[COPY]], [[COPY1]]
93 ; SSE: $xmm0 = COPY [[DIVSDrr]]
111 ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
112 ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
113 ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
114 ; SSE: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
115 ; SSE: [[DIVSDrr:%[0-9]+]]:fr64 = DIVSDrr [[COPY1]], [[COPY3]]
116 ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY [[DIVSDrr]]
117 ; SSE: $xmm0 = COPY [[COPY4]]
94118 ; SSE: RET 0, implicit $xmm0
95119 ; AVX-LABEL: name: test_fdiv_double
96 ; AVX: [[COPY:%[0-9]+]]:fr64 = COPY $xmm0
97 ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY $xmm1
98 ; AVX: [[VDIVSDrr:%[0-9]+]]:fr64 = VDIVSDrr [[COPY]], [[COPY1]]
99 ; AVX: $xmm0 = COPY [[VDIVSDrr]]
120 ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
121 ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
122 ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
123 ; AVX: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
124 ; AVX: [[VDIVSDrr:%[0-9]+]]:fr64 = VDIVSDrr [[COPY1]], [[COPY3]]
125 ; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY [[VDIVSDrr]]
126 ; AVX: $xmm0 = COPY [[COPY4]]
100127 ; AVX: RET 0, implicit $xmm0
101128 ; AVX512F-LABEL: name: test_fdiv_double
102 ; AVX512F: [[COPY:%[0-9]+]]:fr64x = COPY $xmm0
103 ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY $xmm1
104 ; AVX512F: [[VDIVSDZrr:%[0-9]+]]:fr64x = VDIVSDZrr [[COPY]], [[COPY1]]
105 ; AVX512F: $xmm0 = COPY [[VDIVSDZrr]]
129 ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
130 ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
131 ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
132 ; AVX512F: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]]
133 ; AVX512F: [[VDIVSDZrr:%[0-9]+]]:fr64x = VDIVSDZrr [[COPY1]], [[COPY3]]
134 ; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY [[VDIVSDZrr]]
135 ; AVX512F: $xmm0 = COPY [[COPY4]]
106136 ; AVX512F: RET 0, implicit $xmm0
107137 ; AVX512VL-LABEL: name: test_fdiv_double
108 ; AVX512VL: [[COPY:%[0-9]+]]:fr64x = COPY $xmm0
109 ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY $xmm1
110 ; AVX512VL: [[VDIVSDZrr:%[0-9]+]]:fr64x = VDIVSDZrr [[COPY]], [[COPY1]]
111 ; AVX512VL: $xmm0 = COPY [[VDIVSDZrr]]
138 ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
139 ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
140 ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
141 ; AVX512VL: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]]
142 ; AVX512VL: [[VDIVSDZrr:%[0-9]+]]:fr64x = VDIVSDZrr [[COPY1]], [[COPY3]]
143 ; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY [[VDIVSDZrr]]
144 ; AVX512VL: $xmm0 = COPY [[COPY4]]
112145 ; AVX512VL: RET 0, implicit $xmm0
113 %0(s64) = COPY $xmm0
114 %1(s64) = COPY $xmm1
115 %2(s64) = G_FDIV %0, %1
116 $xmm0 = COPY %2(s64)
146 %2:vecr(s128) = COPY $xmm0
147 %0:vecr(s64) = G_TRUNC %2(s128)
148 %3:vecr(s128) = COPY $xmm1
149 %1:vecr(s64) = G_TRUNC %3(s128)
150 %4:vecr(s64) = G_FDIV %0, %1
151 %5:vecr(s128) = G_ANYEXT %4(s64)
152 $xmm0 = COPY %5(s128)
117153 RET 0, implicit $xmm0
118154
119155 ...
2525 - { id: 0, class: vecr, preferred-register: '' }
2626 - { id: 1, class: vecr, preferred-register: '' }
2727 - { id: 2, class: vecr, preferred-register: '' }
28 - { id: 3, class: vecr, preferred-register: '' }
29 - { id: 4, class: vecr, preferred-register: '' }
30 - { id: 5, class: vecr, preferred-register: '' }
2831 liveins:
2932 fixedStack:
3033 stack:
3639 liveins: $xmm0, $xmm1
3740
3841 ; SSE-LABEL: name: test_fmul_float
39 ; SSE: [[COPY:%[0-9]+]]:fr32 = COPY $xmm0
40 ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY $xmm1
41 ; SSE: [[MULSSrr:%[0-9]+]]:fr32 = MULSSrr [[COPY]], [[COPY1]]
42 ; SSE: $xmm0 = COPY [[MULSSrr]]
42 ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
43 ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
44 ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
45 ; SSE: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
46 ; SSE: [[MULSSrr:%[0-9]+]]:fr32 = MULSSrr [[COPY1]], [[COPY3]]
47 ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY [[MULSSrr]]
48 ; SSE: $xmm0 = COPY [[COPY4]]
4349 ; SSE: RET 0, implicit $xmm0
4450 ; AVX-LABEL: name: test_fmul_float
45 ; AVX: [[COPY:%[0-9]+]]:fr32 = COPY $xmm0
46 ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY $xmm1
47 ; AVX: [[VMULSSrr:%[0-9]+]]:fr32 = VMULSSrr [[COPY]], [[COPY1]]
48 ; AVX: $xmm0 = COPY [[VMULSSrr]]
51 ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
52 ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
53 ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
54 ; AVX: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
55 ; AVX: [[VMULSSrr:%[0-9]+]]:fr32 = VMULSSrr [[COPY1]], [[COPY3]]
56 ; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY [[VMULSSrr]]
57 ; AVX: $xmm0 = COPY [[COPY4]]
4958 ; AVX: RET 0, implicit $xmm0
5059 ; AVX512F-LABEL: name: test_fmul_float
51 ; AVX512F: [[COPY:%[0-9]+]]:fr32x = COPY $xmm0
52 ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY $xmm1
53 ; AVX512F: [[VMULSSZrr:%[0-9]+]]:fr32x = VMULSSZrr [[COPY]], [[COPY1]]
54 ; AVX512F: $xmm0 = COPY [[VMULSSZrr]]
60 ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
61 ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
62 ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
63 ; AVX512F: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]]
64 ; AVX512F: [[VMULSSZrr:%[0-9]+]]:fr32x = VMULSSZrr [[COPY1]], [[COPY3]]
65 ; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY [[VMULSSZrr]]
66 ; AVX512F: $xmm0 = COPY [[COPY4]]
5567 ; AVX512F: RET 0, implicit $xmm0
5668 ; AVX512VL-LABEL: name: test_fmul_float
57 ; AVX512VL: [[COPY:%[0-9]+]]:fr32x = COPY $xmm0
58 ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY $xmm1
59 ; AVX512VL: [[VMULSSZrr:%[0-9]+]]:fr32x = VMULSSZrr [[COPY]], [[COPY1]]
60 ; AVX512VL: $xmm0 = COPY [[VMULSSZrr]]
69 ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
70 ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
71 ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
72 ; AVX512VL: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]]
73 ; AVX512VL: [[VMULSSZrr:%[0-9]+]]:fr32x = VMULSSZrr [[COPY1]], [[COPY3]]
74 ; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY [[VMULSSZrr]]
75 ; AVX512VL: $xmm0 = COPY [[COPY4]]
6176 ; AVX512VL: RET 0, implicit $xmm0
62 %0(s32) = COPY $xmm0
63 %1(s32) = COPY $xmm1
64 %2(s32) = G_FMUL %0, %1
65 $xmm0 = COPY %2(s32)
77 %2:vecr(s128) = COPY $xmm0
78 %0:vecr(s32) = G_TRUNC %2(s128)
79 %3:vecr(s128) = COPY $xmm1
80 %1:vecr(s32) = G_TRUNC %3(s128)
81 %4:vecr(s32) = G_FMUL %0, %1
82 %5:vecr(s128) = G_ANYEXT %4(s32)
83 $xmm0 = COPY %5(s128)
6684 RET 0, implicit $xmm0
6785
6886 ...
7694 - { id: 0, class: vecr, preferred-register: '' }
7795 - { id: 1, class: vecr, preferred-register: '' }
7896 - { id: 2, class: vecr, preferred-register: '' }
97 - { id: 3, class: vecr, preferred-register: '' }
98 - { id: 4, class: vecr, preferred-register: '' }
99 - { id: 5, class: vecr, preferred-register: '' }
79100 liveins:
80101 fixedStack:
81102 stack:
87108 liveins: $xmm0, $xmm1
88109
89110 ; SSE-LABEL: name: test_fmul_double
90 ; SSE: [[COPY:%[0-9]+]]:fr64 = COPY $xmm0
91 ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY $xmm1
92 ; SSE: [[MULSDrr:%[0-9]+]]:fr64 = MULSDrr [[COPY]], [[COPY1]]
93 ; SSE: $xmm0 = COPY [[MULSDrr]]
111 ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
112 ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
113 ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
114 ; SSE: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
115 ; SSE: [[MULSDrr:%[0-9]+]]:fr64 = MULSDrr [[COPY1]], [[COPY3]]
116 ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY [[MULSDrr]]
117 ; SSE: $xmm0 = COPY [[COPY4]]
94118 ; SSE: RET 0, implicit $xmm0
95119 ; AVX-LABEL: name: test_fmul_double
96 ; AVX: [[COPY:%[0-9]+]]:fr64 = COPY $xmm0
97 ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY $xmm1
98 ; AVX: [[VMULSDrr:%[0-9]+]]:fr64 = VMULSDrr [[COPY]], [[COPY1]]
99 ; AVX: $xmm0 = COPY [[VMULSDrr]]
120 ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
121 ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
122 ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
123 ; AVX: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
124 ; AVX: [[VMULSDrr:%[0-9]+]]:fr64 = VMULSDrr [[COPY1]], [[COPY3]]
125 ; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY [[VMULSDrr]]
126 ; AVX: $xmm0 = COPY [[COPY4]]
100127 ; AVX: RET 0, implicit $xmm0
101128 ; AVX512F-LABEL: name: test_fmul_double
102 ; AVX512F: [[COPY:%[0-9]+]]:fr64x = COPY $xmm0
103 ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY $xmm1
104 ; AVX512F: [[VMULSDZrr:%[0-9]+]]:fr64x = VMULSDZrr [[COPY]], [[COPY1]]
105 ; AVX512F: $xmm0 = COPY [[VMULSDZrr]]
129 ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
130 ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
131 ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
132 ; AVX512F: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]]
133 ; AVX512F: [[VMULSDZrr:%[0-9]+]]:fr64x = VMULSDZrr [[COPY1]], [[COPY3]]
134 ; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY [[VMULSDZrr]]
135 ; AVX512F: $xmm0 = COPY [[COPY4]]
106136 ; AVX512F: RET 0, implicit $xmm0
107137 ; AVX512VL-LABEL: name: test_fmul_double
108 ; AVX512VL: [[COPY:%[0-9]+]]:fr64x = COPY $xmm0
109 ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY $xmm1
110 ; AVX512VL: [[VMULSDZrr:%[0-9]+]]:fr64x = VMULSDZrr [[COPY]], [[COPY1]]
111 ; AVX512VL: $xmm0 = COPY [[VMULSDZrr]]
138 ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
139 ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
140 ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
141 ; AVX512VL: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]]
142 ; AVX512VL: [[VMULSDZrr:%[0-9]+]]:fr64x = VMULSDZrr [[COPY1]], [[COPY3]]
143 ; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY [[VMULSDZrr]]
144 ; AVX512VL: $xmm0 = COPY [[COPY4]]
112145 ; AVX512VL: RET 0, implicit $xmm0
113 %0(s64) = COPY $xmm0
114 %1(s64) = COPY $xmm1
115 %2(s64) = G_FMUL %0, %1
116 $xmm0 = COPY %2(s64)
146 %2:vecr(s128) = COPY $xmm0
147 %0:vecr(s64) = G_TRUNC %2(s128)
148 %3:vecr(s128) = COPY $xmm1
149 %1:vecr(s64) = G_TRUNC %3(s128)
150 %4:vecr(s64) = G_FMUL %0, %1
151 %5:vecr(s128) = G_ANYEXT %4(s64)
152 $xmm0 = COPY %5(s128)
117153 RET 0, implicit $xmm0
118154
119155 ...
1616 registers:
1717 - { id: 0, class: vecr, preferred-register: '' }
1818 - { id: 1, class: vecr, preferred-register: '' }
19 - { id: 2, class: vecr, preferred-register: '' }
20 - { id: 3, class: vecr, preferred-register: '' }
1921 liveins:
2022 fixedStack:
2123 stack:
2527 liveins: $xmm0
2628
2729 ; ALL-LABEL: name: test
28 ; ALL: [[COPY:%[0-9]+]]:fr32 = COPY $xmm0
29 ; ALL: [[CVTSS2SDrr:%[0-9]+]]:fr64 = CVTSS2SDrr [[COPY]]
30 ; ALL: $xmm0 = COPY [[CVTSS2SDrr]]
30 ; ALL: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
31 ; ALL: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
32 ; ALL: [[CVTSS2SDrr:%[0-9]+]]:fr64 = CVTSS2SDrr [[COPY1]]
33 ; ALL: [[COPY2:%[0-9]+]]:vr128 = COPY [[CVTSS2SDrr]]
34 ; ALL: $xmm0 = COPY [[COPY2]]
3135 ; ALL: RET 0, implicit $xmm0
32 %0(s32) = COPY $xmm0
33 %1(s64) = G_FPEXT %0(s32)
34 $xmm0 = COPY %1(s64)
36 %1:vecr(s128) = COPY $xmm0
37 %0:vecr(s32) = G_TRUNC %1(s128)
38 %2:vecr(s64) = G_FPEXT %0(s32)
39 %3:vecr(s128) = G_ANYEXT %2(s64)
40 $xmm0 = COPY %3(s128)
3541 RET 0, implicit $xmm0
3642
3743 ...
2525 - { id: 0, class: vecr, preferred-register: '' }
2626 - { id: 1, class: vecr, preferred-register: '' }
2727 - { id: 2, class: vecr, preferred-register: '' }
28 - { id: 3, class: vecr, preferred-register: '' }
29 - { id: 4, class: vecr, preferred-register: '' }
30 - { id: 5, class: vecr, preferred-register: '' }
2831 liveins:
2932 fixedStack:
3033 stack:
3639 liveins: $xmm0, $xmm1
3740
3841 ; SSE-LABEL: name: test_fsub_float
39 ; SSE: [[COPY:%[0-9]+]]:fr32 = COPY $xmm0
40 ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY $xmm1
41 ; SSE: [[SUBSSrr:%[0-9]+]]:fr32 = SUBSSrr [[COPY]], [[COPY1]]
42 ; SSE: $xmm0 = COPY [[SUBSSrr]]
42 ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
43 ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
44 ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
45 ; SSE: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
46 ; SSE: [[SUBSSrr:%[0-9]+]]:fr32 = SUBSSrr [[COPY1]], [[COPY3]]
47 ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY [[SUBSSrr]]
48 ; SSE: $xmm0 = COPY [[COPY4]]
4349 ; SSE: RET 0, implicit $xmm0
4450 ; AVX-LABEL: name: test_fsub_float
45 ; AVX: [[COPY:%[0-9]+]]:fr32 = COPY $xmm0
46 ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY $xmm1
47 ; AVX: [[VSUBSSrr:%[0-9]+]]:fr32 = VSUBSSrr [[COPY]], [[COPY1]]
48 ; AVX: $xmm0 = COPY [[VSUBSSrr]]
51 ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
52 ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
53 ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
54 ; AVX: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
55 ; AVX: [[VSUBSSrr:%[0-9]+]]:fr32 = VSUBSSrr [[COPY1]], [[COPY3]]
56 ; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY [[VSUBSSrr]]
57 ; AVX: $xmm0 = COPY [[COPY4]]
4958 ; AVX: RET 0, implicit $xmm0
5059 ; AVX512F-LABEL: name: test_fsub_float
51 ; AVX512F: [[COPY:%[0-9]+]]:fr32x = COPY $xmm0
52 ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY $xmm1
53 ; AVX512F: [[VSUBSSZrr:%[0-9]+]]:fr32x = VSUBSSZrr [[COPY]], [[COPY1]]
54 ; AVX512F: $xmm0 = COPY [[VSUBSSZrr]]
60 ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
61 ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
62 ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
63 ; AVX512F: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]]
64 ; AVX512F: [[VSUBSSZrr:%[0-9]+]]:fr32x = VSUBSSZrr [[COPY1]], [[COPY3]]
65 ; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY [[VSUBSSZrr]]
66 ; AVX512F: $xmm0 = COPY [[COPY4]]
5567 ; AVX512F: RET 0, implicit $xmm0
5668 ; AVX512VL-LABEL: name: test_fsub_float
57 ; AVX512VL: [[COPY:%[0-9]+]]:fr32x = COPY $xmm0
58 ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY $xmm1
59 ; AVX512VL: [[VSUBSSZrr:%[0-9]+]]:fr32x = VSUBSSZrr [[COPY]], [[COPY1]]
60 ; AVX512VL: $xmm0 = COPY [[VSUBSSZrr]]
69 ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
70 ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
71 ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
72 ; AVX512VL: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]]
73 ; AVX512VL: [[VSUBSSZrr:%[0-9]+]]:fr32x = VSUBSSZrr [[COPY1]], [[COPY3]]
74 ; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY [[VSUBSSZrr]]
75 ; AVX512VL: $xmm0 = COPY [[COPY4]]
6176 ; AVX512VL: RET 0, implicit $xmm0
62 %0(s32) = COPY $xmm0
63 %1(s32) = COPY $xmm1
64 %2(s32) = G_FSUB %0, %1
65 $xmm0 = COPY %2(s32)
77 %2:vecr(s128) = COPY $xmm0
78 %0:vecr(s32) = G_TRUNC %2(s128)
79 %3:vecr(s128) = COPY $xmm1
80 %1:vecr(s32) = G_TRUNC %3(s128)
81 %4:vecr(s32) = G_FSUB %0, %1
82 %5:vecr(s128) = G_ANYEXT %4(s32)
83 $xmm0 = COPY %5(s128)
6684 RET 0, implicit $xmm0
6785
6886 ...
7694 - { id: 0, class: vecr, preferred-register: '' }
7795 - { id: 1, class: vecr, preferred-register: '' }
7896 - { id: 2, class: vecr, preferred-register: '' }
97 - { id: 3, class: vecr, preferred-register: '' }
98 - { id: 4, class: vecr, preferred-register: '' }
99 - { id: 5, class: vecr, preferred-register: '' }
79100 liveins:
80101 fixedStack:
81102 stack:
87108 liveins: $xmm0, $xmm1
88109
89110 ; SSE-LABEL: name: test_fsub_double
90 ; SSE: [[COPY:%[0-9]+]]:fr64 = COPY $xmm0
91 ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY $xmm1
92 ; SSE: [[SUBSDrr:%[0-9]+]]:fr64 = SUBSDrr [[COPY]], [[COPY1]]
93 ; SSE: $xmm0 = COPY [[SUBSDrr]]
111 ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
112 ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
113 ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
114 ; SSE: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
115 ; SSE: [[SUBSDrr:%[0-9]+]]:fr64 = SUBSDrr [[COPY1]], [[COPY3]]
116 ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY [[SUBSDrr]]
117 ; SSE: $xmm0 = COPY [[COPY4]]
94118 ; SSE: RET 0, implicit $xmm0
95119 ; AVX-LABEL: name: test_fsub_double
96 ; AVX: [[COPY:%[0-9]+]]:fr64 = COPY $xmm0
97 ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY $xmm1
98 ; AVX: [[VSUBSDrr:%[0-9]+]]:fr64 = VSUBSDrr [[COPY]], [[COPY1]]
99 ; AVX: $xmm0 = COPY [[VSUBSDrr]]
120 ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
121 ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
122 ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
123 ; AVX: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
124 ; AVX: [[VSUBSDrr:%[0-9]+]]:fr64 = VSUBSDrr [[COPY1]], [[COPY3]]
125 ; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY [[VSUBSDrr]]
126 ; AVX: $xmm0 = COPY [[COPY4]]
100127 ; AVX: RET 0, implicit $xmm0
101128 ; AVX512F-LABEL: name: test_fsub_double
102 ; AVX512F: [[COPY:%[0-9]+]]:fr64x = COPY $xmm0
103 ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY $xmm1
104 ; AVX512F: [[VSUBSDZrr:%[0-9]+]]:fr64x = VSUBSDZrr [[COPY]], [[COPY1]]
105 ; AVX512F: $xmm0 = COPY [[VSUBSDZrr]]
129 ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
130 ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
131 ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
132 ; AVX512F: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]]
133 ; AVX512F: [[VSUBSDZrr:%[0-9]+]]:fr64x = VSUBSDZrr [[COPY1]], [[COPY3]]
134 ; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY [[VSUBSDZrr]]
135 ; AVX512F: $xmm0 = COPY [[COPY4]]
106136 ; AVX512F: RET 0, implicit $xmm0
107137 ; AVX512VL-LABEL: name: test_fsub_double
108 ; AVX512VL: [[COPY:%[0-9]+]]:fr64x = COPY $xmm0
109 ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY $xmm1
110 ; AVX512VL: [[VSUBSDZrr:%[0-9]+]]:fr64x = VSUBSDZrr [[COPY]], [[COPY1]]
111 ; AVX512VL: $xmm0 = COPY [[VSUBSDZrr]]
138 ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
139 ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
140 ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
141 ; AVX512VL: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]]
142 ; AVX512VL: [[VSUBSDZrr:%[0-9]+]]:fr64x = VSUBSDZrr [[COPY1]], [[COPY3]]
143 ; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY [[VSUBSDZrr]]
144 ; AVX512VL: $xmm0 = COPY [[COPY4]]
112145 ; AVX512VL: RET 0, implicit $xmm0
113 %0(s64) = COPY $xmm0
114 %1(s64) = COPY $xmm1
115 %2(s64) = G_FSUB %0, %1
116 $xmm0 = COPY %2(s64)
146 %2:vecr(s128) = COPY $xmm0
147 %0:vecr(s64) = G_TRUNC %2(s128)
148 %3:vecr(s128) = COPY $xmm1
149 %1:vecr(s64) = G_TRUNC %3(s128)
150 %4:vecr(s64) = G_FSUB %0, %1
151 %5:vecr(s128) = G_ANYEXT %4(s64)
152 $xmm0 = COPY %5(s128)
117153 RET 0, implicit $xmm0
118154
119155 ...
256256 legalized: true
257257 regBankSelected: true
258258 registers:
259 - { id: 0, class: gpr }
260 - { id: 1, class: gpr }
259 - { id: 0, class: gpr, preferred-register: '' }
260 - { id: 1, class: gpr, preferred-register: '' }
261 - { id: 2, class: vecr, preferred-register: '' }
262 - { id: 3, class: vecr, preferred-register: '' }
261263 body: |
262264 bb.1 (%ir-block.0):
263265 liveins: $rdi
265267 ; SSE-LABEL: name: test_load_float
266268 ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
267269 ; SSE: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load 4 from %ir.p1)
268 ; SSE: $xmm0 = COPY [[MOV32rm]]
270 ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[MOV32rm]]
271 ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY1]]
272 ; SSE: $xmm0 = COPY [[COPY2]]
269273 ; SSE: RET 0, implicit $xmm0
270274 ; AVX-LABEL: name: test_load_float
271275 ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
272276 ; AVX: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load 4 from %ir.p1)
273 ; AVX: $xmm0 = COPY [[MOV32rm]]
277 ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[MOV32rm]]
278 ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY1]]
279 ; AVX: $xmm0 = COPY [[COPY2]]
274280 ; AVX: RET 0, implicit $xmm0
275281 ; AVX512F-LABEL: name: test_load_float
276282 ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
277283 ; AVX512F: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load 4 from %ir.p1)
278 ; AVX512F: $xmm0 = COPY [[MOV32rm]]
284 ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[MOV32rm]]
285 ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY [[COPY1]]
286 ; AVX512F: $xmm0 = COPY [[COPY2]]
279287 ; AVX512F: RET 0, implicit $xmm0
280288 ; AVX512VL-LABEL: name: test_load_float
281289 ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
282290 ; AVX512VL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load 4 from %ir.p1)
283 ; AVX512VL: $xmm0 = COPY [[MOV32rm]]
291 ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[MOV32rm]]
292 ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY [[COPY1]]
293 ; AVX512VL: $xmm0 = COPY [[COPY2]]
284294 ; AVX512VL: RET 0, implicit $xmm0
285 %0(p0) = COPY $rdi
286 %1(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1)
287 $xmm0 = COPY %1(s32)
295 %0:gpr(p0) = COPY $rdi
296 %1:gpr(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1)
297 %3:vecr(s32) = COPY %1(s32)
298 %2:vecr(s128) = G_ANYEXT %3(s32)
299 $xmm0 = COPY %2(s128)
288300 RET 0, implicit $xmm0
289301
290302 ...
294306 legalized: true
295307 regBankSelected: true
296308 registers:
297 - { id: 0, class: gpr }
298 - { id: 1, class: vecr }
309 - { id: 0, class: gpr, preferred-register: '' }
310 - { id: 1, class: gpr, preferred-register: '' }
311 - { id: 2, class: vecr, preferred-register: '' }
312 - { id: 3, class: vecr, preferred-register: '' }
299313 body: |
300314 bb.1 (%ir-block.0):
301315 liveins: $rdi
302316
303317 ; SSE-LABEL: name: test_load_float_vecreg
304318 ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
305 ; SSE: [[MOVSSrm:%[0-9]+]]:fr32 = MOVSSrm [[COPY]], 1, $noreg, 0, $noreg :: (load 4 from %ir.p1)
306 ; SSE: $xmm0 = COPY [[MOVSSrm]]
319 ; SSE: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load 4 from %ir.p1)
320 ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[MOV32rm]]
321 ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY1]]
322 ; SSE: $xmm0 = COPY [[COPY2]]
307323 ; SSE: RET 0, implicit $xmm0
308324 ; AVX-LABEL: name: test_load_float_vecreg
309325 ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
310 ; AVX: [[VMOVSSrm:%[0-9]+]]:fr32 = VMOVSSrm [[COPY]], 1, $noreg, 0, $noreg :: (load 4 from %ir.p1)
311 ; AVX: $xmm0 = COPY [[VMOVSSrm]]
326 ; AVX: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load 4 from %ir.p1)
327 ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[MOV32rm]]
328 ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY1]]
329 ; AVX: $xmm0 = COPY [[COPY2]]
312330 ; AVX: RET 0, implicit $xmm0
313331 ; AVX512F-LABEL: name: test_load_float_vecreg
314332 ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
315 ; AVX512F: [[VMOVSSZrm:%[0-9]+]]:fr32x = VMOVSSZrm [[COPY]], 1, $noreg, 0, $noreg :: (load 4 from %ir.p1)
316 ; AVX512F: $xmm0 = COPY [[VMOVSSZrm]]
333 ; AVX512F: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load 4 from %ir.p1)
334 ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[MOV32rm]]
335 ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY [[COPY1]]
336 ; AVX512F: $xmm0 = COPY [[COPY2]]
317337 ; AVX512F: RET 0, implicit $xmm0
318338 ; AVX512VL-LABEL: name: test_load_float_vecreg
319339 ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
320 ; AVX512VL: [[VMOVSSZrm:%[0-9]+]]:fr32x = VMOVSSZrm [[COPY]], 1, $noreg, 0, $noreg :: (load 4 from %ir.p1)
321 ; AVX512VL: $xmm0 = COPY [[VMOVSSZrm]]
340 ; AVX512VL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load 4 from %ir.p1)
341 ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[MOV32rm]]
342 ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY [[COPY1]]
343 ; AVX512VL: $xmm0 = COPY [[COPY2]]
322344 ; AVX512VL: RET 0, implicit $xmm0
323 %0(p0) = COPY $rdi
324 %1(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1)
325 $xmm0 = COPY %1(s32)
345 %0:gpr(p0) = COPY $rdi
346 %1:gpr(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1)
347 %3:vecr(s32) = COPY %1(s32)
348 %2:vecr(s128) = G_ANYEXT %3(s32)
349 $xmm0 = COPY %2(s128)
326350 RET 0, implicit $xmm0
327351
328352 ...
332356 legalized: true
333357 regBankSelected: true
334358 registers:
335 - { id: 0, class: gpr }
336 - { id: 1, class: gpr }
359 - { id: 0, class: gpr, preferred-register: '' }
360 - { id: 1, class: gpr, preferred-register: '' }
361 - { id: 2, class: vecr, preferred-register: '' }
362 - { id: 3, class: vecr, preferred-register: '' }
337363 body: |
338364 bb.1 (%ir-block.0):
339365 liveins: $rdi
341367 ; SSE-LABEL: name: test_load_double
342368 ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
343369 ; SSE: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load 8 from %ir.p1)
344 ; SSE: $xmm0 = COPY [[MOV64rm]]
370 ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[MOV64rm]]
371 ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY1]]
372 ; SSE: $xmm0 = COPY [[COPY2]]
345373 ; SSE: RET 0, implicit $xmm0
346374 ; AVX-LABEL: name: test_load_double
347375 ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
348376 ; AVX: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load 8 from %ir.p1)
349 ; AVX: $xmm0 = COPY [[MOV64rm]]
377 ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[MOV64rm]]
378 ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY1]]
379 ; AVX: $xmm0 = COPY [[COPY2]]
350380 ; AVX: RET 0, implicit $xmm0
351381 ; AVX512F-LABEL: name: test_load_double
352382 ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
353383 ; AVX512F: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load 8 from %ir.p1)
354 ; AVX512F: $xmm0 = COPY [[MOV64rm]]
384 ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[MOV64rm]]
385 ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY [[COPY1]]
386 ; AVX512F: $xmm0 = COPY [[COPY2]]
355387 ; AVX512F: RET 0, implicit $xmm0
356388 ; AVX512VL-LABEL: name: test_load_double
357389 ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
358390 ; AVX512VL: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load 8 from %ir.p1)
359 ; AVX512VL: $xmm0 = COPY [[MOV64rm]]
391 ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[MOV64rm]]
392 ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY [[COPY1]]
393 ; AVX512VL: $xmm0 = COPY [[COPY2]]
360394 ; AVX512VL: RET 0, implicit $xmm0
361 %0(p0) = COPY $rdi
362 %1(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1)
363 $xmm0 = COPY %1(s64)
395 %0:gpr(p0) = COPY $rdi
396 %1:gpr(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1)
397 %3:vecr(s64) = COPY %1(s64)
398 %2:vecr(s128) = G_ANYEXT %3(s64)
399 $xmm0 = COPY %2(s128)
364400 RET 0, implicit $xmm0
365401
366402 ...
370406 legalized: true
371407 regBankSelected: true
372408 registers:
373 - { id: 0, class: gpr }
374 - { id: 1, class: vecr }
409 - { id: 0, class: gpr, preferred-register: '' }
410 - { id: 1, class: gpr, preferred-register: '' }
411 - { id: 2, class: vecr, preferred-register: '' }
412 - { id: 3, class: vecr, preferred-register: '' }
375413 body: |
376414 bb.1 (%ir-block.0):
377415 liveins: $rdi
378416
379417 ; SSE-LABEL: name: test_load_double_vecreg
380418 ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
381 ; SSE: [[MOVSDrm:%[0-9]+]]:fr64 = MOVSDrm [[COPY]], 1, $noreg, 0, $noreg :: (load 8 from %ir.p1)
382 ; SSE: $xmm0 = COPY [[MOVSDrm]]
419 ; SSE: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load 8 from %ir.p1)
420 ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[MOV64rm]]
421 ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY1]]
422 ; SSE: $xmm0 = COPY [[COPY2]]
383423 ; SSE: RET 0, implicit $xmm0
384424 ; AVX-LABEL: name: test_load_double_vecreg
385425 ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
386 ; AVX: [[VMOVSDrm:%[0-9]+]]:fr64 = VMOVSDrm [[COPY]], 1, $noreg, 0, $noreg :: (load 8 from %ir.p1)
387 ; AVX: $xmm0 = COPY [[VMOVSDrm]]
426 ; AVX: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load 8 from %ir.p1)
427 ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[MOV64rm]]
428 ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY1]]
429 ; AVX: $xmm0 = COPY [[COPY2]]
388430 ; AVX: RET 0, implicit $xmm0
389431 ; AVX512F-LABEL: name: test_load_double_vecreg
390432 ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
391 ; AVX512F: [[VMOVSDZrm:%[0-9]+]]:fr64x = VMOVSDZrm [[COPY]], 1, $noreg, 0, $noreg :: (load 8 from %ir.p1)
392 ; AVX512F: $xmm0 = COPY [[VMOVSDZrm]]
433 ; AVX512F: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load 8 from %ir.p1)
434 ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[MOV64rm]]
435 ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY [[COPY1]]
436 ; AVX512F: $xmm0 = COPY [[COPY2]]
393437 ; AVX512F: RET 0, implicit $xmm0
394438 ; AVX512VL-LABEL: name: test_load_double_vecreg
395439 ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
396 ; AVX512VL: [[VMOVSDZrm:%[0-9]+]]:fr64x = VMOVSDZrm [[COPY]], 1, $noreg, 0, $noreg :: (load 8 from %ir.p1)
397 ; AVX512VL: $xmm0 = COPY [[VMOVSDZrm]]
440 ; AVX512VL: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load 8 from %ir.p1)
441 ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[MOV64rm]]
442 ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY [[COPY1]]
443 ; AVX512VL: $xmm0 = COPY [[COPY2]]
398444 ; AVX512VL: RET 0, implicit $xmm0
399 %0(p0) = COPY $rdi
400 %1(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1)
401 $xmm0 = COPY %1(s64)
445 %0:gpr(p0) = COPY $rdi
446 %1:gpr(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1)
447 %3:vecr(s64) = COPY %1(s64)
448 %2:vecr(s128) = G_ANYEXT %3(s64)
449 $xmm0 = COPY %2(s128)
402450 RET 0, implicit $xmm0
403451
404452 ...
494542 legalized: true
495543 regBankSelected: true
496544 registers:
497 - { id: 0, class: vecr }
498 - { id: 1, class: gpr }
499 - { id: 2, class: gpr }
545 - { id: 0, class: vecr, preferred-register: '' }
546 - { id: 1, class: gpr, preferred-register: '' }
547 - { id: 2, class: vecr, preferred-register: '' }
548 - { id: 3, class: gpr, preferred-register: '' }
500549 body: |
501550 bb.1 (%ir-block.0):
502551 liveins: $rdi, $xmm0
503552
504553 ; SSE-LABEL: name: test_store_float
505 ; SSE: [[COPY:%[0-9]+]]:fr32 = COPY $xmm0
506 ; SSE: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
507 ; SSE: [[COPY2:%[0-9]+]]:gr32 = COPY [[COPY]]
508 ; SSE: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store 4 into %ir.p1)
509 ; SSE: $rax = COPY [[COPY1]]
554 ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
555 ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
556 ; SSE: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
557 ; SSE: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY1]]
558 ; SSE: MOV32mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store 4 into %ir.p1)
559 ; SSE: $rax = COPY [[COPY2]]
510560 ; SSE: RET 0, implicit $rax
511561 ; AVX-LABEL: name: test_store_float
512 ; AVX: [[COPY:%[0-9]+]]:fr32 = COPY $xmm0
513 ; AVX: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
514 ; AVX: [[COPY2:%[0-9]+]]:gr32 = COPY [[COPY]]
515 ; AVX: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store 4 into %ir.p1)
516 ; AVX: $rax = COPY [[COPY1]]
562 ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
563 ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
564 ; AVX: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
565 ; AVX: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY1]]
566 ; AVX: MOV32mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store 4 into %ir.p1)
567 ; AVX: $rax = COPY [[COPY2]]
517568 ; AVX: RET 0, implicit $rax
518569 ; AVX512F-LABEL: name: test_store_float
519 ; AVX512F: [[COPY:%[0-9]+]]:fr32x = COPY $xmm0
520 ; AVX512F: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
521 ; AVX512F: [[COPY2:%[0-9]+]]:gr32 = COPY [[COPY]]
522 ; AVX512F: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store 4 into %ir.p1)
523 ; AVX512F: $rax = COPY [[COPY1]]
570 ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
571 ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
572 ; AVX512F: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
573 ; AVX512F: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY1]]
574 ; AVX512F: MOV32mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store 4 into %ir.p1)
575 ; AVX512F: $rax = COPY [[COPY2]]
524576 ; AVX512F: RET 0, implicit $rax
525577 ; AVX512VL-LABEL: name: test_store_float
526 ; AVX512VL: [[COPY:%[0-9]+]]:fr32x = COPY $xmm0
527 ; AVX512VL: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
528 ; AVX512VL: [[COPY2:%[0-9]+]]:gr32 = COPY [[COPY]]
529 ; AVX512VL: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store 4 into %ir.p1)
530 ; AVX512VL: $rax = COPY [[COPY1]]
578 ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
579 ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
580 ; AVX512VL: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
581 ; AVX512VL: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY1]]
582 ; AVX512VL: MOV32mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store 4 into %ir.p1)
583 ; AVX512VL: $rax = COPY [[COPY2]]
531584 ; AVX512VL: RET 0, implicit $rax
532 %0(s32) = COPY $xmm0
533 %1(p0) = COPY $rdi
534 %2(s32) = COPY %0(s32)
535 G_STORE %2(s32), %1(p0) :: (store 4 into %ir.p1)
585 %2:vecr(s128) = COPY $xmm0
586 %0:vecr(s32) = G_TRUNC %2(s128)
587 %1:gpr(p0) = COPY $rdi
588 %3:gpr(s32) = COPY %0(s32)
589 G_STORE %3(s32), %1(p0) :: (store 4 into %ir.p1)
536590 $rax = COPY %1(p0)
537591 RET 0, implicit $rax
538592
543597 legalized: true
544598 regBankSelected: true
545599 registers:
546 - { id: 0, class: vecr }
547 - { id: 1, class: gpr }
600 - { id: 0, class: vecr, preferred-register: '' }
601 - { id: 1, class: gpr, preferred-register: '' }
602 - { id: 2, class: vecr, preferred-register: '' }
603 - { id: 3, class: gpr, preferred-register: '' }
548604 body: |
549605 bb.1 (%ir-block.0):
550606 liveins: $rdi, $xmm0
551607
552608 ; SSE-LABEL: name: test_store_float_vec
553 ; SSE: [[COPY:%[0-9]+]]:fr32 = COPY $xmm0
554 ; SSE: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
555 ; SSE: MOVSSmr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store 4 into %ir.p1)
556 ; SSE: $rax = COPY [[COPY1]]
609 ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
610 ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
611 ; SSE: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
612 ; SSE: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY1]]
613 ; SSE: MOV32mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store 4 into %ir.p1)
614 ; SSE: $rax = COPY [[COPY2]]
557615 ; SSE: RET 0, implicit $rax
558616 ; AVX-LABEL: name: test_store_float_vec
559 ; AVX: [[COPY:%[0-9]+]]:fr32 = COPY $xmm0
560 ; AVX: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
561 ; AVX: VMOVSSmr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store 4 into %ir.p1)
562 ; AVX: $rax = COPY [[COPY1]]
617 ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
618 ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
619 ; AVX: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
620 ; AVX: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY1]]
621 ; AVX: MOV32mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store 4 into %ir.p1)
622 ; AVX: $rax = COPY [[COPY2]]
563623 ; AVX: RET 0, implicit $rax
564624 ; AVX512F-LABEL: name: test_store_float_vec
565 ; AVX512F: [[COPY:%[0-9]+]]:fr32x = COPY $xmm0
566 ; AVX512F: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
567 ; AVX512F: VMOVSSZmr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store 4 into %ir.p1)
568 ; AVX512F: $rax = COPY [[COPY1]]
625 ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
626 ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
627 ; AVX512F: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
628 ; AVX512F: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY1]]
629 ; AVX512F: MOV32mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store 4 into %ir.p1)
630 ; AVX512F: $rax = COPY [[COPY2]]
569631 ; AVX512F: RET 0, implicit $rax
570632 ; AVX512VL-LABEL: name: test_store_float_vec
571 ; AVX512VL: [[COPY:%[0-9]+]]:fr32x = COPY $xmm0
572 ; AVX512VL: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
573 ; AVX512VL: VMOVSSZmr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store 4 into %ir.p1)
574 ; AVX512VL: $rax = COPY [[COPY1]]
633 ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
634 ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
635 ; AVX512VL: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
636 ; AVX512VL: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY1]]
637 ; AVX512VL: MOV32mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store 4 into %ir.p1)
638 ; AVX512VL: $rax = COPY [[COPY2]]
575639 ; AVX512VL: RET 0, implicit $rax
576 %0(s32) = COPY $xmm0
577 %1(p0) = COPY $rdi
578 G_STORE %0(s32), %1(p0) :: (store 4 into %ir.p1)
640 %2:vecr(s128) = COPY $xmm0
641 %0:vecr(s32) = G_TRUNC %2(s128)
642 %1:gpr(p0) = COPY $rdi
643 %3:gpr(s32) = COPY %0(s32)
644 G_STORE %3(s32), %1(p0) :: (store 4 into %ir.p1)
579645 $rax = COPY %1(p0)
580646 RET 0, implicit $rax
581647
586652 legalized: true
587653 regBankSelected: true
588654 registers:
589 - { id: 0, class: vecr }
590 - { id: 1, class: gpr }
591 - { id: 2, class: gpr }
655 - { id: 0, class: vecr, preferred-register: '' }
656 - { id: 1, class: gpr, preferred-register: '' }
657 - { id: 2, class: vecr, preferred-register: '' }
658 - { id: 3, class: gpr, preferred-register: '' }
592659 # NO_AVX512X: %0:fr64 = COPY $xmm0
593660 body: |
594661 bb.1 (%ir-block.0):
595662 liveins: $rdi, $xmm0
596663
597664 ; SSE-LABEL: name: test_store_double
598 ; SSE: [[COPY:%[0-9]+]]:fr64 = COPY $xmm0
599 ; SSE: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
600 ; SSE: [[COPY2:%[0-9]+]]:gr64 = COPY [[COPY]]
601 ; SSE: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store 8 into %ir.p1)
602 ; SSE: $rax = COPY [[COPY1]]
665 ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
666 ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
667 ; SSE: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
668 ; SSE: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY1]]
669 ; SSE: MOV64mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store 8 into %ir.p1)
670 ; SSE: $rax = COPY [[COPY2]]
603671 ; SSE: RET 0, implicit $rax
604672 ; AVX-LABEL: name: test_store_double
605 ; AVX: [[COPY:%[0-9]+]]:fr64 = COPY $xmm0
606 ; AVX: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
607 ; AVX: [[COPY2:%[0-9]+]]:gr64 = COPY [[COPY]]
608 ; AVX: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store 8 into %ir.p1)
609 ; AVX: $rax = COPY [[COPY1]]
673 ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
674 ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
675 ; AVX: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
676 ; AVX: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY1]]
677 ; AVX: MOV64mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store 8 into %ir.p1)
678 ; AVX: $rax = COPY [[COPY2]]
610679 ; AVX: RET 0, implicit $rax
611680 ; AVX512F-LABEL: name: test_store_double
612 ; AVX512F: [[COPY:%[0-9]+]]:fr64x = COPY $xmm0
613 ; AVX512F: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
614 ; AVX512F: [[COPY2:%[0-9]+]]:gr64 = COPY [[COPY]]
615 ; AVX512F: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store 8 into %ir.p1)
616 ; AVX512F: $rax = COPY [[COPY1]]
681 ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
682 ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
683 ; AVX512F: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
684 ; AVX512F: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY1]]
685 ; AVX512F: MOV64mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store 8 into %ir.p1)
686 ; AVX512F: $rax = COPY [[COPY2]]
617687 ; AVX512F: RET 0, implicit $rax
618688 ; AVX512VL-LABEL: name: test_store_double
619 ; AVX512VL: [[COPY:%[0-9]+]]:fr64x = COPY $xmm0
620 ; AVX512VL: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
621 ; AVX512VL: [[COPY2:%[0-9]+]]:gr64 = COPY [[COPY]]
622 ; AVX512VL: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store 8 into %ir.p1)
623 ; AVX512VL: $rax = COPY [[COPY1]]
689 ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
690 ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
691 ; AVX512VL: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
692 ; AVX512VL: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY1]]
693 ; AVX512VL: MOV64mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store 8 into %ir.p1)
694 ; AVX512VL: $rax = COPY [[COPY2]]
624695 ; AVX512VL: RET 0, implicit $rax
625 %0(s64) = COPY $xmm0
626 %1(p0) = COPY $rdi
627 %2(s64) = COPY %0(s64)
628 G_STORE %2(s64), %1(p0) :: (store 8 into %ir.p1)
696 %2:vecr(s128) = COPY $xmm0
697 %0:vecr(s64) = G_TRUNC %2(s128)
698 %1:gpr(p0) = COPY $rdi
699 %3:gpr(s64) = COPY %0(s64)
700 G_STORE %3(s64), %1(p0) :: (store 8 into %ir.p1)
629701 $rax = COPY %1(p0)
630702 RET 0, implicit $rax
631703
636708 legalized: true
637709 regBankSelected: true
638710 registers:
639 - { id: 0, class: vecr }
640 - { id: 1, class: gpr }
711 - { id: 0, class: vecr, preferred-register: '' }
712 - { id: 1, class: gpr, preferred-register: '' }
713 - { id: 2, class: vecr, preferred-register: '' }
714 - { id: 3, class: gpr, preferred-register: '' }
641715 body: |
642716 bb.1 (%ir-block.0):
643717 liveins: $rdi, $xmm0
644718
645719 ; SSE-LABEL: name: test_store_double_vec
646 ; SSE: [[COPY:%[0-9]+]]:fr64 = COPY $xmm0
647 ; SSE: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
648 ; SSE: MOVSDmr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store 8 into %ir.p1)
649 ; SSE: $rax = COPY [[COPY1]]
720 ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
721 ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
722 ; SSE: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
723 ; SSE: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY1]]
724 ; SSE: MOV64mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store 8 into %ir.p1)
725 ; SSE: $rax = COPY [[COPY2]]
650726 ; SSE: RET 0, implicit $rax
651727 ; AVX-LABEL: name: test_store_double_vec
652 ; AVX: [[COPY:%[0-9]+]]:fr64 = COPY $xmm0
653 ; AVX: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
654 ; AVX: VMOVSDmr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store 8 into %ir.p1)
655 ; AVX: $rax = COPY [[COPY1]]
728 ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
729 ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
730 ; AVX: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
731 ; AVX: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY1]]
732 ; AVX: MOV64mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store 8 into %ir.p1)
733 ; AVX: $rax = COPY [[COPY2]]
656734 ; AVX: RET 0, implicit $rax
657735 ; AVX512F-LABEL: name: test_store_double_vec
658 ; AVX512F: [[COPY:%[0-9]+]]:fr64x = COPY $xmm0
659 ; AVX512F: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
660 ; AVX512F: VMOVSDZmr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store 8 into %ir.p1)
661 ; AVX512F: $rax = COPY [[COPY1]]
736 ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
737 ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
738 ; AVX512F: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
739 ; AVX512F: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY1]]
740 ; AVX512F: MOV64mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store 8 into %ir.p1)
741 ; AVX512F: $rax = COPY [[COPY2]]
662742 ; AVX512F: RET 0, implicit $rax
663743 ; AVX512VL-LABEL: name: test_store_double_vec
664 ; AVX512VL: [[COPY:%[0-9]+]]:fr64x = COPY $xmm0
665 ; AVX512VL: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
666 ; AVX512VL: VMOVSDZmr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store 8 into %ir.p1)
667 ; AVX512VL: $rax = COPY [[COPY1]]
744 ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
745 ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
746 ; AVX512VL: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
747 ; AVX512VL: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY1]]
748 ; AVX512VL: MOV64mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store 8 into %ir.p1)
749 ; AVX512VL: $rax = COPY [[COPY2]]
668750 ; AVX512VL: RET 0, implicit $rax
669 %0(s64) = COPY $xmm0
670 %1(p0) = COPY $rdi
671 G_STORE %0(s64), %1(p0) :: (store 8 into %ir.p1)
751 %2:vecr(s128) = COPY $xmm0
752 %0:vecr(s64) = G_TRUNC %2(s128)
753 %1:gpr(p0) = COPY $rdi
754 %3:gpr(s64) = COPY %0(s64)
755 G_STORE %3(s64), %1(p0) :: (store 8 into %ir.p1)
672756 $rax = COPY %1(p0)
673757 RET 0, implicit $rax
674758
345345 ...
346346 ---
347347 name: test_float
348 # ALL-LABEL: name: test_float
349 alignment: 4
350 legalized: true
351 regBankSelected: true
352 tracksRegLiveness: true
353 # ALL: registers:
354 # ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
355 # ALL-NEXT: - { id: 1, class: fr32, preferred-register: '' }
356 # ALL-NEXT: - { id: 2, class: fr32, preferred-register: '' }
357 # ALL-NEXT: - { id: 3, class: gr32, preferred-register: '' }
358 # ALL-NEXT: - { id: 4, class: gr8, preferred-register: '' }
359 # ALL-NEXT: - { id: 5, class: fr32, preferred-register: '' }
348 alignment: 4
349 legalized: true
350 regBankSelected: true
351 tracksRegLiveness: true
360352 registers:
361353 - { id: 0, class: gpr, preferred-register: '' }
362354 - { id: 1, class: vecr, preferred-register: '' }
363355 - { id: 2, class: vecr, preferred-register: '' }
364 - { id: 3, class: gpr, preferred-register: '' }
365 - { id: 4, class: gpr, preferred-register: '' }
366 - { id: 5, class: vecr, preferred-register: '' }
356 - { id: 3, class: vecr, preferred-register: '' }
357 - { id: 4, class: vecr, preferred-register: '' }
358 - { id: 5, class: gpr, preferred-register: '' }
359 - { id: 6, class: gpr, preferred-register: '' }
360 - { id: 7, class: vecr, preferred-register: '' }
361 - { id: 8, class: vecr, preferred-register: '' }
367362 liveins:
368363 fixedStack:
369364 stack:
370365 constants:
371 # ALL-LABEL: bb.3.cond.end:
372 # ALL: %5:fr32 = PHI %1, %bb.1, %2, %bb.2
373 # ALL-NEXT: $xmm0 = COPY %5
374 # ALL-NEXT: RET 0, implicit $xmm0
375 body: |
376 bb.1.entry:
377 successors: %bb.2(0x40000000), %bb.3(0x40000000)
366 body: |
367 ; ALL-LABEL: name: test_float
368 ; ALL: bb.0.entry:
369 ; ALL: successors: %bb.2(0x40000000), %bb.1(0x40000000)
370 ; ALL: liveins: $edi, $xmm0, $xmm1
371 ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
372 ; ALL: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
373 ; ALL: [[COPY2:%[0-9]+]]:fr32 = COPY [[COPY1]]
374 ; ALL: [[COPY3:%[0-9]+]]:vr128 = COPY $xmm1
375 ; ALL: [[COPY4:%[0-9]+]]:fr32 = COPY [[COPY3]]
376 ; ALL: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
377 ; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
378 ; ALL: [[SETGr:%[0-9]+]]:gr8 = SETGr implicit $eflags
379 ; ALL: TEST8ri [[SETGr]], 1, implicit-def $eflags
380 ; ALL: JNE_1 %bb.2, implicit $eflags
381 ; ALL: bb.1.cond.false:
382 ; ALL: successors: %bb.2(0x80000000)
383 ; ALL: bb.2.cond.end:
384 ; ALL: [[PHI:%[0-9]+]]:fr32 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0
385 ; ALL: [[COPY5:%[0-9]+]]:vr128 = COPY [[PHI]]
386 ; ALL: $xmm0 = COPY [[COPY5]]
387 ; ALL: RET 0, implicit $xmm0
388 bb.1.entry:
389 successors: %bb.3(0x40000000), %bb.2(0x40000000)
378390 liveins: $edi, $xmm0, $xmm1
379391
380 %0(s32) = COPY $edi
381 %1(s32) = COPY $xmm0
382 %2(s32) = COPY $xmm1
383 %3(s32) = G_CONSTANT i32 0
384 %4(s1) = G_ICMP intpred(sgt), %0(s32), %3
385 G_BRCOND %4(s1), %bb.2
386 G_BR %bb.3
387
388 bb.2.cond.true:
389 successors: %bb.4(0x80000000)
390
391 G_BR %bb.4
392
393 bb.3.cond.false:
394 successors: %bb.4(0x80000000)
395
396
397 bb.4.cond.end:
398 %5(s32) = G_PHI %1(s32), %bb.2, %2(s32), %bb.3
399 $xmm0 = COPY %5(s32)
392 %0:gpr(s32) = COPY $edi
393 %3:vecr(s128) = COPY $xmm0
394 %1:vecr(s32) = G_TRUNC %3(s128)
395 %4:vecr(s128) = COPY $xmm1
396 %2:vecr(s32) = G_TRUNC %4(s128)
397 %5:gpr(s32) = G_CONSTANT i32 0
398 %6:gpr(s1) = G_ICMP intpred(sgt), %0(s32), %5
399 G_BRCOND %6(s1), %bb.3
400
401 bb.2.cond.false:
402 successors: %bb.3(0x80000000)
403
404 bb.3.cond.end:
405 %7:vecr(s32) = G_PHI %2(s32), %bb.2, %1(s32), %bb.1
406 %8:vecr(s128) = G_ANYEXT %7(s32)
407 $xmm0 = COPY %8(s128)
400408 RET 0, implicit $xmm0
401409
402410 ...
403411 ---
404412 name: test_double
405 # ALL-LABEL: name: test_double
406 alignment: 4
407 legalized: true
408 regBankSelected: true
409 tracksRegLiveness: true
410 # ALL: registers:
411 # ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
412 # ALL-NEXT: - { id: 1, class: fr64, preferred-register: '' }
413 # ALL-NEXT: - { id: 2, class: fr64, preferred-register: '' }
414 # ALL-NEXT: - { id: 3, class: gr32, preferred-register: '' }
415 # ALL-NEXT: - { id: 4, class: gr8, preferred-register: '' }
416 # ALL-NEXT: - { id: 5, class: fr64, preferred-register: '' }
413 alignment: 4
414 legalized: true
415 regBankSelected: true
416 tracksRegLiveness: true
417417 registers:
418418 - { id: 0, class: gpr, preferred-register: '' }
419419 - { id: 1, class: vecr, preferred-register: '' }
420420 - { id: 2, class: vecr, preferred-register: '' }
421 - { id: 3, class: gpr, preferred-register: '' }
422 - { id: 4, class: gpr, preferred-register: '' }
423 - { id: 5, class: vecr, preferred-register: '' }
424 # ALL-LABEL: bb.3.cond.end:
425 # ALL: %5:fr64 = PHI %1, %bb.1, %2, %bb.2
426 # ALL-NEXT: $xmm0 = COPY %5
427 # ALL-NEXT: RET 0, implicit $xmm0
428 body: |
429 bb.1.entry:
430 successors: %bb.2(0x40000000), %bb.3(0x40000000)
421 - { id: 3, class: vecr, preferred-register: '' }
422 - { id: 4, class: vecr, preferred-register: '' }
423 - { id: 5, class: gpr, preferred-register: '' }
424 - { id: 6, class: gpr, preferred-register: '' }
425 - { id: 7, class: vecr, preferred-register: '' }
426 - { id: 8, class: vecr, preferred-register: '' }
427 body: |
428 ; ALL-LABEL: name: test_double
429 ; ALL: bb.0.entry:
430 ; ALL: successors: %bb.2(0x40000000), %bb.1(0x40000000)
431 ; ALL: liveins: $edi, $xmm0, $xmm1
432 ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
433 ; ALL: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
434 ; ALL: [[COPY2:%[0-9]+]]:fr64 = COPY [[COPY1]]
435 ; ALL: [[COPY3:%[0-9]+]]:vr128 = COPY $xmm1
436 ; ALL: [[COPY4:%[0-9]+]]:fr64 = COPY [[COPY3]]
437 ; ALL: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
438 ; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
439 ; ALL: [[SETGr:%[0-9]+]]:gr8 = SETGr implicit $eflags
440 ; ALL: TEST8ri [[SETGr]], 1, implicit-def $eflags
441 ; ALL: JNE_1 %bb.2, implicit $eflags
442 ; ALL: bb.1.cond.false:
443 ; ALL: successors: %bb.2(0x80000000)
444 ; ALL: bb.2.cond.end:
445 ; ALL: [[PHI:%[0-9]+]]:fr64 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0
446 ; ALL: [[COPY5:%[0-9]+]]:vr128 = COPY [[PHI]]
447 ; ALL: $xmm0 = COPY [[COPY5]]
448 ; ALL: RET 0, implicit $xmm0
449 bb.1.entry:
450 successors: %bb.3(0x40000000), %bb.2(0x40000000)
431451 liveins: $edi, $xmm0, $xmm1
432452
433 %0(s32) = COPY $edi
434 %1(s64) = COPY $xmm0
435 %2(s64) = COPY $xmm1
436 %3(s32) = G_CONSTANT i32 0
437 %4(s1) = G_ICMP intpred(sgt), %0(s32), %3
438 G_BRCOND %4(s1), %bb.2
439 G_BR %bb.3
440
441 bb.2.cond.true:
442 successors: %bb.4(0x80000000)
443
444 G_BR %bb.4
445
446 bb.3.cond.false:
447 successors: %bb.4(0x80000000)
448
449
450 bb.4.cond.end:
451 %5(s64) = G_PHI %1(s64), %bb.2, %2(s64), %bb.3
452 $xmm0 = COPY %5(s64)
453 %0:gpr(s32) = COPY $edi
454 %3:vecr(s128) = COPY $xmm0
455 %1:vecr(s64) = G_TRUNC %3(s128)
456 %4:vecr(s128) = COPY $xmm1
457 %2:vecr(s64) = G_TRUNC %4(s128)
458 %5:gpr(s32) = G_CONSTANT i32 0
459 %6:gpr(s1) = G_ICMP intpred(sgt), %0(s32), %5
460 G_BRCOND %6(s1), %bb.3
461
462 bb.2.cond.false:
463 successors: %bb.3(0x80000000)
464
465 bb.3.cond.end:
466 %7:vecr(s64) = G_PHI %2(s64), %bb.2, %1(s64), %bb.1
467 %8:vecr(s128) = G_ANYEXT %7(s64)
468 $xmm0 = COPY %8(s128)
453469 RET 0, implicit $xmm0
454470
455471 ...