llvm.org GIT mirror llvm / cbd850f
[PowerPC] Use helper functions to check sign-/zero-extended value Helper functions to identify sign- and zero-extending machine instruction is introduced in rL315888. This patch makes PPCInstrInfo::optimizeCompareInstr use the helper functions. It simplifies the code and also makes possible more optimizations since the helper can do more analysis than the original check code; I observed about 5000 more compare instructions are eliminated while building LLVM. Also, this patch fixes a bug in helpers on ANDIo instruction handling due to the order of checks. This bug causes a failure in an existing test case for optimizeCompareInstr. Differential Revision: https://reviews.llvm.org/D38988 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316071 91177308-0d34-0410-b5e6-96231b3b80d8 Hiroshi Inoue 2 years ago
2 changed file(s) with 32 addition(s) and 23 deletion(s). Raw diff Collapse all Expand all
16331633 // Get the unique definition of SrcReg.
16341634 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
16351635 if (!MI) return false;
1636 int MIOpC = MI->getOpcode();
16371636
16381637 bool equalityOnly = false;
16391638 bool noSub = false;
16401639 if (isPPC64) {
16411640 if (is32BitSignedCompare) {
16421641 // We can perform this optimization only if MI is sign-extending.
1643 if (MIOpC == PPC::SRAW || MIOpC == PPC::SRAWo ||
1644 MIOpC == PPC::SRAWI || MIOpC == PPC::SRAWIo ||
1645 MIOpC == PPC::EXTSB || MIOpC == PPC::EXTSBo ||
1646 MIOpC == PPC::EXTSH || MIOpC == PPC::EXTSHo ||
1647 MIOpC == PPC::EXTSW || MIOpC == PPC::EXTSWo) {
1642 if (isSignExtended(*MI))
16481643 noSub = true;
1649 } else
1644 else
16501645 return false;
16511646 } else if (is32BitUnsignedCompare) {
1652 // 32-bit rotate and mask instructions are zero extending only if MB <= ME
1653 bool isZeroExtendingRotate =
1654 (MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINMo ||
1655 MIOpC == PPC::RLWNM || MIOpC == PPC::RLWNMo)
1656 && MI->getOperand(3).getImm() <= MI->getOperand(4).getImm();
1657
16581647 // We can perform this optimization, equality only, if MI is
16591648 // zero-extending.
1660 // FIXME: Other possible target instructions include ANDISo and
1661 // RLWINM aliases, such as ROTRWI, EXTLWI, SLWI and SRWI.
1662 if (MIOpC == PPC::CNTLZW || MIOpC == PPC::CNTLZWo ||
1663 MIOpC == PPC::SLW || MIOpC == PPC::SLWo ||
1664 MIOpC == PPC::SRW || MIOpC == PPC::SRWo ||
1665 MIOpC == PPC::ANDIo ||
1666 isZeroExtendingRotate) {
1649 if (isZeroExtended(*MI)) {
16671650 noSub = true;
16681651 equalityOnly = true;
16691652 } else
18101793 if (!MI) MI = Sub;
18111794
18121795 int NewOpC = -1;
1813 MIOpC = MI->getOpcode();
1796 int MIOpC = MI->getOpcode();
18141797 if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8)
18151798 NewOpC = MIOpC;
18161799 else {
22222205 const MachineFunction *MF = MI.getParent()->getParent();
22232206 const MachineRegisterInfo *MRI = &MF->getRegInfo();
22242207
2208 // If we know this instruction returns sign- or zero-extended result,
2209 // return true.
2210 if (SignExt ? isSignExtendingOp(MI):
2211 isZeroExtendingOp(MI))
2212 return true;
2213
22252214 switch (MI.getOpcode()) {
22262215 case PPC::COPY: {
22272216 unsigned SrcReg = MI.getOperand(1).getReg();
23382327 }
23392328
23402329 default:
2341 return SignExt?isSignExtendingOp(MI):
2342 isZeroExtendingOp(MI);
2330 break;
23432331 }
23442332 return false;
23452333 }
7777 }
7878
7979 declare void @exit(i32 signext)
80
81 ; Since %v1 and %v2 are zero-extended 32-bit values, %1 is also zero-extended.
82 ; In this case, we want to use ORo instead of OR + CMPLWI.
83
84 ; CHECK-LABEL: fn5
85 define zeroext i32 @fn5(i32* %p1, i32* %p2) {
86 ; CHECK: ORo
87 ; CHECK-NOT: CMP
88 ; CHECK: BCC
89 %v1 = load i32, i32* %p1
90 %v2 = load i32, i32* %p2
91 %1 = or i32 %v1, %v2
92 %2 = icmp eq i32 %1, 0
93 br i1 %2, label %foo, label %bar
94
95 foo:
96 ret i32 1
97
98 bar:
99 ret i32 0
100 }