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[MIRParser] Allow generic register specification on operand. This completes r292321 by adding support for generic registers, e.g.: %2:_(s32) = G_ADD %0, %1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292550 91177308-0d34-0410-b5e6-96231b3b80d8 Ahmed Bougacha 3 years ago
2 changed file(s) with 21 addition(s) and 14 deletion(s). Raw diff Collapse all Expand all
882882 }
883883
884884 bool MIParser::parseRegisterClassOrBank(VRegInfo &RegInfo) {
885 if (Token.isNot(MIToken::Identifier))
886 return error("expected a register class or register bank name");
885 if (Token.isNot(MIToken::Identifier) && Token.isNot(MIToken::underscore))
886 return error("expected '_', register class, or register bank name");
887887 StringRef::iterator Loc = Token.location();
888888 StringRef Name = Token.stringValue();
889889
913913 llvm_unreachable("Unexpected register kind");
914914 }
915915
916 // Should be a register bank.
917 auto RBNameI = PFS.Names2RegBanks.find(Name);
918 lex();
919 if (RBNameI == PFS.Names2RegBanks.end())
920 return error(Loc, "expected a register class or register bank name");
921
922 const RegisterBank &RegBank = *RBNameI->getValue();
916 // Should be a register bank or a generic register.
917 const RegisterBank *RegBank = nullptr;
918 if (Name != "_") {
919 auto RBNameI = PFS.Names2RegBanks.find(Name);
920 if (RBNameI == PFS.Names2RegBanks.end())
921 return error(Loc, "expected '_', register class, or register bank name");
922 RegBank = RBNameI->getValue();
923 }
924
925 lex();
926
923927 switch (RegInfo.Kind) {
924928 case VRegInfo::UNKNOWN:
925929 case VRegInfo::GENERIC:
926930 case VRegInfo::REGBANK:
927 RegInfo.Kind = VRegInfo::REGBANK;
928 if (RegInfo.Explicit && RegInfo.D.RegBank != &RegBank)
929 return error(Loc, "conflicting register banks");
930 RegInfo.D.RegBank = &RegBank;
931 RegInfo.Kind = RegBank ? VRegInfo::REGBANK : VRegInfo::GENERIC;
932 if (RegInfo.Explicit && RegInfo.D.RegBank != RegBank)
933 return error(Loc, "conflicting generic register banks");
934 RegInfo.D.RegBank = RegBank;
931935 RegInfo.Explicit = true;
932936 return false;
933937
934938 case VRegInfo::NORMAL:
935 return error(Loc, "register class specification on normal register");
939 return error(Loc, "register bank specification on normal register");
936940 }
937941 llvm_unreachable("Unexpected register kind");
938942 }
99 # CHECK: - { id: 1, class: gr64 }
1010 # CHECK: - { id: 2, class: gr32 }
1111 # CHECK: - { id: 3, class: gr16 }
12 # CHECK: - { id: 4, class: _ }
1213 name: func
1314 body: |
1415 bb.0:
2021
2122 %3 : gr16 = COPY %bx
2223 %bx = COPY %3 : gr16
24
25 %4 : _(s32) = COPY %edx
2326 ...