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Merging r292473: ------------------------------------------------------------------------ r292473 | arsenm | 2017-01-18 22:35:27 -0800 (Wed, 18 Jan 2017) | 9 lines AMDGPU: Disable some fneg combines unless nsz For -(x + y) -> (-x) + (-y), if x == -y, this would change the result from -0.0 to 0.0. Since the fma/fmad combine is an extension of this problem it also applies there. fmul should be fine, and I don't think any of the unary operators or conversions should be a problem either. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_40@293319 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 2 years ago
4 changed file(s) with 122 addition(s) and 41 deletion(s). Raw diff Collapse all Expand all
28542854 SDLoc SL(N);
28552855 switch (Opc) {
28562856 case ISD::FADD: {
2857 if (!mayIgnoreSignedZero(N0))
2858 return SDValue();
2859
28572860 // (fneg (fadd x, y)) -> (fadd (fneg x), (fneg y))
28582861 SDValue LHS = N0.getOperand(0);
28592862 SDValue RHS = N0.getOperand(1);
28942897 }
28952898 case ISD::FMA:
28962899 case ISD::FMAD: {
2900 if (!mayIgnoreSignedZero(N0))
2901 return SDValue();
2902
28972903 // (fneg (fma x, y, z)) -> (fma x, (fneg y), (fneg z))
28982904 SDValue LHS = N0.getOperand(0);
28992905 SDValue MHS = N0.getOperand(1);
117117
118118 public:
119119 AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
120
121 bool mayIgnoreSignedZero(SDValue Op) const {
122 if (getTargetMachine().Options.UnsafeFPMath) // FIXME: nsz only
123 return true;
124
125 if (const auto *BO = dyn_cast(Op))
126 return BO->Flags.hasNoSignedZeros();
127
128 return false;
129 }
120130
121131 bool isFAbsFree(EVT VT) const override;
122132 bool isFNegFree(EVT VT) const override;
None ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
0 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-SAFE -check-prefix=SI -check-prefix=FUNC %s
1 ; RUN: llc -enable-unsafe-fp-math -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NSZ -check-prefix=SI -check-prefix=FUNC %s
12
23 ; --------------------------------------------------------------------------------
34 ; fadd tests
67 ; GCN-LABEL: {{^}}v_fneg_add_f32:
78 ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
89 ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
9 ; GCN: v_sub_f32_e64 [[RESULT:v[0-9]+]], -[[A]], [[B]]
10 ; GCN-NEXT: buffer_store_dword [[RESULT]]
10
11 ; GCN-SAFE: v_add_f32_e32 [[ADD:v[0-9]+]], [[B]], [[A]]
12 ; GCN-SAFE: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, [[ADD]]
13
14 ; GCN-NSZ: v_sub_f32_e64 [[RESULT:v[0-9]+]], -[[A]], [[B]]
15 ; GCN-NSZ-NEXT: buffer_store_dword [[RESULT]]
1116 define void @v_fneg_add_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
1217 %tid = call i32 @llvm.amdgcn.workitem.id.x()
1318 %tid.ext = sext i32 %tid to i64
7176 ; GCN-LABEL: {{^}}v_fneg_add_fneg_x_f32:
7277 ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
7378 ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
74 ; GCN: v_subrev_f32_e32 [[ADD:v[0-9]+]], [[B]], [[A]]
75 ; GCN-NEXT: buffer_store_dword [[ADD]]
79
80 ; GCN-SAFE: v_subrev_f32_e32
81 ; GCN-SAFE: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000,
82
83 ; GCN-NSZ: v_subrev_f32_e32 [[ADD:v[0-9]+]], [[B]], [[A]]
84 ; GCN-NSZ-NEXT: buffer_store_dword [[ADD]]
7685 define void @v_fneg_add_fneg_x_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
7786 %tid = call i32 @llvm.amdgcn.workitem.id.x()
7887 %tid.ext = sext i32 %tid to i64
91100 ; GCN-LABEL: {{^}}v_fneg_add_x_fneg_f32:
92101 ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
93102 ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
94 ; GCN: v_subrev_f32_e32 [[ADD:v[0-9]+]], [[A]], [[B]]
95 ; GCN-NEXT: buffer_store_dword [[ADD]]
103
104 ; GCN-SAFE: v_subrev_f32_e32 [[ADD:v[0-9]+]], [[B]], [[A]]
105 ; GCN-SAFE: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, [[ADD]]
106
107 ; GCN-NSZ: v_subrev_f32_e32 [[ADD:v[0-9]+]], [[A]], [[B]]
108 ; GCN-NSZ-NEXT: buffer_store_dword [[ADD]]
96109 define void @v_fneg_add_x_fneg_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
97110 %tid = call i32 @llvm.amdgcn.workitem.id.x()
98111 %tid.ext = sext i32 %tid to i64
111124 ; GCN-LABEL: {{^}}v_fneg_add_fneg_fneg_f32:
112125 ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
113126 ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
114 ; GCN: v_add_f32_e32 [[ADD:v[0-9]+]], [[B]], [[A]]
115 ; GCN-NEXT: buffer_store_dword [[ADD]]
127
128 ; GCN-SAFE: v_sub_f32_e64 [[ADD:v[0-9]+]], -[[A]], [[B]]
129 ; GCN-SAFE: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, [[ADD]]
130
131 ; GCN-NSZ: v_add_f32_e32 [[ADD:v[0-9]+]], [[B]], [[A]]
132 ; GCN-NSZ-NEXT: buffer_store_dword [[ADD]]
116133 define void @v_fneg_add_fneg_fneg_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
117134 %tid = call i32 @llvm.amdgcn.workitem.id.x()
118135 %tid.ext = sext i32 %tid to i64
132149 ; GCN-LABEL: {{^}}v_fneg_add_store_use_fneg_x_f32:
133150 ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
134151 ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
135 ; GCN-DAG: v_xor_b32_e32 [[NEG_A:v[0-9]+]], 0x80000000, [[A]]
136 ; GCN-DAG: v_subrev_f32_e32 [[NEG_ADD:v[0-9]+]], [[B]], [[A]]
137 ; GCN-NEXT: buffer_store_dword [[NEG_ADD]]
138 ; GCN-NEXT: buffer_store_dword [[NEG_A]]
152
153 ; GCN-SAFE: v_bfrev_b32_e32 [[SIGNBIT:v[0-9]+]], 1{{$}}
154 ; GCN-SAFE: v_xor_b32_e32 [[NEG_A:v[0-9]+]], [[A]], [[SIGNBIT]]
155 ; GCN-SAFE: v_subrev_f32_e32 [[ADD:v[0-9]+]], [[A]], [[B]]
156 ; GCN-SAFE: v_xor_b32_e32 [[NEG_ADD:v[0-9]+]], [[ADD]], [[SIGNBIT]]
157
158 ; GCN-NSZ-DAG: v_xor_b32_e32 [[NEG_A:v[0-9]+]], 0x80000000, [[A]]
159 ; GCN-NSZ-DAG: v_subrev_f32_e32 [[NEG_ADD:v[0-9]+]], [[B]], [[A]]
160 ; GCN-NSZ-NEXT: buffer_store_dword [[NEG_ADD]]
161 ; GCN-NSZ-NEXT: buffer_store_dword [[NEG_A]]
139162 define void @v_fneg_add_store_use_fneg_x_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
140163 %tid = call i32 @llvm.amdgcn.workitem.id.x()
141164 %tid.ext = sext i32 %tid to i64
155178 ; GCN-LABEL: {{^}}v_fneg_add_multi_use_fneg_x_f32:
156179 ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
157180 ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
158 ; GCN-DAG: v_subrev_f32_e32 [[NEG_ADD:v[0-9]+]], [[B]], [[A]]
159 ; GCN-DAG: v_mul_f32_e64 [[MUL:v[0-9]+]], -[[A]], s{{[0-9]+}}
160 ; GCN-NEXT: buffer_store_dword [[NEG_ADD]]
161 ; GCN-NEXT: buffer_store_dword [[MUL]]
181
182 ; GCN-SAFE-DAG: v_mul_f32_e64 [[MUL:v[0-9]+]], -[[A]], s{{[0-9]+}}
183 ; GCN-SAFE-DAG: v_subrev_f32_e32 [[ADD:v[0-9]+]], [[A]], [[B]]
184 ; GCN-SAFE: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, [[ADD]]
185
186 ; GCN-NSZ-DAG: v_subrev_f32_e32 [[NEG_ADD:v[0-9]+]], [[B]], [[A]]
187 ; GCN-NSZ-DAG: v_mul_f32_e64 [[MUL:v[0-9]+]], -[[A]], s{{[0-9]+}}
188 ; GCN-NSZ-NEXT: buffer_store_dword [[NEG_ADD]]
189 ; GCN-NSZ-NEXT: buffer_store_dword [[MUL]]
162190 define void @v_fneg_add_multi_use_fneg_x_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float %c) #0 {
163191 %tid = call i32 @llvm.amdgcn.workitem.id.x()
164192 %tid.ext = sext i32 %tid to i64
361389 ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
362390 ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
363391 ; GCN: {{buffer|flat}}_load_dword [[C:v[0-9]+]]
364 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[A]], -[[B]], -[[C]]
365 ; GCN-NEXT: buffer_store_dword [[RESULT]]
392
393 ; GCN-SAFE: v_fma_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], [[C]]
394 ; GCN-SAFE: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, [[RESULT]]
395
396 ; GCN-NSZ: v_fma_f32 [[RESULT:v[0-9]+]], [[A]], -[[B]], -[[C]]
397 ; GCN-NSZ-NEXT: buffer_store_dword [[RESULT]]
366398 define void @v_fneg_fma_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float addrspace(1)* %c.ptr) #0 {
367399 %tid = call i32 @llvm.amdgcn.workitem.id.x()
368400 %tid.ext = sext i32 %tid to i64
435467 ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
436468 ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
437469 ; GCN: {{buffer|flat}}_load_dword [[C:v[0-9]+]]
438 ; GCN: v_fma_f32 [[FMA:v[0-9]+]], [[A]], [[B]], -[[C]]
439 ; GCN-NEXT: buffer_store_dword [[FMA]]
470
471 ; GCN-SAFE: v_fma_f32 [[FMA:v[0-9]+]], -[[A]], [[B]], [[C]]
472 ; GCN-SAFE: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, [[FMA]]
473
474 ; GCN-NSZ: v_fma_f32 [[FMA:v[0-9]+]], [[A]], [[B]], -[[C]]
475 ; GCN-NSZ-NEXT: buffer_store_dword [[FMA]]
440476 define void @v_fneg_fma_fneg_x_y_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float addrspace(1)* %c.ptr) #0 {
441477 %tid = call i32 @llvm.amdgcn.workitem.id.x()
442478 %tid.ext = sext i32 %tid to i64
458494 ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
459495 ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
460496 ; GCN: {{buffer|flat}}_load_dword [[C:v[0-9]+]]
461 ; GCN: v_fma_f32 [[FMA:v[0-9]+]], [[A]], [[B]], -[[C]]
462 ; GCN-NEXT: buffer_store_dword [[FMA]]
497
498 ; GCN-SAFE: v_fma_f32 [[FMA:v[0-9]+]], [[A]], -[[B]], [[C]]
499 ; GCN-SAFE: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, [[FMA]]
500
501 ; GCN-NSZ: v_fma_f32 [[FMA:v[0-9]+]], [[A]], [[B]], -[[C]]
502 ; GCN-NSZ-NEXT: buffer_store_dword [[FMA]]
463503 define void @v_fneg_fma_x_fneg_y_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float addrspace(1)* %c.ptr) #0 {
464504 %tid = call i32 @llvm.amdgcn.workitem.id.x()
465505 %tid.ext = sext i32 %tid to i64
481521 ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
482522 ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
483523 ; GCN: {{buffer|flat}}_load_dword [[C:v[0-9]+]]
484 ; GCN: v_fma_f32 [[FMA:v[0-9]+]], [[A]], -[[B]], -[[C]]
485 ; GCN-NEXT: buffer_store_dword [[FMA]]
524
525 ; GCN-SAFE: v_fma_f32 [[FMA:v[0-9]+]], -[[A]], -[[B]], [[C]]
526 ; GCN-SAFE: v_xor_b32_e32 v{{[[0-9]+}}, 0x80000000, [[FMA]]
527
528 ; GCN-NSZ: v_fma_f32 [[FMA:v[0-9]+]], [[A]], -[[B]], -[[C]]
529 ; GCN-NSZ-NEXT: buffer_store_dword [[FMA]]
486530 define void @v_fneg_fma_fneg_fneg_y_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float addrspace(1)* %c.ptr) #0 {
487531 %tid = call i32 @llvm.amdgcn.workitem.id.x()
488532 %tid.ext = sext i32 %tid to i64
505549 ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
506550 ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
507551 ; GCN: {{buffer|flat}}_load_dword [[C:v[0-9]+]]
508 ; GCN: v_fma_f32 [[FMA:v[0-9]+]], [[A]], [[B]], [[C]]
509 ; GCN-NEXT: buffer_store_dword [[FMA]]
552
553 ; GCN-SAFE: v_fma_f32 [[FMA:v[0-9]+]], -[[A]], [[B]], -[[C]]
554 ; GCN-SAFE: v_xor_b32_e32 v{{[[0-9]+}}, 0x80000000, [[FMA]]
555
556 ; GCN-NSZ: v_fma_f32 [[FMA:v[0-9]+]], [[A]], [[B]], [[C]]
557 ; GCN-NSZ-NEXT: buffer_store_dword [[FMA]]
510558 define void @v_fneg_fma_fneg_x_fneg_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float addrspace(1)* %c.ptr) #0 {
511559 %tid = call i32 @llvm.amdgcn.workitem.id.x()
512560 %tid.ext = sext i32 %tid to i64
529577 ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
530578 ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
531579 ; GCN: {{buffer|flat}}_load_dword [[C:v[0-9]+]]
532 ; GCN: v_fma_f32 [[FMA:v[0-9]+]], [[A]], -[[B]], [[C]]
533 ; GCN-NEXT: buffer_store_dword [[FMA]]
580
581 ; GCN-NSZ-SAFE: v_fma_f32 [[FMA:v[0-9]+]], [[A]], [[B]], -[[C]]
582 ; GCN-NSZ-SAFE: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, [[FMA]]
583
584 ; GCN-NSZ: v_fma_f32 [[FMA:v[0-9]+]], [[A]], -[[B]], [[C]]
585 ; GCN-NSZ-NEXT: buffer_store_dword [[FMA]]
534586 define void @v_fneg_fma_x_y_fneg_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float addrspace(1)* %c.ptr) #0 {
535587 %tid = call i32 @llvm.amdgcn.workitem.id.x()
536588 %tid.ext = sext i32 %tid to i64
552604 ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
553605 ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
554606 ; GCN: {{buffer|flat}}_load_dword [[C:v[0-9]+]]
555 ; GCN-DAG: v_xor_b32_e32 [[NEG_A:v[0-9]+]], 0x80000000, [[A]]
556 ; GCN-DAG: v_fma_f32 [[FMA:v[0-9]+]], [[A]], [[B]], -[[C]]
557 ; GCN-NEXT: buffer_store_dword [[FMA]]
558 ; GCN-NEXT: buffer_store_dword [[NEG_A]]
607
608 ; GCN-SAFE: v_xor_b32
609 ; GCN-SAFE: v_fma_f32 [[FMA:v[0-9]+]], -[[A]],
610 ; GCN-SAFE: v_xor_b32
611
612 ; GCN-NSZ-DAG: v_xor_b32_e32 [[NEG_A:v[0-9]+]], 0x80000000, [[A]]
613 ; GCN-NSZ-DAG: v_fma_f32 [[FMA:v[0-9]+]], [[A]], [[B]], -[[C]]
614 ; GCN-NSZ-NEXT: buffer_store_dword [[FMA]]
615 ; GCN-NSZ-NEXT: buffer_store_dword [[NEG_A]]
559616 define void @v_fneg_fma_store_use_fneg_x_y_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float addrspace(1)* %c.ptr) #0 {
560617 %tid = call i32 @llvm.amdgcn.workitem.id.x()
561618 %tid.ext = sext i32 %tid to i64
578635 ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
579636 ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
580637 ; GCN: {{buffer|flat}}_load_dword [[C:v[0-9]+]]
581 ; GCN-DAG: v_mul_f32_e64 [[MUL:v[0-9]+]], -[[A]], s{{[0-9]+}}
582 ; GCN-DAG: v_fma_f32 [[NEG_FMA:v[0-9]+]], [[A]], [[B]], -[[C]]
583 ; GCN-NEXT: buffer_store_dword [[NEG_FMA]]
584 ; GCN-NEXT: buffer_store_dword [[MUL]]
638
639 ; GCN: v_mul_f32_e64 [[MUL:v[0-9]+]], -[[A]], s{{[0-9]+}}
640 ; GCN-SAFE: v_fma_f32 [[FMA:v[0-9]+]]
641 ; GCN-SAFE: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, [[FMA]]
642
643 ; GCN-NSZ-DAG: v_fma_f32 [[NEG_FMA:v[0-9]+]], [[A]], [[B]], -[[C]]
644 ; GCN-NSZ-NEXT: buffer_store_dword [[NEG_FMA]]
645 ; GCN-NSZ-NEXT: buffer_store_dword [[MUL]]
585646 define void @v_fneg_fma_multi_use_fneg_x_y_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float addrspace(1)* %c.ptr, float %d) #0 {
586647 %tid = call i32 @llvm.amdgcn.workitem.id.x()
587648 %tid.ext = sext i32 %tid to i64
609670 ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
610671 ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
611672 ; GCN: {{buffer|flat}}_load_dword [[C:v[0-9]+]]
612 ; GCN: v_mad_f32 [[RESULT:v[0-9]+]], [[A]], -[[B]], -[[C]]
613 ; GCN-NEXT: buffer_store_dword [[RESULT]]
673
674 ; GCN-SAFE: v_mac_f32_e32 [[C]], [[B]], [[A]]
675 ; GCN-SAFE: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, [[C]]
676
677 ; GCN-NSZ: v_mad_f32 [[RESULT:v[0-9]+]], [[A]], -[[B]], -[[C]]
678 ; GCN-NSZ-NEXT: buffer_store_dword [[RESULT]]
614679 define void @v_fneg_fmad_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float addrspace(1)* %c.ptr) #0 {
615680 %tid = call i32 @llvm.amdgcn.workitem.id.x()
616681 %tid.ext = sext i32 %tid to i64
None ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
1 ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
0 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
1 ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
22
33 ; GCN-LABEL: {{^}}add_select_fabs_fabs_f32:
44 ; GCN: buffer_load_dword [[X:v[0-9]+]]