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ARM: Allow __fp16 as a function arg or return type for AArch64 ACLE 2.0 allows __fp16 to be used as a function argument or return type. This enables this for AArch64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212812 91177308-0d34-0410-b5e6-96231b3b80d8 Oliver Stannard 5 years ago
4 changed file(s) with 26 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
269269
270270 EVT OrigVT = VT;
271271 EVT SVT = VT;
272 while (SVT != MVT::f32) {
272 while (SVT != MVT::f32 && SVT != MVT::f16) {
273273 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
274274 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
275275 // Only do this if the target has a native EXTLOAD instruction from
5353
5454 CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7],
5555 [W0, W1, W2, W3, W4, W5, W6, W7]>>,
56 CCIfType<[f16], CCAssignToRegWithShadow<[H0, H1, H2, H3, H4, H5, H6, H7],
57 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
5658 CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7],
5759 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
5860 CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
6466 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
6567
6668 // If more than will fit in registers, pass them on the stack instead.
67 CCIfType<[i1, i8, i16], CCAssignToStack<8, 8>>,
69 CCIfType<[i1, i8, i16, f16], CCAssignToStack<8, 8>>,
6870 CCIfType<[i32, f32], CCAssignToStack<8, 8>>,
6971 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8],
7072 CCAssignToStack<8, 8>>,
8789 [X0, X1, X2, X3, X4, X5, X6, X7]>>,
8890 CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7],
8991 [W0, W1, W2, W3, W4, W5, W6, W7]>>,
92 CCIfType<[f16], CCAssignToRegWithShadow<[H0, H1, H2, H3, H4, H5, H6, H7],
93 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
9094 CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7],
9195 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
9296 CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
128132
129133 CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7],
130134 [W0, W1, W2, W3, W4, W5, W6, W7]>>,
135 CCIfType<[f16], CCAssignToRegWithShadow<[H0, H1, H2, H3, H4, H5, H6, H7],
136 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
131137 CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7],
132138 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
133139 CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
140146
141147 // If more than will fit in registers, pass them on the stack instead.
142148 CCIf<"ValVT == MVT::i1 || ValVT == MVT::i8", CCAssignToStack<1, 1>>,
143 CCIf<"ValVT == MVT::i16", CCAssignToStack<2, 2>>,
149 CCIf<"ValVT == MVT::i16 || ValVT == MVT::f16", CCAssignToStack<2, 2>>,
144150 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
145151 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8],
146152 CCAssignToStack<8, 8>>,
153159
154160 // Handle all scalar types as either i64 or f64.
155161 CCIfType<[i8, i16, i32], CCPromoteToType>,
156 CCIfType<[f32], CCPromoteToType>,
162 CCIfType<[f16, f32], CCPromoteToType>,
157163
158164 // Everything is on the stack.
159165 // i128 is split to two i64s, and its stack alignment is 16 bytes.
17101710 RC = &AArch64::GPR32RegClass;
17111711 else if (RegVT == MVT::i64)
17121712 RC = &AArch64::GPR64RegClass;
1713 else if (RegVT == MVT::f16)
1714 RC = &AArch64::FPR16RegClass;
17131715 else if (RegVT == MVT::f32)
17141716 RC = &AArch64::FPR32RegClass;
17151717 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
108108 ; CHECK: ldr {{q[0-9]+}}, [sp]
109109 ret <2 x double> %varg_stack;
110110 }
111
112 ; Check that f16 can be passed and returned (ACLE 2.0 extension)
113 define half @test_half(float, half %arg) {
114 ; CHECK-LABEL: test_half:
115 ; CHECK: mov v0.16b, v{{[0-9]+}}.16b
116 ret half %arg;
117 }
118
119 ; Check that f16 constants are materialized correctly
120 define half @test_half_const() {
121 ; CHECK-LABEL: test_half_const:
122 ; CHECK: ldr h0, [x{{[0-9]+}}, :lo12:{{.*}}]
123 ret half 0xH4248
124 }