llvm.org GIT mirror llvm / cadff44
Delete unused EmitByteSwap method Implement mul/div/rem constant expressions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9424 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 16 years ago
2 changed file(s) with 88 addition(s) and 100 deletion(s). Raw diff Collapse all Expand all
191191 ///
192192 void promote32(unsigned targetReg, const ValueRecord &VR);
193193
194 /// EmitByteSwap - Byteswap SrcReg into DestReg.
195 ///
196 void EmitByteSwap(unsigned DestReg, unsigned SrcReg, unsigned Class);
197
198194 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
199195 /// constant expression GEP support.
200196 ///
213209 MachineBasicBlock::iterator &IP,
214210 Value *Op0, Value *Op1,
215211 unsigned OperatorClass, unsigned TargetReg);
212
213 void emitDivRemOperation(MachineBasicBlock *BB,
214 MachineBasicBlock::iterator &IP,
215 unsigned Op0Reg, unsigned Op1Reg, bool isDiv,
216 const Type *Ty, unsigned TargetReg);
216217
217218 /// emitSetCCOperation - Common code shared between visitSetCondInst and
218219 /// constant expression support.
353354 emitSimpleBinaryOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
354355 Class, R);
355356 return;
357
358 case Instruction::Mul: {
359 unsigned Op0Reg = getReg(CE->getOperand(0), MBB, IP);
360 unsigned Op1Reg = getReg(CE->getOperand(1), MBB, IP);
361 doMultiply(MBB, IP, R, CE->getType(), Op0Reg, Op1Reg);
362 return;
363 }
364 case Instruction::Div:
365 case Instruction::Rem: {
366 unsigned Op0Reg = getReg(CE->getOperand(0), MBB, IP);
367 unsigned Op1Reg = getReg(CE->getOperand(1), MBB, IP);
368 emitDivRemOperation(MBB, IP, Op0Reg, Op1Reg,
369 CE->getOpcode() == Instruction::Div,
370 CE->getType(), R);
371 return;
372 }
356373
357374 case Instruction::SetNE:
358375 case Instruction::SetEQ:
13381355 /// instructions work differently for signed and unsigned operands.
13391356 ///
13401357 void ISel::visitDivRem(BinaryOperator &I) {
1341 unsigned Class = getClass(I.getType());
1342 unsigned Op0Reg, Op1Reg, ResultReg = getReg(I);
1343
1358 unsigned Op0Reg = getReg(I.getOperand(0));
1359 unsigned Op1Reg = getReg(I.getOperand(1));
1360 unsigned ResultReg = getReg(I);
1361
1362 MachineBasicBlock::iterator IP = BB->end();
1363 emitDivRemOperation(BB, IP, Op0Reg, Op1Reg, I.getOpcode() == Instruction::Div,
1364 I.getType(), ResultReg);
1365 }
1366
1367 void ISel::emitDivRemOperation(MachineBasicBlock *BB,
1368 MachineBasicBlock::iterator &IP,
1369 unsigned Op0Reg, unsigned Op1Reg, bool isDiv,
1370 const Type *Ty, unsigned ResultReg) {
1371 unsigned Class = getClass(Ty);
13441372 switch (Class) {
13451373 case cFP: // Floating point divide
1346 if (I.getOpcode() == Instruction::Div) {
1347 Op0Reg = getReg(I.getOperand(0));
1348 Op1Reg = getReg(I.getOperand(1));
1374 if (isDiv) {
13491375 BuildMI(BB, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
13501376 } else { // Floating point remainder...
13511377 MachineInstr *TheCall =
13521378 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true);
13531379 std::vector Args;
1354 Args.push_back(ValueRecord(I.getOperand(0)));
1355 Args.push_back(ValueRecord(I.getOperand(1)));
1380 Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy));
1381 Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy));
13561382 doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args);
13571383 }
13581384 return;
13601386 static const char *FnName[] =
13611387 { "__moddi3", "__divdi3", "__umoddi3", "__udivdi3" };
13621388
1363 unsigned NameIdx = I.getType()->isUnsigned()*2;
1364 NameIdx += I.getOpcode() == Instruction::Div;
1389 unsigned NameIdx = Ty->isUnsigned()*2 + isDiv;
13651390 MachineInstr *TheCall =
13661391 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol(FnName[NameIdx], true);
13671392
13681393 std::vector Args;
1369 Args.push_back(ValueRecord(I.getOperand(0)));
1370 Args.push_back(ValueRecord(I.getOperand(1)));
1394 Args.push_back(ValueRecord(Op0Reg, Type::LongTy));
1395 Args.push_back(ValueRecord(Op1Reg, Type::LongTy));
13711396 doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args);
13721397 return;
13731398 }
13871412 { X86::IDIVr8, X86::IDIVr16, X86::IDIVr32, 0 }, // Signed division
13881413 };
13891414
1390 bool isSigned = I.getType()->isSigned();
1415 bool isSigned = Ty->isSigned();
13911416 unsigned Reg = Regs[Class];
13921417 unsigned ExtReg = ExtRegs[Class];
13931418
13941419 // Put the first operand into one of the A registers...
1395 Op0Reg = getReg(I.getOperand(0));
13961420 BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
13971421
13981422 if (isSigned) {
13991423 // Emit a sign extension instruction...
1400 unsigned ShiftResult = makeAnotherReg(I.getType());
1424 unsigned ShiftResult = makeAnotherReg(Ty);
14011425 BuildMI(BB, SarOpcode[Class], 2, ShiftResult).addReg(Op0Reg).addZImm(31);
14021426 BuildMI(BB, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult);
14031427 } else {
14061430 }
14071431
14081432 // Emit the appropriate divide or remainder instruction...
1409 Op1Reg = getReg(I.getOperand(1));
14101433 BuildMI(BB, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
14111434
14121435 // Figure out which register we want to pick the result out of...
1413 unsigned DestReg = (I.getOpcode() == Instruction::Div) ? Reg : ExtReg;
1436 unsigned DestReg = isDiv ? Reg : ExtReg;
14141437
14151438 // Put the result into the destination register...
14161439 BuildMI(BB, MovOpcode[Class], 1, ResultReg).addReg(DestReg);
15391562
15401563 const unsigned *Opc = NonConstantOperand[isLeftShift*2+isSigned];
15411564 BuildMI(BB, Opc[Class], 1, DestReg).addReg(SrcReg);
1542 }
1543 }
1544
1545
1546 /// EmitByteSwap - Byteswap SrcReg into DestReg.
1547 ///
1548 void ISel::EmitByteSwap(unsigned DestReg, unsigned SrcReg, unsigned Class) {
1549 // Emit the byte swap instruction...
1550 switch (Class) {
1551 case cByte:
1552 // No byteswap necessary for 8 bit value...
1553 BuildMI(BB, X86::MOVrr8, 1, DestReg).addReg(SrcReg);
1554 break;
1555 case cInt:
1556 // Use the 32 bit bswap instruction to do a 32 bit swap...
1557 BuildMI(BB, X86::BSWAPr32, 1, DestReg).addReg(SrcReg);
1558 break;
1559
1560 case cShort:
1561 // For 16 bit we have to use an xchg instruction, because there is no
1562 // 16-bit bswap. XCHG is necessarily not in SSA form, so we force things
1563 // into AX to do the xchg.
1564 //
1565 BuildMI(BB, X86::MOVrr16, 1, X86::AX).addReg(SrcReg);
1566 BuildMI(BB, X86::XCHGrr8, 2).addReg(X86::AL, MOTy::UseAndDef)
1567 .addReg(X86::AH, MOTy::UseAndDef);
1568 BuildMI(BB, X86::MOVrr16, 1, DestReg).addReg(X86::AX);
1569 break;
1570 default: assert(0 && "Cannot byteswap this class!");
15711565 }
15721566 }
15731567
191191 ///
192192 void promote32(unsigned targetReg, const ValueRecord &VR);
193193
194 /// EmitByteSwap - Byteswap SrcReg into DestReg.
195 ///
196 void EmitByteSwap(unsigned DestReg, unsigned SrcReg, unsigned Class);
197
198194 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
199195 /// constant expression GEP support.
200196 ///
213209 MachineBasicBlock::iterator &IP,
214210 Value *Op0, Value *Op1,
215211 unsigned OperatorClass, unsigned TargetReg);
212
213 void emitDivRemOperation(MachineBasicBlock *BB,
214 MachineBasicBlock::iterator &IP,
215 unsigned Op0Reg, unsigned Op1Reg, bool isDiv,
216 const Type *Ty, unsigned TargetReg);
216217
217218 /// emitSetCCOperation - Common code shared between visitSetCondInst and
218219 /// constant expression support.
353354 emitSimpleBinaryOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
354355 Class, R);
355356 return;
357
358 case Instruction::Mul: {
359 unsigned Op0Reg = getReg(CE->getOperand(0), MBB, IP);
360 unsigned Op1Reg = getReg(CE->getOperand(1), MBB, IP);
361 doMultiply(MBB, IP, R, CE->getType(), Op0Reg, Op1Reg);
362 return;
363 }
364 case Instruction::Div:
365 case Instruction::Rem: {
366 unsigned Op0Reg = getReg(CE->getOperand(0), MBB, IP);
367 unsigned Op1Reg = getReg(CE->getOperand(1), MBB, IP);
368 emitDivRemOperation(MBB, IP, Op0Reg, Op1Reg,
369 CE->getOpcode() == Instruction::Div,
370 CE->getType(), R);
371 return;
372 }
356373
357374 case Instruction::SetNE:
358375 case Instruction::SetEQ:
13381355 /// instructions work differently for signed and unsigned operands.
13391356 ///
13401357 void ISel::visitDivRem(BinaryOperator &I) {
1341 unsigned Class = getClass(I.getType());
1342 unsigned Op0Reg, Op1Reg, ResultReg = getReg(I);
1343
1358 unsigned Op0Reg = getReg(I.getOperand(0));
1359 unsigned Op1Reg = getReg(I.getOperand(1));
1360 unsigned ResultReg = getReg(I);
1361
1362 MachineBasicBlock::iterator IP = BB->end();
1363 emitDivRemOperation(BB, IP, Op0Reg, Op1Reg, I.getOpcode() == Instruction::Div,
1364 I.getType(), ResultReg);
1365 }
1366
1367 void ISel::emitDivRemOperation(MachineBasicBlock *BB,
1368 MachineBasicBlock::iterator &IP,
1369 unsigned Op0Reg, unsigned Op1Reg, bool isDiv,
1370 const Type *Ty, unsigned ResultReg) {
1371 unsigned Class = getClass(Ty);
13441372 switch (Class) {
13451373 case cFP: // Floating point divide
1346 if (I.getOpcode() == Instruction::Div) {
1347 Op0Reg = getReg(I.getOperand(0));
1348 Op1Reg = getReg(I.getOperand(1));
1374 if (isDiv) {
13491375 BuildMI(BB, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
13501376 } else { // Floating point remainder...
13511377 MachineInstr *TheCall =
13521378 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true);
13531379 std::vector Args;
1354 Args.push_back(ValueRecord(I.getOperand(0)));
1355 Args.push_back(ValueRecord(I.getOperand(1)));
1380 Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy));
1381 Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy));
13561382 doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args);
13571383 }
13581384 return;
13601386 static const char *FnName[] =
13611387 { "__moddi3", "__divdi3", "__umoddi3", "__udivdi3" };
13621388
1363 unsigned NameIdx = I.getType()->isUnsigned()*2;
1364 NameIdx += I.getOpcode() == Instruction::Div;
1389 unsigned NameIdx = Ty->isUnsigned()*2 + isDiv;
13651390 MachineInstr *TheCall =
13661391 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol(FnName[NameIdx], true);
13671392
13681393 std::vector Args;
1369 Args.push_back(ValueRecord(I.getOperand(0)));
1370 Args.push_back(ValueRecord(I.getOperand(1)));
1394 Args.push_back(ValueRecord(Op0Reg, Type::LongTy));
1395 Args.push_back(ValueRecord(Op1Reg, Type::LongTy));
13711396 doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args);
13721397 return;
13731398 }
13871412 { X86::IDIVr8, X86::IDIVr16, X86::IDIVr32, 0 }, // Signed division
13881413 };
13891414
1390 bool isSigned = I.getType()->isSigned();
1415 bool isSigned = Ty->isSigned();
13911416 unsigned Reg = Regs[Class];
13921417 unsigned ExtReg = ExtRegs[Class];
13931418
13941419 // Put the first operand into one of the A registers...
1395 Op0Reg = getReg(I.getOperand(0));
13961420 BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
13971421
13981422 if (isSigned) {
13991423 // Emit a sign extension instruction...
1400 unsigned ShiftResult = makeAnotherReg(I.getType());
1424 unsigned ShiftResult = makeAnotherReg(Ty);
14011425 BuildMI(BB, SarOpcode[Class], 2, ShiftResult).addReg(Op0Reg).addZImm(31);
14021426 BuildMI(BB, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult);
14031427 } else {
14061430 }
14071431
14081432 // Emit the appropriate divide or remainder instruction...
1409 Op1Reg = getReg(I.getOperand(1));
14101433 BuildMI(BB, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
14111434
14121435 // Figure out which register we want to pick the result out of...
1413 unsigned DestReg = (I.getOpcode() == Instruction::Div) ? Reg : ExtReg;
1436 unsigned DestReg = isDiv ? Reg : ExtReg;
14141437
14151438 // Put the result into the destination register...
14161439 BuildMI(BB, MovOpcode[Class], 1, ResultReg).addReg(DestReg);
15391562
15401563 const unsigned *Opc = NonConstantOperand[isLeftShift*2+isSigned];
15411564 BuildMI(BB, Opc[Class], 1, DestReg).addReg(SrcReg);
1542 }
1543 }
1544
1545
1546 /// EmitByteSwap - Byteswap SrcReg into DestReg.
1547 ///
1548 void ISel::EmitByteSwap(unsigned DestReg, unsigned SrcReg, unsigned Class) {
1549 // Emit the byte swap instruction...
1550 switch (Class) {
1551 case cByte:
1552 // No byteswap necessary for 8 bit value...
1553 BuildMI(BB, X86::MOVrr8, 1, DestReg).addReg(SrcReg);
1554 break;
1555 case cInt:
1556 // Use the 32 bit bswap instruction to do a 32 bit swap...
1557 BuildMI(BB, X86::BSWAPr32, 1, DestReg).addReg(SrcReg);
1558 break;
1559
1560 case cShort:
1561 // For 16 bit we have to use an xchg instruction, because there is no
1562 // 16-bit bswap. XCHG is necessarily not in SSA form, so we force things
1563 // into AX to do the xchg.
1564 //
1565 BuildMI(BB, X86::MOVrr16, 1, X86::AX).addReg(SrcReg);
1566 BuildMI(BB, X86::XCHGrr8, 2).addReg(X86::AL, MOTy::UseAndDef)
1567 .addReg(X86::AH, MOTy::UseAndDef);
1568 BuildMI(BB, X86::MOVrr16, 1, DestReg).addReg(X86::AX);
1569 break;
1570 default: assert(0 && "Cannot byteswap this class!");
15711565 }
15721566 }
15731567