llvm.org GIT mirror llvm / caa9ba2
Remove the rest of the nonexistent 64-bit AVX instructions. Bruno, please review. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113014 91177308-0d34-0410-b5e6-96231b3b80d8 Dale Johannesen 10 years ago
2 changed file(s) with 76 addition(s) and 175 deletion(s). Raw diff Collapse all Expand all
35913591
35923592 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
35933593 multiclass SS3I_binop_rm_int opc, string OpcodeStr,
3594 PatFrag mem_frag64, PatFrag mem_frag128,
3595 Intrinsic IntId64, Intrinsic IntId128,
3594 PatFrag mem_frag128, Intrinsic IntId128,
35963595 bit Is2Addr = 1> {
3597 let isCommutable = 1 in
3598 def rr64 : SS38I
3599 (ins VR64:$src1, VR64:$src2),
3600 !if(Is2Addr,
3601 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3602 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3603 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]>;
3604 def rm64 : SS38I
3605 (ins VR64:$src1, i64mem:$src2),
3606 !if(Is2Addr,
3607 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3608 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3609 [(set VR64:$dst,
3610 (IntId64 VR64:$src1,
3611 (bitconvert (memopv8i8 addr:$src2))))]>;
3612
36133596 let isCommutable = 1 in
36143597 def rr128 : SS38I
36153598 (ins VR128:$src1, VR128:$src2),
36273610 (IntId128 VR128:$src1,
36283611 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
36293612 }
3613 multiclass SS3I_binop_rm_int_mm opc, string OpcodeStr,
3614 PatFrag mem_frag64, Intrinsic IntId64> {
3615 let isCommutable = 1 in
3616 def rr64 : SS38I
3617 (ins VR64:$src1, VR64:$src2),
3618 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3619 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]>;
3620 def rm64 : SS38I
3621 (ins VR64:$src1, i64mem:$src2),
3622 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3623 [(set VR64:$dst,
3624 (IntId64 VR64:$src1,
3625 (bitconvert (memopv8i8 addr:$src2))))]>;
3626 }
36303627
36313628 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
36323629 let isCommutable = 0 in {
3633 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv4i16, memopv8i16,
3634 int_x86_ssse3_phadd_w,
3630 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv8i16,
36353631 int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
3636 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv2i32, memopv4i32,
3637 int_x86_ssse3_phadd_d,
3632 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv4i32,
36383633 int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
3639 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv4i16, memopv8i16,
3640 int_x86_ssse3_phadd_sw,
3634 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv8i16,
36413635 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
3642 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv4i16, memopv8i16,
3643 int_x86_ssse3_phsub_w,
3636 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv8i16,
36443637 int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
3645 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv2i32, memopv4i32,
3646 int_x86_ssse3_phsub_d,
3638 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv4i32,
36473639 int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
3648 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv4i16, memopv8i16,
3649 int_x86_ssse3_phsub_sw,
3640 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv8i16,
36503641 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
3651 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv8i8, memopv16i8,
3652 int_x86_ssse3_pmadd_ub_sw,
3642 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv16i8,
36533643 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
3654 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv8i8, memopv16i8,
3655 int_x86_ssse3_pshuf_b,
3644 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv16i8,
36563645 int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
3657 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv8i8, memopv16i8,
3658 int_x86_ssse3_psign_b,
3646 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv16i8,
36593647 int_x86_ssse3_psign_b_128, 0>, VEX_4V;
3660 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv4i16, memopv8i16,
3661 int_x86_ssse3_psign_w,
3648 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv8i16,
36623649 int_x86_ssse3_psign_w_128, 0>, VEX_4V;
3663 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv2i32, memopv4i32,
3664 int_x86_ssse3_psign_d,
3650 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv4i32,
36653651 int_x86_ssse3_psign_d_128, 0>, VEX_4V;
36663652 }
3667 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv4i16, memopv8i16,
3668 int_x86_ssse3_pmul_hr_sw,
3653 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv8i16,
36693654 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
36703655 }
36713656
36723657 // None of these have i8 immediate fields.
36733658 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
36743659 let isCommutable = 0 in {
3675 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv4i16, memopv8i16,
3676 int_x86_ssse3_phadd_w,
3677 int_x86_ssse3_phadd_w_128>;
3678 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv2i32, memopv4i32,
3679 int_x86_ssse3_phadd_d,
3680 int_x86_ssse3_phadd_d_128>;
3681 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv4i16, memopv8i16,
3682 int_x86_ssse3_phadd_sw,
3683 int_x86_ssse3_phadd_sw_128>;
3684 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv4i16, memopv8i16,
3685 int_x86_ssse3_phsub_w,
3686 int_x86_ssse3_phsub_w_128>;
3687 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv2i32, memopv4i32,
3688 int_x86_ssse3_phsub_d,
3689 int_x86_ssse3_phsub_d_128>;
3690 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv4i16, memopv8i16,
3691 int_x86_ssse3_phsub_sw,
3692 int_x86_ssse3_phsub_sw_128>;
3693 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv8i8, memopv16i8,
3694 int_x86_ssse3_pmadd_ub_sw,
3695 int_x86_ssse3_pmadd_ub_sw_128>;
3696 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv8i8, memopv16i8,
3697 int_x86_ssse3_pshuf_b,
3698 int_x86_ssse3_pshuf_b_128>;
3699 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv8i8, memopv16i8,
3700 int_x86_ssse3_psign_b,
3701 int_x86_ssse3_psign_b_128>;
3702 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv4i16, memopv8i16,
3703 int_x86_ssse3_psign_w,
3704 int_x86_ssse3_psign_w_128>;
3705 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv2i32, memopv4i32,
3706 int_x86_ssse3_psign_d,
3707 int_x86_ssse3_psign_d_128>;
3708 }
3709 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv4i16, memopv8i16,
3710 int_x86_ssse3_pmul_hr_sw,
3711 int_x86_ssse3_pmul_hr_sw_128>;
3660 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv8i16,
3661 int_x86_ssse3_phadd_w_128>,
3662 SS3I_binop_rm_int_mm<0x01, "phaddw", memopv4i16,
3663 int_x86_ssse3_phadd_w>;
3664 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv4i32,
3665 int_x86_ssse3_phadd_d_128>,
3666 SS3I_binop_rm_int_mm<0x02, "phaddd", memopv2i32,
3667 int_x86_ssse3_phadd_d>;
3668 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv8i16,
3669 int_x86_ssse3_phadd_sw_128>,
3670 SS3I_binop_rm_int_mm<0x03, "phaddsw", memopv4i16,
3671 int_x86_ssse3_phadd_sw>;
3672 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv8i16,
3673 int_x86_ssse3_phsub_w_128>,
3674 SS3I_binop_rm_int_mm<0x05, "phsubw", memopv4i16,
3675 int_x86_ssse3_phsub_w>;
3676 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv4i32,
3677 int_x86_ssse3_phsub_d_128>,
3678 SS3I_binop_rm_int_mm<0x06, "phsubd", memopv2i32,
3679 int_x86_ssse3_phsub_d>;
3680 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv8i16,
3681 int_x86_ssse3_phsub_sw_128>,
3682 SS3I_binop_rm_int_mm<0x07, "phsubsw", memopv4i16,
3683 int_x86_ssse3_phsub_sw>;
3684 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv16i8,
3685 int_x86_ssse3_pmadd_ub_sw_128>,
3686 SS3I_binop_rm_int_mm<0x04, "pmaddubsw", memopv8i8,
3687 int_x86_ssse3_pmadd_ub_sw>;
3688 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv8i8,
3689 int_x86_ssse3_pshuf_b_128>,
3690 SS3I_binop_rm_int_mm<0x00, "pshufb", memopv8i8,
3691 int_x86_ssse3_pshuf_b>;
3692 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv16i8,
3693 int_x86_ssse3_psign_b_128>,
3694 SS3I_binop_rm_int_mm<0x08, "psignb", memopv8i8,
3695 int_x86_ssse3_psign_b>;
3696 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv8i16,
3697 int_x86_ssse3_psign_w_128>,
3698 SS3I_binop_rm_int_mm<0x09, "psignw", memopv4i16,
3699 int_x86_ssse3_psign_w>;
3700 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv4i32,
3701 int_x86_ssse3_psign_d_128>,
3702 SS3I_binop_rm_int_mm<0x0A, "psignd", memopv2i32,
3703 int_x86_ssse3_psign_d>;
3704 }
3705 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv8i16,
3706 int_x86_ssse3_pmul_hr_sw_128>,
3707 SS3I_binop_rm_int_mm<0x0B, "pmulhrsw", memopv4i16,
3708 int_x86_ssse3_pmul_hr_sw>;
37123709 }
37133710
37143711 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
17381738 declare <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16>) nounwind readnone
17391739
17401740
1741 define <2 x i32> @test_x86_ssse3_phadd_d(<2 x i32> %a0, <2 x i32> %a1) {
1742 ; CHECK: vphaddd
1743 %res = call <2 x i32> @llvm.x86.ssse3.phadd.d(<2 x i32> %a0, <2 x i32> %a1) ; <<2 x i32>> [#uses=1]
1744 ret <2 x i32> %res
1745 }
1746 declare <2 x i32> @llvm.x86.ssse3.phadd.d(<2 x i32>, <2 x i32>) nounwind readnone
1747
1748
17491741 define <4 x i32> @test_x86_ssse3_phadd_d_128(<4 x i32> %a0, <4 x i32> %a1) {
17501742 ; CHECK: vphaddd
17511743 %res = call <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
17541746 declare <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32>, <4 x i32>) nounwind readnone
17551747
17561748
1757 define <4 x i16> @test_x86_ssse3_phadd_sw(<4 x i16> %a0, <4 x i16> %a1) {
1758 ; CHECK: vphaddsw
1759 %res = call <4 x i16> @llvm.x86.ssse3.phadd.sw(<4 x i16> %a0, <4 x i16> %a1) ; <<4 x i16>> [#uses=1]
1760 ret <4 x i16> %res
1761 }
1762 declare <4 x i16> @llvm.x86.ssse3.phadd.sw(<4 x i16>, <4 x i16>) nounwind readnone
1763
1764
17651749 define <4 x i32> @test_x86_ssse3_phadd_sw_128(<4 x i32> %a0, <4 x i32> %a1) {
17661750 ; CHECK: vphaddsw
17671751 %res = call <4 x i32> @llvm.x86.ssse3.phadd.sw.128(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
17701754 declare <4 x i32> @llvm.x86.ssse3.phadd.sw.128(<4 x i32>, <4 x i32>) nounwind readnone
17711755
17721756
1773 define <4 x i16> @test_x86_ssse3_phadd_w(<4 x i16> %a0, <4 x i16> %a1) {
1774 ; CHECK: vphaddw
1775 %res = call <4 x i16> @llvm.x86.ssse3.phadd.w(<4 x i16> %a0, <4 x i16> %a1) ; <<4 x i16>> [#uses=1]
1776 ret <4 x i16> %res
1777 }
1778 declare <4 x i16> @llvm.x86.ssse3.phadd.w(<4 x i16>, <4 x i16>) nounwind readnone
1779
1780
17811757 define <8 x i16> @test_x86_ssse3_phadd_w_128(<8 x i16> %a0, <8 x i16> %a1) {
17821758 ; CHECK: vphaddw
17831759 %res = call <8 x i16> @llvm.x86.ssse3.phadd.w.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
17861762 declare <8 x i16> @llvm.x86.ssse3.phadd.w.128(<8 x i16>, <8 x i16>) nounwind readnone
17871763
17881764
1789 define <2 x i32> @test_x86_ssse3_phsub_d(<2 x i32> %a0, <2 x i32> %a1) {
1790 ; CHECK: vphsubd
1791 %res = call <2 x i32> @llvm.x86.ssse3.phsub.d(<2 x i32> %a0, <2 x i32> %a1) ; <<2 x i32>> [#uses=1]
1792 ret <2 x i32> %res
1793 }
1794 declare <2 x i32> @llvm.x86.ssse3.phsub.d(<2 x i32>, <2 x i32>) nounwind readnone
1795
1796
17971765 define <4 x i32> @test_x86_ssse3_phsub_d_128(<4 x i32> %a0, <4 x i32> %a1) {
17981766 ; CHECK: vphsubd
17991767 %res = call <4 x i32> @llvm.x86.ssse3.phsub.d.128(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
18021770 declare <4 x i32> @llvm.x86.ssse3.phsub.d.128(<4 x i32>, <4 x i32>) nounwind readnone
18031771
18041772
1805 define <4 x i16> @test_x86_ssse3_phsub_sw(<4 x i16> %a0, <4 x i16> %a1) {
1806 ; CHECK: vphsubsw
1807 %res = call <4 x i16> @llvm.x86.ssse3.phsub.sw(<4 x i16> %a0, <4 x i16> %a1) ; <<4 x i16>> [#uses=1]
1808 ret <4 x i16> %res
1809 }
1810 declare <4 x i16> @llvm.x86.ssse3.phsub.sw(<4 x i16>, <4 x i16>) nounwind readnone
1811
1812
18131773 define <8 x i16> @test_x86_ssse3_phsub_sw_128(<8 x i16> %a0, <8 x i16> %a1) {
18141774 ; CHECK: vphsubsw
18151775 %res = call <8 x i16> @llvm.x86.ssse3.phsub.sw.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
18181778 declare <8 x i16> @llvm.x86.ssse3.phsub.sw.128(<8 x i16>, <8 x i16>) nounwind readnone
18191779
18201780
1821 define <4 x i16> @test_x86_ssse3_phsub_w(<4 x i16> %a0, <4 x i16> %a1) {
1822 ; CHECK: vphsubw
1823 %res = call <4 x i16> @llvm.x86.ssse3.phsub.w(<4 x i16> %a0, <4 x i16> %a1) ; <<4 x i16>> [#uses=1]
1824 ret <4 x i16> %res
1825 }
1826 declare <4 x i16> @llvm.x86.ssse3.phsub.w(<4 x i16>, <4 x i16>) nounwind readnone
1827
1828
18291781 define <8 x i16> @test_x86_ssse3_phsub_w_128(<8 x i16> %a0, <8 x i16> %a1) {
18301782 ; CHECK: vphsubw
18311783 %res = call <8 x i16> @llvm.x86.ssse3.phsub.w.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
18341786 declare <8 x i16> @llvm.x86.ssse3.phsub.w.128(<8 x i16>, <8 x i16>) nounwind readnone
18351787
18361788
1837 define <4 x i16> @test_x86_ssse3_pmadd_ub_sw(<4 x i16> %a0, <4 x i16> %a1) {
1838 ; CHECK: vpmaddubsw
1839 %res = call <4 x i16> @llvm.x86.ssse3.pmadd.ub.sw(<4 x i16> %a0, <4 x i16> %a1) ; <<4 x i16>> [#uses=1]
1840 ret <4 x i16> %res
1841 }
1842 declare <4 x i16> @llvm.x86.ssse3.pmadd.ub.sw(<4 x i16>, <4 x i16>) nounwind readnone
1843
1844
18451789 define <8 x i16> @test_x86_ssse3_pmadd_ub_sw_128(<8 x i16> %a0, <8 x i16> %a1) {
18461790 ; CHECK: vpmaddubsw
18471791 %res = call <8 x i16> @llvm.x86.ssse3.pmadd.ub.sw.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
18501794 declare <8 x i16> @llvm.x86.ssse3.pmadd.ub.sw.128(<8 x i16>, <8 x i16>) nounwind readnone
18511795
18521796
1853 define <4 x i16> @test_x86_ssse3_pmul_hr_sw(<4 x i16> %a0, <4 x i16> %a1) {
1854 ; CHECK: vpmulhrsw
1855 %res = call <4 x i16> @llvm.x86.ssse3.pmul.hr.sw(<4 x i16> %a0, <4 x i16> %a1) ; <<4 x i16>> [#uses=1]
1856 ret <4 x i16> %res
1857 }
1858 declare <4 x i16> @llvm.x86.ssse3.pmul.hr.sw(<4 x i16>, <4 x i16>) nounwind readnone
1859
1860
18611797 define <8 x i16> @test_x86_ssse3_pmul_hr_sw_128(<8 x i16> %a0, <8 x i16> %a1) {
18621798 ; CHECK: vpmulhrsw
18631799 %res = call <8 x i16> @llvm.x86.ssse3.pmul.hr.sw.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
18641800 ret <8 x i16> %res
18651801 }
18661802 declare <8 x i16> @llvm.x86.ssse3.pmul.hr.sw.128(<8 x i16>, <8 x i16>) nounwind readnone
1867
1868
1869 define <8 x i8> @test_x86_ssse3_pshuf_b(<8 x i8> %a0, <8 x i8> %a1) {
1870 ; CHECK: vpshufb
1871 %res = call <8 x i8> @llvm.x86.ssse3.pshuf.b(<8 x i8> %a0, <8 x i8> %a1) ; <<8 x i8>> [#uses=1]
1872 ret <8 x i8> %res
1873 }
1874 declare <8 x i8> @llvm.x86.ssse3.pshuf.b(<8 x i8>, <8 x i8>) nounwind readnone
18751803
18761804
18771805 define <16 x i8> @test_x86_ssse3_pshuf_b_128(<16 x i8> %a0, <16 x i8> %a1) {
18821810 declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>) nounwind readnone
18831811
18841812
1885 define <8 x i8> @test_x86_ssse3_psign_b(<8 x i8> %a0, <8 x i8> %a1) {
1886 ; CHECK: vpsignb
1887 %res = call <8 x i8> @llvm.x86.ssse3.psign.b(<8 x i8> %a0, <8 x i8> %a1) ; <<8 x i8>> [#uses=1]
1888 ret <8 x i8> %res
1889 }
1890 declare <8 x i8> @llvm.x86.ssse3.psign.b(<8 x i8>, <8 x i8>) nounwind readnone
1891
1892
18931813 define <16 x i8> @test_x86_ssse3_psign_b_128(<16 x i8> %a0, <16 x i8> %a1) {
18941814 ; CHECK: vpsignb
18951815 %res = call <16 x i8> @llvm.x86.ssse3.psign.b.128(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]
18981818 declare <16 x i8> @llvm.x86.ssse3.psign.b.128(<16 x i8>, <16 x i8>) nounwind readnone
18991819
19001820
1901 define <2 x i32> @test_x86_ssse3_psign_d(<2 x i32> %a0, <2 x i32> %a1) {
1902 ; CHECK: vpsignd
1903 %res = call <2 x i32> @llvm.x86.ssse3.psign.d(<2 x i32> %a0, <2 x i32> %a1) ; <<2 x i32>> [#uses=1]
1904 ret <2 x i32> %res
1905 }
1906 declare <2 x i32> @llvm.x86.ssse3.psign.d(<2 x i32>, <2 x i32>) nounwind readnone
1907
1908
19091821 define <4 x i32> @test_x86_ssse3_psign_d_128(<4 x i32> %a0, <4 x i32> %a1) {
19101822 ; CHECK: vpsignd
19111823 %res = call <4 x i32> @llvm.x86.ssse3.psign.d.128(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
19121824 ret <4 x i32> %res
19131825 }
19141826 declare <4 x i32> @llvm.x86.ssse3.psign.d.128(<4 x i32>, <4 x i32>) nounwind readnone
1915
1916
1917 define <4 x i16> @test_x86_ssse3_psign_w(<4 x i16> %a0, <4 x i16> %a1) {
1918 ; CHECK: vpsignw
1919 %res = call <4 x i16> @llvm.x86.ssse3.psign.w(<4 x i16> %a0, <4 x i16> %a1) ; <<4 x i16>> [#uses=1]
1920 ret <4 x i16> %res
1921 }
1922 declare <4 x i16> @llvm.x86.ssse3.psign.w(<4 x i16>, <4 x i16>) nounwind readnone
19231827
19241828
19251829 define <8 x i16> @test_x86_ssse3_psign_w_128(<8 x i16> %a0, <8 x i16> %a1) {