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TableGen: convert InstAlias's Emit bit to an int. When multiple aliases overlap, the correct string to print can often be determined purely by considering the InstAlias declarations in some particular order. This allows the user to specify that order manually when desired, without resorting to hacking around with the default lexicographical order on Record instantiation, which is error-prone and ugly. I was also mistaken about "add w2, w3, w4" being the same as "add w2, w3, w4, uxtw". That's only true if Rn is the stack pointer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209199 91177308-0d34-0410-b5e6-96231b3b80d8 Tim Northover 5 years ago
6 changed file(s) with 116 addition(s) and 104 deletion(s). Raw diff Collapse all Expand all
949949 /// InstAlias - This defines an alternate assembly syntax that is allowed to
950950 /// match an instruction that has a different (more canonical) assembly
951951 /// representation.
952 class InstAliasbit Emit = 0b1> {
952 class InstAliasint Emit = 1> {
953953 string AsmString = Asm; // The .s format to match the instruction with.
954954 dag ResultInst = Result; // The MCInst to generate.
955 bit EmitAlias = Emit; // Emit the alias instead of what's aliased.
955
956 // This determines which order the InstPrinter detects aliases for
957 // printing. A larger value makes the alias more likely to be
958 // emitted. The Instruction's own definition is notionally 0.5, so 0
959 // disables printing and 1 enables it if there are no conflicting aliases.
960 int EmitPriority = Emit;
956961
957962 // Predicates - Predicates that must be true for this to match.
958963 list Predicates = [];
16571657 let Inst{31} = 1;
16581658 }
16591659
1660 // Register/register aliases with no shift when SP is not used.
1661 def : AddSubRegAlias(NAME#"Wrs"),
1662 GPR32, GPR32, GPR32, 0>;
1663 def : AddSubRegAlias(NAME#"Xrs"),
1664 GPR64, GPR64, GPR64, 0>;
1665
16601666 // Register/register aliases with no shift when either the destination or
1661 // first source register is SP. This relies on the shifted register aliases
1662 // above matching first in the case when SP is not used.
1667 // first source register is SP.
16631668 def : AddSubRegAlias(NAME#"Wrx"),
1664 GPR32sp, GPR32sp, GPR32, 16>; // UXTW #0
1669 GPR32sponly, GPR32sp, GPR32, 16>; // UXTW #0
1670 def : AddSubRegAlias(NAME#"Wrx"),
1671 GPR32sp, GPR32sponly, GPR32, 16>; // UXTW #0
16651672 def : AddSubRegAlias
16661673 !cast(NAME#"Xrx64"),
1667 GPR64sp, GPR64sp, GPR64, 24>; // UXTX #0
1674 GPR64sponly, GPR64sp, GPR64, 24>; // UXTX #0
1675 def : AddSubRegAlias
1676 !cast(NAME#"Xrx64"),
1677 GPR64sp, GPR64sponly, GPR64, 24>; // UXTX #0
16681678 }
16691679
16701680 multiclass AddSubS {
17151725
17161726 // Compare aliases
17171727 def : InstAlias(NAME#"Wri")
1718 WZR, GPR32sp:$src, addsub_shifted_imm32:$imm)>;
1728 WZR, GPR32sp:$src, addsub_shifted_imm32:$imm), 5>;
17191729 def : InstAlias(NAME#"Xri")
1720 XZR, GPR64sp:$src, addsub_shifted_imm64:$imm)>;
1730 XZR, GPR64sp:$src, addsub_shifted_imm64:$imm), 5>;
17211731 def : InstAlias(NAME#"Wrx")
1722 WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh)>;
1732 WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh), 4>;
17231733 def : InstAlias(NAME#"Xrx")
1724 XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh)>;
1734 XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh), 4>;
17251735 def : InstAlias(NAME#"Xrx64")
1726 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh)>;
1736 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh), 4>;
17271737 def : InstAlias(NAME#"Wrs")
1728 WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh)>;
1738 WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh), 4>;
17291739 def : InstAlias(NAME#"Xrs")
1730 XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh)>;
1740 XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh), 4>;
17311741
17321742 // Compare shorthands
17331743 def : InstAlias(NAME#"Wrs")
1734 WZR, GPR32:$src1, GPR32:$src2, 0)>;
1744 WZR, GPR32:$src1, GPR32:$src2, 0), 5>;
17351745 def : InstAlias(NAME#"Xrs")
1736 XZR, GPR64:$src1, GPR64:$src2, 0)>;
1746 XZR, GPR64:$src1, GPR64:$src2, 0), 5>;
1747
1748 // Register/register aliases with no shift when SP is not used.
1749 def : AddSubRegAlias(NAME#"Wrs"),
1750 GPR32, GPR32, GPR32, 0>;
1751 def : AddSubRegAlias(NAME#"Xrs"),
1752 GPR64, GPR64, GPR64, 0>;
17371753
17381754 // Register/register aliases with no shift when the first source register
1739 // is SP. This relies on the shifted register aliases above matching first
1740 // in the case when SP is not used.
1755 // is SP.
17411756 def : AddSubRegAlias(NAME#"Wrx"),
1742 GPR32, GPR32sp, GPR32, 16>; // UXTW #0
1757 GPR32, GPR32sponly, GPR32, 16>; // UXTW #0
17431758 def : AddSubRegAlias
17441759 !cast(NAME#"Xrx64"),
1745 GPR64, GPR64sp, GPR64, 24>; // UXTX #0
1760 GPR64, GPR64sponly, GPR64, 24>; // UXTX #0
17461761 }
17471762
17481763 //---
567567 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
568568 }
569569
570 def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0)>;
571 def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0)>;
570 def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
571 def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
572572 def : InstAlias<"neg $dst, $src$shift",
573 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift)>;
573 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
574574 def : InstAlias<"neg $dst, $src$shift",
575 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift)>;
576
577 def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0)>;
578 def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0)>;
575 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
576
577 def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
578 def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
579579 def : InstAlias<"negs $dst, $src$shift",
580 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift)>;
580 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
581581 def : InstAlias<"negs $dst, $src$shift",
582 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift)>;
583
584
585 // Register/register aliases with no shift when SP is not used.
586 def : AddSubRegAlias<"add", ADDWrs, GPR32, GPR32, GPR32, 0>;
587 def : AddSubRegAlias<"add", ADDXrs, GPR64, GPR64, GPR64, 0>;
588 def : AddSubRegAlias<"sub", SUBWrs, GPR32, GPR32, GPR32, 0>;
589 def : AddSubRegAlias<"sub", SUBXrs, GPR64, GPR64, GPR64, 0>;
590 def : AddSubRegAlias<"adds", ADDSWrs, GPR32, GPR32, GPR32, 0>;
591 def : AddSubRegAlias<"adds", ADDSXrs, GPR64, GPR64, GPR64, 0>;
592 def : AddSubRegAlias<"subs", SUBSWrs, GPR32, GPR32, GPR32, 0>;
593 def : AddSubRegAlias<"subs", SUBSXrs, GPR64, GPR64, GPR64, 0>;
582 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
594583
595584
596585 // Unsigned/Signed divide
707696 BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
708697 defm ORR : LogicalReg<0b01, 0, "orr", or>;
709698
710 // FIXME: these aliases are named so that they get considered by TableGen before
711 // the already instantiated anonymous_ABC ones. Some kind of explicit priority
712 // system would be better.
713 def AA_MOVWr : InstAlias<"mov $dst, $src",
714 (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0)>;
715 def AA_MOVXr : InstAlias<"mov $dst, $src",
716 (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0)>;
717
718 def AA_MVNWr : InstAlias<"mvn $Wd, $Wm",
719 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0)>;
720 def AA_MVNXr : InstAlias<"mvn $Xd, $Xm",
721 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0)>;
722
723 def AA_MVNWrs : InstAlias<"mvn $Wd, $Wm$sh",
724 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh)>;
725 def AA_MVNXrs : InstAlias<"mvn $Xd, $Xm$sh",
726 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh)>;
727
728 def AA_TSTWri : InstAlias<"tst $src1, $src2",
729 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2)>;
730 def AA_TSTXri : InstAlias<"tst $src1, $src2",
731 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2)>;
732
733 def AA_TSTWr: InstAlias<"tst $src1, $src2",
734 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0)>;
735 def AA_TSTXr: InstAlias<"tst $src1, $src2",
736 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0)>;
737
738 def AB_TSTWrs : InstAlias<"tst $src1, $src2$sh",
739 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh)>;
740 def AB_TSTXrs : InstAlias<"tst $src1, $src2$sh",
741 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh)>;
699 def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0), 2>;
700 def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0), 2>;
701
702 def : InstAlias<"mvn $Wd, $Wm", (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0), 3>;
703 def : InstAlias<"mvn $Xd, $Xm", (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0), 3>;
704
705 def : InstAlias<"mvn $Wd, $Wm$sh",
706 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh), 2>;
707 def : InstAlias<"mvn $Xd, $Xm$sh",
708 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh), 2>;
709
710 def : InstAlias<"tst $src1, $src2",
711 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2), 2>;
712 def : InstAlias<"tst $src1, $src2",
713 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2), 2>;
714
715 def : InstAlias<"tst $src1, $src2",
716 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0), 3>;
717 def : InstAlias<"tst $src1, $src2",
718 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0), 3>;
719
720 def : InstAlias<"tst $src1, $src2$sh",
721 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh), 2>;
722 def : InstAlias<"tst $src1, $src2$sh",
723 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh), 2>;
742724
743725
744726 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
2626 // CHECK: add x2, x4, w5, uxtb // encoding: [0x82,0x00,0x25,0x8b]
2727 // CHECK: add x20, sp, w19, uxth // encoding: [0xf4,0x23,0x33,0x8b]
2828 // CHECK: add x12, x1, w20, uxtw // encoding: [0x2c,0x40,0x34,0x8b]
29 // CHECK-AARCH64: add x20, x3, x13, uxtx // encoding: [0x74,0x60,0x2d,0x8b]
30 // CHECK-ARM64: add x20, x3, x13 // encoding: [0x74,0x60,0x2d,0x8b]
29 // CHECK: add x20, x3, x13, uxtx // encoding: [0x74,0x60,0x2d,0x8b]
3130 // CHECK: add x17, x25, w20, sxtb // encoding: [0x31,0x83,0x34,0x8b]
3231 // CHECK: add x18, x13, w19, sxth // encoding: [0xb2,0xa1,0x33,0x8b]
3332 // CHECK: add sp, x2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0x8b]
4443 add w2, w3, w5, sxtx
4544 // CHECK: add w2, w5, w7, uxtb // encoding: [0xa2,0x00,0x27,0x0b]
4645 // CHECK: add w21, w15, w17, uxth // encoding: [0xf5,0x21,0x31,0x0b]
47 // CHECK-AARCH64: add w30, w29, wzr, uxtw // encoding: [0xbe,0x43,0x3f,0x0b]
48 // CHECK-ARM64: add w30, w29, wzr // encoding: [0xbe,0x43,0x3f,0x0b]
46 // CHECK: add w30, w29, wzr, uxtw // encoding: [0xbe,0x43,0x3f,0x0b]
4947 // CHECK: add w19, w17, w1, uxtx // encoding: [0x33,0x62,0x21,0x0b]
5048 // CHECK: add w2, w5, w1, sxtb // encoding: [0xa2,0x80,0x21,0x0b]
5149 // CHECK: add w26, w17, w19, sxth // encoding: [0x3a,0xa2,0x33,0x0b]
7472 // CHECK: sub x2, x4, w5, uxtb #2 // encoding: [0x82,0x08,0x25,0xcb]
7573 // CHECK: sub x20, sp, w19, uxth #4 // encoding: [0xf4,0x33,0x33,0xcb]
7674 // CHECK: sub x12, x1, w20, uxtw // encoding: [0x2c,0x40,0x34,0xcb]
77 // CHECK-AARCH64: sub x20, x3, x13, uxtx // encoding: [0x74,0x60,0x2d,0xcb]
78 // CHECK-ARM64: sub x20, x3, x13 // encoding: [0x74,0x60,0x2d,0xcb]
75 // CHECK: sub x20, x3, x13, uxtx // encoding: [0x74,0x60,0x2d,0xcb]
7976 // CHECK: sub x17, x25, w20, sxtb // encoding: [0x31,0x83,0x34,0xcb]
8077 // CHECK: sub x18, x13, w19, sxth // encoding: [0xb2,0xa1,0x33,0xcb]
8178 // CHECK: sub sp, x2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0xcb]
9188 sub w2, w3, w5, sxtx
9289 // CHECK: sub w2, w5, w7, uxtb // encoding: [0xa2,0x00,0x27,0x4b]
9390 // CHECK: sub w21, w15, w17, uxth // encoding: [0xf5,0x21,0x31,0x4b]
94 // CHECK-AARCH64: sub w30, w29, wzr, uxtw // encoding: [0xbe,0x43,0x3f,0x4b]
95 // CHECK-ARM64: sub w30, w29, wzr // encoding: [0xbe,0x43,0x3f,0x4b]
91 // CHECK: sub w30, w29, wzr, uxtw // encoding: [0xbe,0x43,0x3f,0x4b]
9692 // CHECK: sub w19, w17, w1, uxtx // encoding: [0x33,0x62,0x21,0x4b]
9793 // CHECK: sub w2, w5, w1, sxtb // encoding: [0xa2,0x80,0x21,0x4b]
9894 // CHECK: sub w26, wsp, w19, sxth // encoding: [0xfa,0xa3,0x33,0x4b]
111107 // CHECK: adds x2, x4, w5, uxtb #2 // encoding: [0x82,0x08,0x25,0xab]
112108 // CHECK: adds x20, sp, w19, uxth #4 // encoding: [0xf4,0x33,0x33,0xab]
113109 // CHECK: adds x12, x1, w20, uxtw // encoding: [0x2c,0x40,0x34,0xab]
114 // CHECK-AARCH64: adds x20, x3, x13, uxtx // encoding: [0x74,0x60,0x2d,0xab]
115 // CHECK-ARM64: adds x20, x3, x13 // encoding: [0x74,0x60,0x2d,0xab]
110 // CHECK: adds x20, x3, x13, uxtx // encoding: [0x74,0x60,0x2d,0xab]
116111 // CHECK: {{adds xzr,|cmn}} x25, w20, sxtb #3 // encoding: [0x3f,0x8f,0x34,0xab]
117112 // CHECK: adds x18, sp, w19, sxth // encoding: [0xf2,0xa3,0x33,0xab]
118113 // CHECK: {{adds xzr,|cmn}} x2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0xab]
128123 adds w2, w3, w5, sxtx
129124 // CHECK: adds w2, w5, w7, uxtb // encoding: [0xa2,0x00,0x27,0x2b]
130125 // CHECK: adds w21, w15, w17, uxth // encoding: [0xf5,0x21,0x31,0x2b]
131 // CHECK-AARCH64: adds w30, w29, wzr, uxtw // encoding: [0xbe,0x43,0x3f,0x2b]
132 // CHECK-ARM64: adds w30, w29, wzr // encoding: [0xbe,0x43,0x3f,0x2b]
126 // CHECK: adds w30, w29, wzr, uxtw // encoding: [0xbe,0x43,0x3f,0x2b]
133127 // CHECK: adds w19, w17, w1, uxtx // encoding: [0x33,0x62,0x21,0x2b]
134128 // CHECK: adds w2, w5, w1, sxtb #1 // encoding: [0xa2,0x84,0x21,0x2b]
135129 // CHECK: adds w26, wsp, w19, sxth // encoding: [0xfa,0xa3,0x33,0x2b]
149143 // CHECK: subs x2, x4, w5, uxtb #2 // encoding: [0x82,0x08,0x25,0xeb]
150144 // CHECK: subs x20, sp, w19, uxth #4 // encoding: [0xf4,0x33,0x33,0xeb]
151145 // CHECK: subs x12, x1, w20, uxtw // encoding: [0x2c,0x40,0x34,0xeb]
152 // CHECK-AARCH64: subs x20, x3, x13, uxtx // encoding: [0x74,0x60,0x2d,0xeb]
153 // CHECK-ARM64: subs x20, x3, x13 // encoding: [0x74,0x60,0x2d,0xeb]
146 // CHECK: subs x20, x3, x13, uxtx // encoding: [0x74,0x60,0x2d,0xeb]
154147 // CHECK: {{subs xzr,|cmp}} x25, w20, sxtb #3 // encoding: [0x3f,0x8f,0x34,0xeb]
155148 // CHECK: subs x18, sp, w19, sxth // encoding: [0xf2,0xa3,0x33,0xeb]
156149 // CHECK: {{subs xzr,|cmp}} x2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0xeb]
166159 subs w2, w3, w5, sxtx
167160 // CHECK: subs w2, w5, w7, uxtb // encoding: [0xa2,0x00,0x27,0x6b]
168161 // CHECK: subs w21, w15, w17, uxth // encoding: [0xf5,0x21,0x31,0x6b]
169 // CHECK-AARCH64: subs w30, w29, wzr, uxtw // encoding: [0xbe,0x43,0x3f,0x6b]
170 // CHECK-ARM64: subs w30, w29, wzr // encoding: [0xbe,0x43,0x3f,0x6b]
162 // CHECK: subs w30, w29, wzr, uxtw // encoding: [0xbe,0x43,0x3f,0x6b]
171163 // CHECK: subs w19, w17, w1, uxtx // encoding: [0x33,0x62,0x21,0x6b]
172164 // CHECK: subs w2, w5, w1, sxtb #1 // encoding: [0xa2,0x84,0x21,0x6b]
173165 // CHECK: subs w26, wsp, w19, sxth // encoding: [0xfa,0xa3,0x33,0x6b]
177177
178178 ; CHECK: add w1, w2, w3, uxtb ; encoding: [0x41,0x00,0x23,0x0b]
179179 ; CHECK: add w1, w2, w3, uxth ; encoding: [0x41,0x20,0x23,0x0b]
180 ; CHECK: add w1, w2, w3 ; encoding: [0x41,0x40,0x23,0x0b]
180 ; CHECK: add w1, w2, w3, uxtw ; encoding: [0x41,0x40,0x23,0x0b]
181181 ; CHECK: add w1, w2, w3, uxtx ; encoding: [0x41,0x60,0x23,0x0b]
182182 ; CHECK: add w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x0b]
183183 ; CHECK: add w1, w2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x0b]
221221
222222 ; CHECK: sub w1, w2, w3, uxtb ; encoding: [0x41,0x00,0x23,0x4b]
223223 ; CHECK: sub w1, w2, w3, uxth ; encoding: [0x41,0x20,0x23,0x4b]
224 ; CHECK: sub w1, w2, w3 ; encoding: [0x41,0x40,0x23,0x4b]
224 ; CHECK: sub w1, w2, w3, uxtw ; encoding: [0x41,0x40,0x23,0x4b]
225225 ; CHECK: sub w1, w2, w3, uxtx ; encoding: [0x41,0x60,0x23,0x4b]
226226 ; CHECK: sub w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x4b]
227227 ; CHECK: sub w1, w2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x4b]
265265
266266 ; CHECK: adds w1, w2, w3, uxtb ; encoding: [0x41,0x00,0x23,0x2b]
267267 ; CHECK: adds w1, w2, w3, uxth ; encoding: [0x41,0x20,0x23,0x2b]
268 ; CHECK: adds w1, w2, w3 ; encoding: [0x41,0x40,0x23,0x2b]
268 ; CHECK: adds w1, w2, w3, uxtw ; encoding: [0x41,0x40,0x23,0x2b]
269269 ; CHECK: adds w1, w2, w3, uxtx ; encoding: [0x41,0x60,0x23,0x2b]
270270 ; CHECK: adds w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x2b]
271271 ; CHECK: adds w1, w2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x2b]
309309
310310 ; CHECK: subs w1, w2, w3, uxtb ; encoding: [0x41,0x00,0x23,0x6b]
311311 ; CHECK: subs w1, w2, w3, uxth ; encoding: [0x41,0x20,0x23,0x6b]
312 ; CHECK: subs w1, w2, w3 ; encoding: [0x41,0x40,0x23,0x6b]
312 ; CHECK: subs w1, w2, w3, uxtw ; encoding: [0x41,0x40,0x23,0x6b]
313313 ; CHECK: subs w1, w2, w3, uxtx ; encoding: [0x41,0x60,0x23,0x6b]
314314 ; CHECK: subs w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x6b]
315315 ; CHECK: subs w1, w2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x6b]
749749 return AsmString.count(' ') + AsmString.count('\t');
750750 }
751751
752 namespace {
753 struct AliasPriorityComparator {
754 typedef std::pair ValueType;
755 bool operator()(const ValueType &LHS, const ValueType &RHS) {
756 if (LHS.second == RHS.second) {
757 // We don't actually care about the order, but for consistency it
758 // shouldn't depend on pointer comparisons.
759 return LHS.first->TheDef->getName() < RHS.first->TheDef->getName();
760 }
761
762 // Aliases with larger priorities should be considered first.
763 return LHS.second > RHS.second;
764 }
765 };
766 }
767
768
752769 void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
753770 Record *AsmWriter = Target.getAsmWriter();
754771
761778
762779 // Emit the method that prints the alias instruction.
763780 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
781 unsigned Variant = AsmWriter->getValueAsInt("Variant");
764782
765783 std::vector AllInstAliases =
766784 Records.getAllDerivedDefinitions("InstAlias");
767785
768786 // Create a map from the qualified name to a list of potential matches.
769 std::map > AliasMap;
770 unsigned Variant = AsmWriter->getValueAsInt("Variant");
787 typedef std::set, AliasPriorityComparator>
788 AliasWithPriority;
789 std::map AliasMap;
771790 for (std::vector::iterator
772791 I = AllInstAliases.begin(), E = AllInstAliases.end(); I != E; ++I) {
773792 CodeGenInstAlias *Alias = new CodeGenInstAlias(*I, Variant, Target);
774793 const Record *R = *I;
775 if (!R->getValueAsBit("EmitAlias"))
776 continue; // We were told not to emit the alias, but to emit the aliasee.
794 int Priority = R->getValueAsInt("EmitPriority");
795 if (Priority < 1)
796 continue; // Aliases with priority 0 are never emitted.
797
777798 const DagInit *DI = R->getValueAsDag("ResultInst");
778799 const DefInit *Op = cast(DI->getOperator());
779 AliasMap[getQualifiedName(Op->getDef())].push_back(Alias);
800 AliasMap[getQualifiedName(Op->getDef())].insert(std::make_pair(Alias,
801 Priority));
780802 }
781803
782804 // A map of which conditions need to be met for each instruction operand
783805 // before it can be matched to the mnemonic.
784806 std::map > IAPrinterMap;
785807
786 for (std::map >::iterator
787 I = AliasMap.begin(), E = AliasMap.end(); I != E; ++I) {
788 std::vector &Aliases = I->second;
789
790 for (std::vector::iterator
791 II = Aliases.begin(), IE = Aliases.end(); II != IE; ++II) {
792 const CodeGenInstAlias *CGA = *II;
808 for (auto &Aliases : AliasMap) {
809 for (auto &Alias : Aliases.second) {
810 const CodeGenInstAlias *CGA = Alias.first;
793811 unsigned LastOpNo = CGA->ResultInstOperandIndex.size();
794812 unsigned NumResultOps =
795813 CountNumOperands(CGA->ResultInst->AsmString, Variant);
899917 }
900918
901919 if (CantHandle) continue;
902 IAPrinterMap[I->first].push_back(IAP);
920 IAPrinterMap[Aliases.first].push_back(IAP);
903921 }
904922 }
905923