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[ARM] Add MVE vector compare instructions. Summary: These take a pair of vector register to compare, and a comparison type (written in the form of an Arm condition suffix); they output a vector of booleans in the VPR register, where predication can conveniently use them. Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62676 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364027 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Tatham 1 year, 1 month ago
5 changed file(s) with 681 addition(s) and 8 deletion(s). Raw diff Collapse all Expand all
6161 let RenderMethod = "addITCondCodeOperands";
6262 let PredicateMethod = "isITCondCodeRestrictedI";
6363 let ParserMethod = "parseITCondCode";
64 let DiagnosticString = "condition code for sign-independent integer "#
65 "comparison must be EQ or NE";
6466 }
6567
6668 // VPT/VCMP restricted predicate for signed types
6971 let RenderMethod = "addITCondCodeOperands";
7072 let PredicateMethod = "isITCondCodeRestrictedS";
7173 let ParserMethod = "parseITCondCode";
74 let DiagnosticString = "condition code for signed integer "#
75 "comparison must be EQ, NE, LT, GT, LE or GE";
7276 }
7377
7478 // VPT/VCMP restricted predicate for unsigned types
7781 let RenderMethod = "addITCondCodeOperands";
7882 let PredicateMethod = "isITCondCodeRestrictedU";
7983 let ParserMethod = "parseITCondCode";
84 let DiagnosticString = "condition code for unsigned integer "#
85 "comparison must be EQ, NE, HS or HI";
8086 }
8187
8288 // VPT/VCMP restricted predicate for floating point
8591 let RenderMethod = "addITCondCodeOperands";
8692 let PredicateMethod = "isITCondCodeRestrictedFP";
8793 let ParserMethod = "parseITCondCode";
88 }
89
90 def pred_basic_i : Operand {
94 let DiagnosticString = "condition code for floating-point "#
95 "comparison must be EQ, NE, LT, GT, LE or GE";
96 }
97
98 class VCMPPredicateOperand : Operand;
99
100 def pred_basic_i : VCMPPredicateOperand {
91101 let PrintMethod = "printMandatoryRestrictedPredicateOperand";
92102 let ParserMatchClass = pred_restricted_i_asmoperand;
93103 let DecoderMethod = "DecodeRestrictedIPredicateOperand";
94104 let EncoderMethod = "getRestrictedCondCodeOpValue";
95105 }
96106
97 def pred_basic_u : Operand {
107 def pred_basic_u : VCMPPredicateOperand {
98108 let PrintMethod = "printMandatoryRestrictedPredicateOperand";
99109 let ParserMatchClass = pred_restricted_u_asmoperand;
100110 let DecoderMethod = "DecodeRestrictedUPredicateOperand";
101111 let EncoderMethod = "getRestrictedCondCodeOpValue";
102112 }
103113
104 def pred_basic_s : Operand {
114 def pred_basic_s : VCMPPredicateOperand {
105115 let PrintMethod = "printMandatoryRestrictedPredicateOperand";
106116 let ParserMatchClass = pred_restricted_s_asmoperand;
107117 let DecoderMethod = "DecodeRestrictedSPredicateOperand";
108118 let EncoderMethod = "getRestrictedCondCodeOpValue";
109119 }
110120
111 def pred_basic_fp : Operand {
121 def pred_basic_fp : VCMPPredicateOperand {
112122 let PrintMethod = "printMandatoryRestrictedPredicateOperand";
113123 let ParserMatchClass = pred_restricted_fp_asmoperand;
114124 let DecoderMethod = "DecodeRestrictedFPPredicateOperand";
22522262
22532263 // end of MVE Floating Point instructions
22542264
2265 // start of MVE compares
2266
2267 class MVE_VCMPqq bits_21_20,
2268 VCMPPredicateOperand predtype, list pattern=[]>
2269 : MVE_p<(outs VCCR:$P0), (ins MQPR:$Qn, MQPR:$Qm, predtype:$fc),
2270 NoItinerary, "vcmp", suffix, "$fc, $Qn, $Qm", vpred_n, "", pattern> {
2271 // Base class for comparing two vector registers
2272 bits<3> fc;
2273 bits<4> Qn;
2274 bits<4> Qm;
2275
2276 let Inst{28} = bit_28;
2277 let Inst{25-22} = 0b1000;
2278 let Inst{21-20} = bits_21_20;
2279 let Inst{19-17} = Qn{2-0};
2280 let Inst{16-13} = 0b1000;
2281 let Inst{12} = fc{2};
2282 let Inst{11-8} = 0b1111;
2283 let Inst{7} = fc{0};
2284 let Inst{6} = 0b0;
2285 let Inst{5} = Qm{3};
2286 let Inst{4} = 0b0;
2287 let Inst{3-1} = Qm{2-0};
2288 let Inst{0} = fc{1};
2289
2290 let Constraints = "";
2291
2292 // We need a custom decoder method for these instructions because of
2293 // the output VCCR operand, which isn't encoded in the instruction
2294 // bits anywhere (there is only one choice for it) but has to be
2295 // included in the MC operands so that codegen will be able to track
2296 // its data flow between instructions, spill/reload it when
2297 // necessary, etc. There seems to be no way to get the Tablegen
2298 // decoder to emit an operand that isn't affected by any instruction
2299 // bit.
2300 let DecoderMethod = "DecodeMVEVCMP";
2301 }
2302
2303 class MVE_VCMPqqf
2304 : MVE_VCMPqq {
2305 let Predicates = [HasMVEFloat];
2306 }
2307
2308 class MVE_VCMPqqi size>
2309 : MVE_VCMPqq {
2310 let Inst{12} = 0b0;
2311 let Inst{0} = 0b0;
2312 }
2313
2314 class MVE_VCMPqqu size>
2315 : MVE_VCMPqq {
2316 let Inst{12} = 0b0;
2317 let Inst{0} = 0b1;
2318 }
2319
2320 class MVE_VCMPqqs size>
2321 : MVE_VCMPqq {
2322 let Inst{12} = 0b1;
2323 }
2324
2325 def MVE_VCMPf32 : MVE_VCMPqqf<"f32", 0b0>;
2326 def MVE_VCMPf16 : MVE_VCMPqqf<"f16", 0b1>;
2327
2328 def MVE_VCMPi8 : MVE_VCMPqqi<"i8", 0b00>;
2329 def MVE_VCMPi16 : MVE_VCMPqqi<"i16", 0b01>;
2330 def MVE_VCMPi32 : MVE_VCMPqqi<"i32", 0b10>;
2331
2332 def MVE_VCMPu8 : MVE_VCMPqqu<"u8", 0b00>;
2333 def MVE_VCMPu16 : MVE_VCMPqqu<"u16", 0b01>;
2334 def MVE_VCMPu32 : MVE_VCMPqqu<"u32", 0b10>;
2335
2336 def MVE_VCMPs8 : MVE_VCMPqqs<"s8", 0b00>;
2337 def MVE_VCMPs16 : MVE_VCMPqqs<"s16", 0b01>;
2338 def MVE_VCMPs32 : MVE_VCMPqqs<"s32", 0b10>;
2339
2340 class MVE_VCMPqr bits_21_20,
2341 VCMPPredicateOperand predtype, list pattern=[]>
2342 : MVE_p<(outs VCCR:$P0), (ins MQPR:$Qn, GPRwithZR:$Rm, predtype:$fc),
2343 NoItinerary, "vcmp", suffix, "$fc, $Qn, $Rm", vpred_n, "", pattern> {
2344 // Base class for comparing a vector register with a scalar
2345 bits<3> fc;
2346 bits<4> Qn;
2347 bits<4> Rm;
2348
2349 let Inst{28} = bit_28;
2350 let Inst{25-22} = 0b1000;
2351 let Inst{21-20} = bits_21_20;
2352 let Inst{19-17} = Qn{2-0};
2353 let Inst{16-13} = 0b1000;
2354 let Inst{12} = fc{2};
2355 let Inst{11-8} = 0b1111;
2356 let Inst{7} = fc{0};
2357 let Inst{6} = 0b1;
2358 let Inst{5} = fc{1};
2359 let Inst{4} = 0b0;
2360 let Inst{3-0} = Rm{3-0};
2361
2362 let Constraints = "";
2363 // Custom decoder method, for the same reason as MVE_VCMPqq
2364 let DecoderMethod = "DecodeMVEVCMP";
2365 }
2366
2367 class MVE_VCMPqrf
2368 : MVE_VCMPqr {
2369 let Predicates = [HasMVEFloat];
2370 }
2371
2372 class MVE_VCMPqri size>
2373 : MVE_VCMPqr {
2374 let Inst{12} = 0b0;
2375 let Inst{5} = 0b0;
2376 }
2377
2378 class MVE_VCMPqru size>
2379 : MVE_VCMPqr {
2380 let Inst{12} = 0b0;
2381 let Inst{5} = 0b1;
2382 }
2383
2384 class MVE_VCMPqrs size>
2385 : MVE_VCMPqr {
2386 let Inst{12} = 0b1;
2387 }
2388
2389 def MVE_VCMPf32r : MVE_VCMPqrf<"f32", 0b0>;
2390 def MVE_VCMPf16r : MVE_VCMPqrf<"f16", 0b1>;
2391
2392 def MVE_VCMPi8r : MVE_VCMPqri<"i8", 0b00>;
2393 def MVE_VCMPi16r : MVE_VCMPqri<"i16", 0b01>;
2394 def MVE_VCMPi32r : MVE_VCMPqri<"i32", 0b10>;
2395
2396 def MVE_VCMPu8r : MVE_VCMPqru<"u8", 0b00>;
2397 def MVE_VCMPu16r : MVE_VCMPqru<"u16", 0b01>;
2398 def MVE_VCMPu32r : MVE_VCMPqru<"u32", 0b10>;
2399
2400 def MVE_VCMPs8r : MVE_VCMPqrs<"s8", 0b00>;
2401 def MVE_VCMPs16r : MVE_VCMPqrs<"s16", 0b01>;
2402 def MVE_VCMPs32r : MVE_VCMPqrs<"s32", 0b10>;
2403
2404 // end of MVE compares
2405
22552406 class MVE_VPT size, dag iops, string asm, list pattern=[]>
22562407 : MVE_MI<(outs ), iops, NoItinerary, !strconcat("vpt", "${Mk}", ".", suffix), asm, "", pattern> {
22572408 bits<3> fc;
65676567 // scalar predication operand we do not add the vector one and leave until
65686568 // now to fix it up.
65696569 if (CanAcceptVPTPredicationCode && Mnemonic != "vmov" &&
6570 !Mnemonic.startswith("vcmp") &&
65706571 !(Mnemonic.startswith("vcvt") && Mnemonic != "vcvta" &&
65716572 Mnemonic != "vcvtn" && Mnemonic != "vcvtp" && Mnemonic != "vcvtm")) {
65726573 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
66826683 Operands.insert(Operands.begin(),
66836684 ARMOperand::CreateToken(StringRef("vcvtn"), MLoc));
66846685 }
6685 // For vmov instructions, as mentioned earlier, we did not add the vector
6686 // For vmov and vcmp, as mentioned earlier, we did not add the vector
66866687 // predication code, since these may contain operands that require
66876688 // special parsing. So now we have to see if they require vector
66886689 // predication and replace the scalar one with the vector predication
66896690 // operand if that is the case.
6690 else if (Mnemonic == "vmov" ||
6691 else if (Mnemonic == "vmov" || Mnemonic.startswith("vcmp") ||
66916692 (Mnemonic.startswith("vcvt") && !Mnemonic.startswith("vcvta") &&
66926693 !Mnemonic.startswith("vcvtn") && !Mnemonic.startswith("vcvtp") &&
66936694 !Mnemonic.startswith("vcvtm"))) {
508508 const void *Decoder);
509509 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn,
510510 uint64_t Address, const void *Decoder);
511 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val,
512 uint64_t Address, const void *Decoder);
513 template
514 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn,
515 uint64_t Address, const void *Decoder);
511516 static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn,
512517 uint64_t Address,
513518 const void *Decoder);
61826187
61836188 return S;
61846189 }
6190
6191 template
6192 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address,
6193 const void *Decoder) {
6194 DecodeStatus S = MCDisassembler::Success;
6195 Inst.addOperand(MCOperand::createReg(ARM::VPR));
6196 unsigned Qn = fieldFromInstruction(Insn, 17, 3);
6197 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
6198 return MCDisassembler::Fail;
6199
6200 unsigned fc;
6201
6202 if (scalar) {
6203 fc = fieldFromInstruction(Insn, 12, 1) << 2 |
6204 fieldFromInstruction(Insn, 7, 1) |
6205 fieldFromInstruction(Insn, 5, 1) << 1;
6206 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
6207 if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder)))
6208 return MCDisassembler::Fail;
6209 } else {
6210 fc = fieldFromInstruction(Insn, 12, 1) << 2 |
6211 fieldFromInstruction(Insn, 7, 1) |
6212 fieldFromInstruction(Insn, 0, 1) << 1;
6213 unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 |
6214 fieldFromInstruction(Insn, 1, 3);
6215 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
6216 return MCDisassembler::Fail;
6217 }
6218
6219 if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder)))
6220 return MCDisassembler::Fail;
6221
6222 Inst.addOperand(MCOperand::createImm(ARMVCC::None));
6223 Inst.addOperand(MCOperand::createReg(0));
6224 Inst.addOperand(MCOperand::createImm(0));
6225
6226 return S;
6227 }
0 # RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding < %s 2>%t \
1 # RUN: | FileCheck --check-prefix=CHECK-NOFP %s
2 # RUN: FileCheck --check-prefix=ERROR-NOFP < %t %s
3 # RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding < %s 2>%t \
4 # RUN: | FileCheck --check-prefix=CHECK %s
5 # RUN: FileCheck --check-prefix=ERROR < %t %s
6
7 # CHECK: vcmp.f16 eq, q0, q4 @ encoding: [0x31,0xfe,0x08,0x0f]
8 # ERROR-NOFP: [[@LINE+2]]:1: {{error|note}}: instruction requires: mve.fp
9 # CHECK-NOFP-NOT: vcmp.f16 eq, q0, q4 @ encoding: [0x31,0xfe,0x08,0x0f]
10 vcmp.f16 eq, q0, q4
11
12 # CHECK: vcmp.f16 ne, q2, q7 @ encoding: [0x35,0xfe,0x8e,0x0f]
13 # ERROR-NOFP: [[@LINE+2]]:1: {{error|note}}: instruction requires: mve.fp
14 # CHECK-NOFP-NOT: vcmp.f16 ne, q2, q7 @ encoding: [0x35,0xfe,0x8e,0x0f]
15 vcmp.f16 ne, q2, q7
16
17 # CHECK: vcmp.f16 ge, q0, q0 @ encoding: [0x31,0xfe,0x00,0x1f]
18 # ERROR-NOFP: [[@LINE+2]]:1: {{error|note}}: instruction requires: mve.fp
19 # CHECK-NOFP-NOT: vcmp.f16 ge, q0, q0 @ encoding: [0x31,0xfe,0x00,0x1f]
20 vcmp.f16 ge, q0, q0
21
22 # CHECK: vcmp.f16 lt, q0, q1 @ encoding: [0x31,0xfe,0x82,0x1f]
23 # ERROR-NOFP: [[@LINE+2]]:1: {{error|note}}: instruction requires: mve.fp
24 # CHECK-NOFP-NOT: vcmp.f16 lt, q0, q1 @ encoding: [0x31,0xfe,0x82,0x1f]
25 vcmp.f16 lt, q0, q1
26
27 # CHECK: vcmp.f16 gt, q1, q4 @ encoding: [0x33,0xfe,0x09,0x1f]
28 # ERROR-NOFP: [[@LINE+2]]:1: {{error|note}}: instruction requires: mve.fp
29 # CHECK-NOFP-NOT: vcmp.f16 gt, q1, q4 @ encoding: [0x33,0xfe,0x09,0x1f]
30 vcmp.f16 gt, q1, q4
31
32 # CHECK: vcmp.f16 le, q2, q6 @ encoding: [0x35,0xfe,0x8d,0x1f]
33 # ERROR-NOFP: [[@LINE+2]]:1: {{error|note}}: instruction requires: mve.fp
34 # CHECK-NOFP-NOT: vcmp.f16 le, q2, q6 @ encoding: [0x35,0xfe,0x8d,0x1f]
35 vcmp.f16 le, q2, q6
36
37 # ERROR: [[@LINE+1]]:10: {{error|note}}: condition code for floating-point comparison must be EQ, NE, LT, GT, LE or GE
38 vcmp.f16 hi, q2, q6
39
40 # ERROR: [[@LINE+1]]:10: {{error|note}}: condition code for floating-point comparison must be EQ, NE, LT, GT, LE or GE
41 vcmp.f16 hs, q2, q6
42
43 # CHECK: vcmp.f32 eq, q2, q5 @ encoding: [0x35,0xee,0x0a,0x0f]
44 # ERROR-NOFP: [[@LINE+2]]:1: {{error|note}}: instruction requires: mve.fp
45 # CHECK-NOFP-NOT: vcmp.f32 eq, q2, q5 @ encoding: [0x35,0xee,0x0a,0x0f]
46 vcmp.f32 eq, q2, q5
47
48 # CHECK: vcmp.f32 ne, q3, q4 @ encoding: [0x37,0xee,0x88,0x0f]
49 # ERROR-NOFP: [[@LINE+2]]:1: {{error|note}}: instruction requires: mve.fp
50 # CHECK-NOFP-NOT: vcmp.f32 ne, q3, q4 @ encoding: [0x37,0xee,0x88,0x0f]
51 vcmp.f32 ne, q3, q4
52
53 # CHECK: vcmp.f32 ge, q0, q7 @ encoding: [0x31,0xee,0x0e,0x1f]
54 # ERROR-NOFP: [[@LINE+2]]:1: {{error|note}}: instruction requires: mve.fp
55 # CHECK-NOFP-NOT: vcmp.f32 ge, q0, q7 @ encoding: [0x31,0xee,0x0e,0x1f]
56 vcmp.f32 ge, q0, q7
57
58 # CHECK: vcmp.f32 lt, q5, q2 @ encoding: [0x3b,0xee,0x84,0x1f]
59 # ERROR-NOFP: [[@LINE+2]]:1: {{error|note}}: instruction requires: mve.fp
60 # CHECK-NOFP-NOT: vcmp.f32 lt, q5, q2 @ encoding: [0x3b,0xee,0x84,0x1f]
61 vcmp.f32 lt, q5, q2
62
63 # CHECK: vcmp.f32 gt, q2, q7 @ encoding: [0x35,0xee,0x0f,0x1f]
64 # ERROR-NOFP: [[@LINE+2]]:1: {{error|note}}: instruction requires: mve.fp
65 # CHECK-NOFP-NOT: vcmp.f32 gt, q2, q7 @ encoding: [0x35,0xee,0x0f,0x1f]
66 vcmp.f32 gt, q2, q7
67
68 # CHECK: vcmp.f32 le, q2, q4 @ encoding: [0x35,0xee,0x89,0x1f]
69 # ERROR-NOFP: [[@LINE+2]]:1: {{error|note}}: instruction requires: mve.fp
70 # CHECK-NOFP-NOT: vcmp.f32 le, q2, q4 @ encoding: [0x35,0xee,0x89,0x1f]
71 vcmp.f32 le, q2, q4
72
73 # ERROR: [[@LINE+1]]:10: {{error|note}}: condition code for floating-point comparison must be EQ, NE, LT, GT, LE or GE
74 vcmp.f32 hi, q2, q6
75
76 # ERROR: [[@LINE+1]]:10: {{error|note}}: condition code for floating-point comparison must be EQ, NE, LT, GT, LE or GE
77 vcmp.f32 hs, q2, q6
78
79 # CHECK: vcmp.i8 eq, q4, q6 @ encoding: [0x09,0xfe,0x0c,0x0f]
80 # CHECK-NOFP: vcmp.i8 eq, q4, q6 @ encoding: [0x09,0xfe,0x0c,0x0f]
81 vcmp.i8 eq, q4, q6
82
83 # CHECK: vcmp.i8 ne, q2, q2 @ encoding: [0x05,0xfe,0x84,0x0f]
84 # CHECK-NOFP: vcmp.i8 ne, q2, q2 @ encoding: [0x05,0xfe,0x84,0x0f]
85 vcmp.i8 ne, q2, q2
86
87 # ERROR: [[@LINE+1]]:9: {{error|note}}: condition code for sign-independent integer comparison must be EQ or NE
88 vcmp.i8 hs, q2, q6
89
90 # ERROR: [[@LINE+1]]:9: {{error|note}}: condition code for sign-independent integer comparison must be EQ or NE
91 vcmp.i8 le, q2, q6
92
93 # CHECK: vcmp.i8 eq, q4, q6 @ encoding: [0x09,0xfe,0x0c,0x0f]
94 # CHECK-NOFP: vcmp.i8 eq, q4, q6 @ encoding: [0x09,0xfe,0x0c,0x0f]
95 vcmp.s8 eq, q4, q6
96
97 # CHECK: vcmp.i8 ne, q2, q2 @ encoding: [0x05,0xfe,0x84,0x0f]
98 # CHECK-NOFP: vcmp.i8 ne, q2, q2 @ encoding: [0x05,0xfe,0x84,0x0f]
99 vcmp.s8 ne, q2, q2
100
101 # CHECK: vcmp.i8 eq, q4, q6 @ encoding: [0x09,0xfe,0x0c,0x0f]
102 # CHECK-NOFP: vcmp.i8 eq, q4, q6 @ encoding: [0x09,0xfe,0x0c,0x0f]
103 vcmp.u8 eq, q4, q6
104
105 # CHECK: vcmp.i8 ne, q2, q2 @ encoding: [0x05,0xfe,0x84,0x0f]
106 # CHECK-NOFP: vcmp.i8 ne, q2, q2 @ encoding: [0x05,0xfe,0x84,0x0f]
107 vcmp.u8 ne, q2, q2
108
109 # CHECK: vcmp.s8 ge, q0, q0 @ encoding: [0x01,0xfe,0x00,0x1f]
110 # CHECK-NOFP: vcmp.s8 ge, q0, q0 @ encoding: [0x01,0xfe,0x00,0x1f]
111 vcmp.s8 ge, q0, q0
112
113 # CHECK: vcmp.s8 lt, q2, q7 @ encoding: [0x05,0xfe,0x8e,0x1f]
114 # CHECK-NOFP: vcmp.s8 lt, q2, q7 @ encoding: [0x05,0xfe,0x8e,0x1f]
115 vcmp.s8 lt, q2, q7
116
117 # CHECK: vcmp.s8 gt, q4, q3 @ encoding: [0x09,0xfe,0x07,0x1f]
118 # CHECK-NOFP: vcmp.s8 gt, q4, q3 @ encoding: [0x09,0xfe,0x07,0x1f]
119 vcmp.s8 gt, q4, q3
120
121 # CHECK: vcmp.s8 le, q7, q3 @ encoding: [0x0f,0xfe,0x87,0x1f]
122 # CHECK-NOFP: vcmp.s8 le, q7, q3 @ encoding: [0x0f,0xfe,0x87,0x1f]
123 vcmp.s8 le, q7, q3
124
125 # ERROR: [[@LINE+1]]:9: {{error|note}}: condition code for signed integer comparison must be EQ, NE, LT, GT, LE or GE
126 vcmp.s8 hs, q2, q6
127
128 # CHECK: vcmp.u8 hi, q1, q4 @ encoding: [0x03,0xfe,0x89,0x0f]
129 # CHECK-NOFP: vcmp.u8 hi, q1, q4 @ encoding: [0x03,0xfe,0x89,0x0f]
130 vcmp.u8 hi, q1, q4
131
132 # CHECK: vcmp.u8 cs, q1, q4 @ encoding: [0x03,0xfe,0x09,0x0f]
133 # CHECK-NOFP: vcmp.u8 cs, q1, q4 @ encoding: [0x03,0xfe,0x09,0x0f]
134 vcmp.u8 cs, q1, q4
135
136 # ERROR: [[@LINE+1]]:9: {{error|note}}: condition code for unsigned integer comparison must be EQ, NE, HS or HI
137 vcmp.u8 gt, q2, q6
138
139 # ERROR: [[@LINE+1]]:9: {{error|note}}: condition code for unsigned integer comparison must be EQ, NE, HS or HI
140 vcmp.u8 lo, q2, q6
141
142 # CHECK: vcmp.i16 eq, q4, q7 @ encoding: [0x19,0xfe,0x0e,0x0f]
143 # CHECK-NOFP: vcmp.i16 eq, q4, q7 @ encoding: [0x19,0xfe,0x0e,0x0f]
144 vcmp.i16 eq, q4, q7
145
146 # CHECK: vcmp.i16 ne, q2, q1 @ encoding: [0x15,0xfe,0x82,0x0f]
147 # CHECK-NOFP: vcmp.i16 ne, q2, q1 @ encoding: [0x15,0xfe,0x82,0x0f]
148 vcmp.i16 ne, q2, q1
149
150 # ERROR: [[@LINE+1]]:10: {{error|note}}: condition code for sign-independent integer comparison must be EQ or NE
151 vcmp.i16 hi, q2, q6
152
153 # ERROR: [[@LINE+1]]:10: {{error|note}}: condition code for sign-independent integer comparison must be EQ or NE
154 vcmp.i16 lt, q2, q6
155
156 # CHECK: vcmp.s16 ge, q1, q7 @ encoding: [0x13,0xfe,0x0e,0x1f]
157 # CHECK-NOFP: vcmp.s16 ge, q1, q7 @ encoding: [0x13,0xfe,0x0e,0x1f]
158 vcmp.s16 ge, q1, q7
159
160 # CHECK: vcmp.s16 lt, q0, q1 @ encoding: [0x11,0xfe,0x82,0x1f]
161 # CHECK-NOFP: vcmp.s16 lt, q0, q1 @ encoding: [0x11,0xfe,0x82,0x1f]
162 vcmp.s16 lt, q0, q1
163
164 # CHECK: vcmp.s16 gt, q1, q7 @ encoding: [0x13,0xfe,0x0f,0x1f]
165 # CHECK-NOFP: vcmp.s16 gt, q1, q7 @ encoding: [0x13,0xfe,0x0f,0x1f]
166 vcmp.s16 gt, q1, q7
167
168 # CHECK: vcmp.s16 le, q2, q1 @ encoding: [0x15,0xfe,0x83,0x1f]
169 # CHECK-NOFP: vcmp.s16 le, q2, q1 @ encoding: [0x15,0xfe,0x83,0x1f]
170 vcmp.s16 le, q2, q1
171
172 # ERROR: [[@LINE+1]]:10: {{error|note}}: condition code for signed integer comparison must be EQ, NE, LT, GT, LE or GE
173 vcmp.s16 hi, q2, q6
174
175 # CHECK: vcmp.u16 hi, q1, q4 @ encoding: [0x13,0xfe,0x89,0x0f]
176 # CHECK-NOFP: vcmp.u16 hi, q1, q4 @ encoding: [0x13,0xfe,0x89,0x0f]
177 vcmp.u16 hi, q1, q4
178
179 # CHECK: vcmp.u16 cs, q1, q4 @ encoding: [0x13,0xfe,0x09,0x0f]
180 # CHECK-NOFP: vcmp.u16 cs, q1, q4 @ encoding: [0x13,0xfe,0x09,0x0f]
181 vcmp.u16 cs, q1, q4
182
183 # ERROR: [[@LINE+1]]:10: {{error|note}}: condition code for unsigned integer comparison must be EQ, NE, HS or HI
184 vcmp.u16 ge, q2, q6
185
186 # ERROR: [[@LINE+1]]:10: {{error|note}}: condition code for unsigned integer comparison must be EQ, NE, HS or HI
187 vcmp.u16 ls, q2, q6
188
189 # CHECK: vcmp.i32 eq, q2, q7 @ encoding: [0x25,0xfe,0x0e,0x0f]
190 # CHECK-NOFP: vcmp.i32 eq, q2, q7 @ encoding: [0x25,0xfe,0x0e,0x0f]
191 vcmp.i32 eq, q2, q7
192
193 # CHECK: vcmp.i32 ne, q2, q4 @ encoding: [0x25,0xfe,0x88,0x0f]
194 # CHECK-NOFP: vcmp.i32 ne, q2, q4 @ encoding: [0x25,0xfe,0x88,0x0f]
195 vcmp.i32 ne, q2, q4
196
197 # ERROR: [[@LINE+1]]:10: {{error|note}}: condition code for sign-independent integer comparison must be EQ or NE
198 vcmp.i32 lo, q2, q6
199
200 # ERROR: [[@LINE+1]]:10: {{error|note}}: condition code for sign-independent integer comparison must be EQ or NE
201 vcmp.i32 ge, q2, q6
202
203 # CHECK: vcmp.s32 ge, q5, q5 @ encoding: [0x2b,0xfe,0x0a,0x1f]
204 # CHECK-NOFP: vcmp.s32 ge, q5, q5 @ encoding: [0x2b,0xfe,0x0a,0x1f]
205 vcmp.s32 ge, q5, q5
206
207 # CHECK: vcmp.s32 lt, q2, q2 @ encoding: [0x25,0xfe,0x84,0x1f]
208 # CHECK-NOFP: vcmp.s32 lt, q2, q2 @ encoding: [0x25,0xfe,0x84,0x1f]
209 vcmp.s32 lt, q2, q2
210
211 # CHECK: vcmp.s32 gt, q0, q1 @ encoding: [0x21,0xfe,0x03,0x1f]
212 # CHECK-NOFP: vcmp.s32 gt, q0, q1 @ encoding: [0x21,0xfe,0x03,0x1f]
213 vcmp.s32 gt, q0, q1
214
215 # CHECK: vcmp.s32 le, q5, q4 @ encoding: [0x2b,0xfe,0x89,0x1f]
216 # CHECK-NOFP: vcmp.s32 le, q5, q4 @ encoding: [0x2b,0xfe,0x89,0x1f]
217 vcmp.s32 le, q5, q4
218
219 # ERROR: [[@LINE+1]]:10: {{error|note}}: condition code for signed integer comparison must be EQ, NE, LT, GT, LE or GE
220 vcmp.s32 ls, q2, q6
221
222 # CHECK: vcmp.u32 hi, q1, q4 @ encoding: [0x23,0xfe,0x89,0x0f]
223 # CHECK-NOFP: vcmp.u32 hi, q1, q4 @ encoding: [0x23,0xfe,0x89,0x0f]
224 vcmp.u32 hi, q1, q4
225
226 # CHECK: vcmp.u32 cs, q1, q4 @ encoding: [0x23,0xfe,0x09,0x0f]
227 # CHECK-NOFP: vcmp.u32 cs, q1, q4 @ encoding: [0x23,0xfe,0x09,0x0f]
228 vcmp.u32 cs, q1, q4
229
230 # ERROR: [[@LINE+1]]:10: {{error|note}}: condition code for unsigned integer comparison must be EQ, NE, HS or HI
231 vcmp.u32 vs, q2, q6
232
233 # ERROR: [[@LINE+1]]:10: {{error|note}}: condition code for unsigned integer comparison must be EQ, NE, HS or HI
234 vcmp.u32 mi, q2, q6
235
236 # CHECK: vcmp.f16 gt, q4, zr @ encoding: [0x39,0xfe,0x6f,0x1f]
237 # ERROR-NOFP: [[@LINE+2]]:1: {{error|note}}: instruction requires: mve.fp
238 # CHECK-NOFP-NOT: vcmp.f16 gt, q4, zr @ encoding: [0x39,0xfe,0x6f,0x1f]
239 vcmp.f16 gt, q4, zr
240
241 # CHECK: vcmp.f16 eq, q4, r12 @ encoding: [0x39,0xfe,0x4c,0x0f]
242 # ERROR-NOFP: [[@LINE+2]]:1: {{error|note}}: instruction requires: mve.fp
243 # CHECK-NOFP-NOT: vcmp.f16 eq, q4, r12 @ encoding: [0x39,0xfe,0x4c,0x0f]
244 vcmp.f16 eq, q4, r12
245
246 # CHECK: vcmp.f32 ne, q3, r0 @ encoding: [0x37,0xee,0xc0,0x0f]
247 # ERROR-NOFP: [[@LINE+2]]:1: {{error|note}}: instruction requires: mve.fp
248 # CHECK-NOFP-NOT: vcmp.f32 ne, q3, r0 @ encoding: [0x37,0xee,0xc0,0x0f]
249 vcmp.f32 ne, q3, r0
250
251 # CHECK: vcmp.i8 eq, q1, r0 @ encoding: [0x03,0xfe,0x40,0x0f]
252 # CHECK-NOFP: vcmp.i8 eq, q1, r0 @ encoding: [0x03,0xfe,0x40,0x0f]
253 vcmp.i8 eq, q1, r0
254
255 # CHECK: vcmp.s8 le, q1, r0 @ encoding: [0x03,0xfe,0xe0,0x1f]
256 # CHECK-NOFP: vcmp.s8 le, q1, r0 @ encoding: [0x03,0xfe,0xe0,0x1f]
257 vcmp.s8 le, q1, r0
258
259 # CHECK: vcmp.u8 cs, q1, r0 @ encoding: [0x03,0xfe,0x60,0x0f]
260 # CHECK-NOFP: vcmp.u8 cs, q1, r0 @ encoding: [0x03,0xfe,0x60,0x0f]
261 vcmp.u8 cs, q1, r0
262
263 # CHECK: vcmp.i16 eq, q5, r10 @ encoding: [0x1b,0xfe,0x4a,0x0f]
264 # CHECK-NOFP: vcmp.i16 eq, q5, r10 @ encoding: [0x1b,0xfe,0x4a,0x0f]
265 vcmp.i16 eq, q5, r10
266
267 # CHECK: vcmp.i32 eq, q1, r4 @ encoding: [0x23,0xfe,0x44,0x0f]
268 # CHECK-NOFP: vcmp.i32 eq, q1, r4 @ encoding: [0x23,0xfe,0x44,0x0f]
269 vcmp.i32 eq, q1, r4
270
271 vpste
272 vcmpt.i8 eq, q0, r0
273 vcmpe.i16 ne, q0, r0
274 # CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
275 # CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
276 # CHECK: vcmpt.i8 eq, q0, r0 @ encoding: [0x01,0xfe,0x40,0x0f]
277 # CHECK-NOFP: vcmpt.i8 eq, q0, r0 @ encoding: [0x01,0xfe,0x40,0x0f]
278 # CHECK: vcmpe.i16 ne, q0, r0 @ encoding: [0x11,0xfe,0xc0,0x0f]
279 # CHECK-NOFP: vcmpe.i16 ne, q0, r0 @ encoding: [0x11,0xfe,0xc0,0x0f]
280
281 # Ensure the scalar FP instructions VCMP and VCMPE are still correctly
282 # distinguished, in spite of VCMPE sometimes being a VPT-suffixed
283 # version of VCMP with identical encoding.
284 vcmp.f16 s0,s1
285 vcmpe.f16 s0,s1
286 # CHECK: vcmp.f16 s0, s1 @ encoding: [0xb4,0xee,0x60,0x09]
287 # CHECK: vcmpe.f16 s0, s1 @ encoding: [0xb4,0xee,0xe0,0x09]
288 # CHECK-NOFP-NOT: vcmp.f16 s0, s1 @ encoding: [0xb4,0xee,0x60,0x09]
289 # CHECK-NOFP-NOT: vcmpe.f16 s0, s1 @ encoding: [0xb4,0xee,0xe0,0x09]
290
291 itt eq
292 vcmpeq.f32 s0, s1
293 vcmpeeq.f32 s0, s1
294 # CHECK: itt eq @ encoding: [0x04,0xbf]
295 # CHECK: vcmpeq.f32 s0, s1 @ encoding: [0xb4,0xee,0x60,0x0a]
296 # CHECK-NOFP-NOT: vcmpeq.f32 s0, s1 @ encoding: [0xb4,0xee,0x60,0x0a]
297 # CHECK: vcmpeeq.f32 s0, s1 @ encoding: [0xb4,0xee,0xe0,0x0a]
298 # CHECK-NOFP-NOT: vcmpeeq.f32 s0, s1 @ encoding: [0xb4,0xee,0xe0,0x0a]
0 # RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s | FileCheck %s
1 # RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t
2 # RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s
3
4 # CHECK: vcmp.f16 eq, q0, q4 @ encoding: [0x31,0xfe,0x08,0x0f]
5 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
6 [0x31,0xfe,0x08,0x0f]
7
8 # CHECK: vcmp.f16 ne, q2, q7 @ encoding: [0x35,0xfe,0x8e,0x0f]
9 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
10 [0x35,0xfe,0x8e,0x0f]
11
12 # CHECK: vcmp.f16 ge, q0, q0 @ encoding: [0x31,0xfe,0x00,0x1f]
13 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
14 [0x31,0xfe,0x00,0x1f]
15
16 # CHECK: vcmp.f16 lt, q0, q1 @ encoding: [0x31,0xfe,0x82,0x1f]
17 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
18 [0x31,0xfe,0x82,0x1f]
19
20 # CHECK: vcmp.f16 gt, q1, q4 @ encoding: [0x33,0xfe,0x09,0x1f]
21 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
22 [0x33,0xfe,0x09,0x1f]
23
24 # CHECK: vcmp.f16 le, q2, q6 @ encoding: [0x35,0xfe,0x8d,0x1f]
25 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
26 [0x35,0xfe,0x8d,0x1f]
27
28 # CHECK: vcmp.f32 eq, q2, q5 @ encoding: [0x35,0xee,0x0a,0x0f]
29 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
30 [0x35,0xee,0x0a,0x0f]
31
32 # CHECK: vcmp.f32 ne, q3, q4 @ encoding: [0x37,0xee,0x88,0x0f]
33 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
34 [0x37,0xee,0x88,0x0f]
35
36 # CHECK: vcmp.f32 ge, q0, q7 @ encoding: [0x31,0xee,0x0e,0x1f]
37 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
38 [0x31,0xee,0x0e,0x1f]
39
40 # CHECK: vcmp.f32 lt, q5, q2 @ encoding: [0x3b,0xee,0x84,0x1f]
41 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
42 [0x3b,0xee,0x84,0x1f]
43
44 # CHECK: vcmp.f32 gt, q2, q7 @ encoding: [0x35,0xee,0x0f,0x1f]
45 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
46 [0x35,0xee,0x0f,0x1f]
47
48 # CHECK: vcmp.f32 le, q2, q4 @ encoding: [0x35,0xee,0x89,0x1f]
49 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
50 [0x35,0xee,0x89,0x1f]
51
52 # CHECK: vcmp.i8 eq, q4, q6 @ encoding: [0x09,0xfe,0x0c,0x0f]
53 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
54 [0x09,0xfe,0x0c,0x0f]
55
56 # CHECK: vcmp.i8 ne, q2, q2 @ encoding: [0x05,0xfe,0x84,0x0f]
57 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
58 [0x05,0xfe,0x84,0x0f]
59
60 # CHECK: vcmp.s8 ge, q0, q0 @ encoding: [0x01,0xfe,0x00,0x1f]
61 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
62 [0x01,0xfe,0x00,0x1f]
63
64 # CHECK: vcmp.s8 lt, q2, q7 @ encoding: [0x05,0xfe,0x8e,0x1f]
65 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
66 [0x05,0xfe,0x8e,0x1f]
67
68 # CHECK: vcmp.s8 gt, q4, q3 @ encoding: [0x09,0xfe,0x07,0x1f]
69 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
70 [0x09,0xfe,0x07,0x1f]
71
72 # CHECK: vcmp.s8 le, q7, q3 @ encoding: [0x0f,0xfe,0x87,0x1f]
73 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
74 [0x0f,0xfe,0x87,0x1f]
75
76 # CHECK: vcmp.u8 hi, q1, q4 @ encoding: [0x03,0xfe,0x89,0x0f]
77 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
78 [0x03,0xfe,0x89,0x0f]
79
80 # CHECK: vcmp.u8 cs, q1, q4 @ encoding: [0x03,0xfe,0x09,0x0f]
81 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
82 [0x03,0xfe,0x09,0x0f]
83
84 # CHECK: vcmp.i16 eq, q4, q7 @ encoding: [0x19,0xfe,0x0e,0x0f]
85 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
86 [0x19,0xfe,0x0e,0x0f]
87
88 # CHECK: vcmp.i16 ne, q2, q1 @ encoding: [0x15,0xfe,0x82,0x0f]
89 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
90 [0x15,0xfe,0x82,0x0f]
91
92 # CHECK: vcmp.s16 ge, q1, q7 @ encoding: [0x13,0xfe,0x0e,0x1f]
93 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
94 [0x13,0xfe,0x0e,0x1f]
95
96 # CHECK: vcmp.s16 lt, q0, q1 @ encoding: [0x11,0xfe,0x82,0x1f]
97 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
98 [0x11,0xfe,0x82,0x1f]
99
100 # CHECK: vcmp.s16 gt, q1, q7 @ encoding: [0x13,0xfe,0x0f,0x1f]
101 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
102 [0x13,0xfe,0x0f,0x1f]
103
104 # CHECK: vcmp.s16 le, q2, q1 @ encoding: [0x15,0xfe,0x83,0x1f]
105 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
106 [0x15,0xfe,0x83,0x1f]
107
108 # CHECK: vcmp.u16 hi, q1, q4 @ encoding: [0x13,0xfe,0x89,0x0f]
109 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
110 [0x13,0xfe,0x89,0x0f]
111
112 # CHECK: vcmp.u16 cs, q1, q4 @ encoding: [0x13,0xfe,0x09,0x0f]
113 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
114 [0x13,0xfe,0x09,0x0f]
115
116 # CHECK: vcmp.i32 eq, q2, q7 @ encoding: [0x25,0xfe,0x0e,0x0f]
117 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
118 [0x25,0xfe,0x0e,0x0f]
119
120 # CHECK: vcmp.i32 ne, q2, q4 @ encoding: [0x25,0xfe,0x88,0x0f]
121 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
122 [0x25,0xfe,0x88,0x0f]
123
124 # CHECK: vcmp.s32 ge, q5, q5 @ encoding: [0x2b,0xfe,0x0a,0x1f]
125 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
126 [0x2b,0xfe,0x0a,0x1f]
127
128 # CHECK: vcmp.s32 lt, q2, q2 @ encoding: [0x25,0xfe,0x84,0x1f]
129 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
130 [0x25,0xfe,0x84,0x1f]
131
132 # CHECK: vcmp.s32 gt, q0, q1 @ encoding: [0x21,0xfe,0x03,0x1f]
133 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
134 [0x21,0xfe,0x03,0x1f]
135
136 # CHECK: vcmp.s32 le, q5, q4 @ encoding: [0x2b,0xfe,0x89,0x1f]
137 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
138 [0x2b,0xfe,0x89,0x1f]
139
140 # CHECK: vcmp.u32 hi, q1, q4 @ encoding: [0x23,0xfe,0x89,0x0f]
141 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
142 [0x23,0xfe,0x89,0x0f]
143
144 # CHECK: vcmp.u32 cs, q1, q4 @ encoding: [0x23,0xfe,0x09,0x0f]
145 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
146 [0x23,0xfe,0x09,0x0f]
147
148 # CHECK: vcmp.f16 gt, q4, zr @ encoding: [0x39,0xfe,0x6f,0x1f]
149 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
150 [0x39,0xfe,0x6f,0x1f]
151
152 # CHECK: vcmp.f16 eq, q4, r12 @ encoding: [0x39,0xfe,0x4c,0x0f]
153 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
154 [0x39,0xfe,0x4c,0x0f]
155
156 # CHECK: vcmp.f32 ne, q3, r0 @ encoding: [0x37,0xee,0xc0,0x0f]
157 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
158 [0x37,0xee,0xc0,0x0f]
159
160 # CHECK: vcmp.i8 eq, q1, r0 @ encoding: [0x03,0xfe,0x40,0x0f]
161 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
162 [0x03,0xfe,0x40,0x0f]
163
164 # CHECK: vcmp.s8 le, q1, r0 @ encoding: [0x03,0xfe,0xe0,0x1f]
165 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
166 [0x03,0xfe,0xe0,0x1f]
167
168 # CHECK: vcmp.u8 cs, q1, r0 @ encoding: [0x03,0xfe,0x60,0x0f]
169 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
170 [0x03,0xfe,0x60,0x0f]
171
172 # CHECK: vcmp.i16 eq, q5, r10 @ encoding: [0x1b,0xfe,0x4a,0x0f]
173 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
174 [0x1b,0xfe,0x4a,0x0f]
175
176 # CHECK: vcmp.i32 eq, q1, r4 @ encoding: [0x23,0xfe,0x44,0x0f]
177 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
178 [0x23,0xfe,0x44,0x0f]