llvm.org GIT mirror llvm / c9e5015
Add a TRI::getLargestLegalSuperClass hook to provide an upper limit on register class inflation. The hook will be used by the register allocator when recomputing register classes after removing constraints. Thumb1 code doesn't allow anything larger than tGPR, and x86 needs to ensure that the spill size doesn't change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130228 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 9 years ago
7 changed file(s) with 74 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
603603 return RC;
604604 }
605605
606 /// getLargestLegalSuperClass - Returns the largest super class of RC that is
607 /// legal to use in the current sub-target and has the same spill size.
608 /// The returned register class can be used to create virtual registers which
609 /// means that all its registers can be copied and spilled.
610 virtual const TargetRegisterClass*
611 getLargestLegalSuperClass(const TargetRegisterClass *RC) const {
612 /// The default implementation is very conservative and doesn't allow the
613 /// register allocator to inflate register classes.
614 return RC;
615 }
616
606617 /// getRegPressureLimit - Return the register pressure "high water mark" for
607618 /// the specific register class. The scheduler is in high register pressure
608619 /// mode (for the specific register class) if it goes over the limit.
341341 return false;
342342 }
343343
344 const TargetRegisterClass*
345 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
346 const {
347 const TargetRegisterClass *Super = RC;
348 TargetRegisterClass::sc_iterator I = RC->superclasses_begin();
349 do {
350 switch (Super->getID()) {
351 case ARM::GPRRegClassID:
352 case ARM::SPRRegClassID:
353 case ARM::DPRRegClassID:
354 case ARM::QPRRegClassID:
355 case ARM::QQPRRegClassID:
356 case ARM::QQQQPRRegClassID:
357 return Super;
358 }
359 Super = *I++;
360 } while (Super);
361 return RC;
362 }
344363
345364 const TargetRegisterClass *
346365 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
126126 unsigned &NewSubIdx) const;
127127
128128 const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
129
130 const TargetRegisterClass*
131 getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
129132
130133 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
131134 MachineFunction &MF) const;
4343 Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii,
4444 const ARMSubtarget &sti)
4545 : ARMBaseRegisterInfo(tii, sti) {
46 }
47
48 const TargetRegisterClass*
49 Thumb1RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
50 const {
51 if (RC == ARM::tGPRRegisterClass || RC->hasSuperClass(ARM::tGPRRegisterClass))
52 return ARM::tGPRRegisterClass;
53 return ARMBaseRegisterInfo::getLargestLegalSuperClass(RC);
4654 }
4755
4856 const TargetRegisterClass *
2626 struct Thumb1RegisterInfo : public ARMBaseRegisterInfo {
2727 public:
2828 Thumb1RegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
29
30 const TargetRegisterClass*
31 getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
2932
3033 const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
3134
305305 break;
306306 }
307307 return 0;
308 }
309
310 const TargetRegisterClass*
311 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
312 const TargetRegisterClass *Super = RC;
313 TargetRegisterClass::sc_iterator I = RC->superclasses_begin();
314 do {
315 switch (Super->getID()) {
316 case X86::GR8RegClassID:
317 case X86::GR16RegClassID:
318 case X86::GR32RegClassID:
319 case X86::GR64RegClassID:
320 case X86::FR32RegClassID:
321 case X86::FR64RegClassID:
322 case X86::RFP32RegClassID:
323 case X86::RFP64RegClassID:
324 case X86::RFP80RegClassID:
325 case X86::VR128RegClassID:
326 case X86::VR256RegClassID:
327 // Don't return a super-class that would shrink the spill size.
328 // That can happen with the vector and float classes.
329 if (Super->getSize() == RC->getSize())
330 return Super;
331 }
332 Super = *I++;
333 } while (Super);
334 return RC;
308335 }
309336
310337 const TargetRegisterClass *
9090 getMatchingSuperRegClass(const TargetRegisterClass *A,
9191 const TargetRegisterClass *B, unsigned Idx) const;
9292
93 const TargetRegisterClass*
94 getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
95
9396 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
9497 /// values.
9598 const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;