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[PowerPC] v2[fi]64 need to be explicitly passed in VSX registers v2[fi]64 values need to be explicitly passed in VSX registers. This is because the code in TRI that finds the minimal register class given a register and a value type will assert if given an Altivec register and a non-Altivec type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205041 91177308-0d34-0410-b5e6-96231b3b80d8 Hal Finkel 6 years ago
3 changed file(s) with 62 addition(s) and 7 deletion(s). Raw diff Collapse all Expand all
3535 CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4]>>,
3636
3737 // Vector types are always returned in V2.
38 CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64], CCAssignToReg<[V2]>>
38 CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToReg<[V2]>>,
39 CCIfType<[v2f64, v2i64], CCAssignToReg<[VSH2]>>
3940 ]>;
4041
4142
6970 CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,
7071 CCIfType<[f32], CCAssignToReg<[F1, F2]>>,
7172 CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4]>>,
72 CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64], CCAssignToReg<[V2]>>
73 CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToReg<[V2]>>,
74 CCIfType<[v2f64, v2i64], CCAssignToReg<[VSH2]>>
7375 ]>;
7476
7577 //===----------------------------------------------------------------------===//
117119 // put vector arguments in vector registers before putting them on the stack.
118120 def CC_PPC32_SVR4 : CallingConv<[
119121 // The first 12 Vector arguments are passed in AltiVec registers.
120 CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64],
122 CCIfType<[v16i8, v8i16, v4i32, v4f32],
121123 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13]>>,
124 CCIfType<[v2f64, v2i64],
125 CCAssignToReg<[VSH2, VSH3, VSH4, VSH5, VSH6, VSH7, VSH8, VSH9,
126 VSH10, VSH11, VSH12, VSH13]>>,
122127
123128 CCDelegateTo
124129 ]>;
21612161 case MVT::v8i16:
21622162 case MVT::v4i32:
21632163 case MVT::v4f32:
2164 RC = &PPC::VRRCRegClass;
2165 break;
21642166 case MVT::v2f64:
21652167 case MVT::v2i64:
2166 RC = &PPC::VRRCRegClass;
2168 RC = &PPC::VSHRCRegClass;
21672169 break;
21682170 }
21692171
23792381 static const uint16_t VR[] = {
23802382 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
23812383 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2384 };
2385 static const uint16_t VSRH[] = {
2386 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2387 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
23822388 };
23832389
23842390 const unsigned Num_GPR_Regs = array_lengthof(GPR);
25722578 // Note that vector arguments in registers don't reserve stack space,
25732579 // except in varargs functions.
25742580 if (VR_idx != Num_VR_Regs) {
2575 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2581 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2582 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2583 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
25762584 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
25772585 if (isVarArg) {
25782586 while ((ArgOffset % 16) != 0) {
40104018 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
40114019 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
40124020 };
4021 static const uint16_t VSRH[] = {
4022 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4023 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4024 };
4025
40134026 const unsigned NumGPRs = array_lengthof(GPR);
40144027 const unsigned NumFPRs = 13;
40154028 const unsigned NumVRs = array_lengthof(VR);
42414254 MachinePointerInfo(),
42424255 false, false, false, 0);
42434256 MemOpChains.push_back(Load.getValue(1));
4244 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4257
4258 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4259 Arg.getSimpleValueType() == MVT::v2i64) ?
4260 VSRH[VR_idx] : VR[VR_idx];
4261 ++VR_idx;
4262
4263 RegsToPass.push_back(std::make_pair(VReg, Load));
42454264 }
42464265 ArgOffset += 16;
42474266 for (unsigned i=0; i<16; i+=PtrByteSize) {
42614280 // stack space allocated at the end.
42624281 if (VR_idx != NumVRs) {
42634282 // Doesn't have GPR space allocated.
4264 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4283 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4284 Arg.getSimpleValueType() == MVT::v2i64) ?
4285 VSRH[VR_idx] : VR[VR_idx];
4286 ++VR_idx;
4287
4288 RegsToPass.push_back(std::make_pair(VReg, Arg));
42654289 } else {
42664290 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
42674291 true, isTailCall, true, MemOpChains,
0 ; RUN: llc < %s -mcpu=pwr7 -mattr=+vsx | FileCheck %s
1 target datalayout = "E-m:e-i64:64-n32:64"
2 target triple = "powerpc64-unknown-linux-gnu"
3
4 declare <2 x double> @sv(<2 x double>, <2 x i64>, <4 x float>) #0
5
6 define <2 x double> @main(<4 x float> %a, <2 x double> %b, <2 x i64> %c) #1 {
7 entry:
8 %ca = tail call <2 x double> @sv(<2 x double> %b, <2 x i64> %c, <4 x float> %a)
9 %v = fadd <2 x double> %ca,
10 ret <2 x double> %v
11
12 ; CHECK-LABEL: @main
13 ; CHECK-DAG: vor [[V:[0-9]+]], 2, 2
14 ; CHECK-DAG: xxlor 34, 35, 35
15 ; CHECK-DAG: xxlor 35, 36, 36
16 ; CHECK-DAG: vor 4, [[V]], [[V]]
17 ; CHECK-DAG: bl sv
18 ; CHECK-DAG: lxvd2x [[VC:[0-9]+]],
19 ; CHECK: xvadddp 34, 34, [[VC]]
20 ; CHECK: blr
21 }
22
23 attributes #0 = { noinline nounwind readnone }
24 attributes #1 = { nounwind }
25