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[PowerPC] PR19796: Also match ISD::TargetConstant in isIntS16Immediate The SplitIndexingFromLoad changes exposed a latent isel bug in the PowerPC64 backend. We matched an immediate offset with STWX8 even though it only supports register offset. The culprit is the complex-pattern predicate, SelectAddrIdx, which decides that if the offset is not ISD::Constant it must be a register. Many thanks to Bill Schmidt for testing this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209219 91177308-0d34-0410-b5e6-96231b3b80d8 Adam Nemet 6 years ago
2 changed file(s) with 23 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
11361136 /// sign extension from a 16-bit value. If so, this returns true and the
11371137 /// immediate.
11381138 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1139 if (N->getOpcode() != ISD::Constant)
1139 if (!isa(N))
11401140 return false;
11411141
11421142 Imm = (short)cast(N)->getZExtValue();
0 ; RUN: llc < %s | FileCheck %s
1
2 ; The SplitIndexingFromLoad tranformation exposed an isel backend bug. This
3 ; testcase used to generate stwx 4, 3, 64. stwx does not have an
4 ; immediate-offset format (note the 64) and it should not be matched.
5
6 target datalayout = "e-m:e-i64:64-n32:64"
7 target triple = "powerpc64le-unknown-linux-gnu"
8
9 %class.test = type { [64 x i8], [5 x i8] }
10
11 ; CHECK-LABEL: f:
12 ; CHECK-NOT: stwx {{[0-9]+}}, {{[0-9]+}}, 64
13 define void @f(%class.test* %this) {
14 entry:
15 %Subminor.i.i = getelementptr inbounds %class.test* %this, i64 0, i32 1
16 %0 = bitcast [5 x i8]* %Subminor.i.i to i40*
17 %bf.load2.i.i = load i40* %0, align 4
18 %bf.clear7.i.i = and i40 %bf.load2.i.i, -8589934592
19 store i40 %bf.clear7.i.i, i40* %0, align 4
20 ret void
21 }