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MIR Serialization: Serialize simple MachineRegisterInfo attributes. This commit serializes the 3 scalar boolean attributes from the MachineRegisterInfo class: IsSSA, TracksRegLiveness, and TracksSubRegLiveness. These attributes are serialized as part of the machine function YAML mapping. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10618 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240579 91177308-0d34-0410-b5e6-96231b3b80d8 Alex Lorenz 5 years ago
5 changed file(s) with 79 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
9696 unsigned Alignment = 0;
9797 bool ExposesReturnsTwice = false;
9898 bool HasInlineAsm = false;
99 // Register information
100 bool IsSSA = false;
101 bool TracksRegLiveness = false;
102 bool TracksSubRegLiveness = false;
103 // TODO: Serialize virtual register definitions.
104 // TODO: Serialize the various register masks.
105 // TODO: Serialize live in registers.
99106
100107 std::vector BasicBlocks;
101108 };
106113 YamlIO.mapOptional("alignment", MF.Alignment);
107114 YamlIO.mapOptional("exposesReturnsTwice", MF.ExposesReturnsTwice);
108115 YamlIO.mapOptional("hasInlineAsm", MF.HasInlineAsm);
116 YamlIO.mapOptional("isSSA", MF.IsSSA);
117 YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness);
118 YamlIO.mapOptional("tracksSubRegLiveness", MF.TracksSubRegLiveness);
109119 YamlIO.mapOptional("body", MF.BasicBlocks);
110120 }
111121 };
1818 #include "llvm/ADT/STLExtras.h"
1919 #include "llvm/AsmParser/Parser.h"
2020 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
2122 #include "llvm/CodeGen/MIRYamlMapping.h"
2223 #include "llvm/IR/BasicBlock.h"
2324 #include "llvm/IR/DiagnosticInfo.h"
8182 /// Return true if an error occurred.
8283 bool initializeMachineBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB,
8384 const yaml::MachineBasicBlock &YamlMBB);
85
86 bool initializeRegisterInfo(MachineRegisterInfo &RegInfo,
87 const yaml::MachineFunction &YamlMF);
8488
8589 private:
8690 /// Return a MIR diagnostic converted from an MI string diagnostic.
211215 MF.setAlignment(YamlMF.Alignment);
212216 MF.setExposesReturnsTwice(YamlMF.ExposesReturnsTwice);
213217 MF.setHasInlineAsm(YamlMF.HasInlineAsm);
218 if (initializeRegisterInfo(MF.getRegInfo(), YamlMF))
219 return true;
220
214221 const auto &F = *MF.getFunction();
215222 for (const auto &YamlMBB : YamlMF.BasicBlocks) {
216223 const BasicBlock *BB = nullptr;
249256 return false;
250257 }
251258
259 bool MIRParserImpl::initializeRegisterInfo(
260 MachineRegisterInfo &RegInfo, const yaml::MachineFunction &YamlMF) {
261 assert(RegInfo.isSSA());
262 if (!YamlMF.IsSSA)
263 RegInfo.leaveSSA();
264 assert(RegInfo.tracksLiveness());
265 if (!YamlMF.TracksRegLiveness)
266 RegInfo.invalidateLiveness();
267 RegInfo.enableSubRegLiveness(YamlMF.TracksSubRegLiveness);
268 return false;
269 }
270
252271 SMDiagnostic MIRParserImpl::diagFromMIStringDiag(const SMDiagnostic &Error,
253272 SMRange SourceRange) {
254273 assert(SourceRange.isValid() && "Invalid source range");
1414 #include "MIRPrinter.h"
1515 #include "llvm/ADT/STLExtras.h"
1616 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
1718 #include "llvm/CodeGen/MIRYamlMapping.h"
1819 #include "llvm/IR/BasicBlock.h"
1920 #include "llvm/IR/Module.h"
3738
3839 void print(const MachineFunction &MF);
3940
41 void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo);
4042 void convert(yaml::MachineBasicBlock &YamlMBB, const MachineBasicBlock &MBB);
4143 };
4244
7779 YamlMF.Alignment = MF.getAlignment();
7880 YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
7981 YamlMF.HasInlineAsm = MF.hasInlineAsm();
82 convert(YamlMF, MF.getRegInfo());
8083 for (const auto &MBB : MF) {
8184 yaml::MachineBasicBlock YamlMBB;
8285 convert(YamlMBB, MBB);
8487 }
8588 yaml::Output Out(OS);
8689 Out << YamlMF;
90 }
91
92 void MIRPrinter::convert(yaml::MachineFunction &MF,
93 const MachineRegisterInfo &RegInfo) {
94 MF.IsSSA = RegInfo.isSSA();
95 MF.TracksRegLiveness = RegInfo.tracksLiveness();
96 MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
8797 }
8898
8999 void MIRPrinter::convert(yaml::MachineBasicBlock &YamlMBB,
2424 # CHECK-NEXT: alignment:
2525 # CHECK-NEXT: exposesReturnsTwice: false
2626 # CHECK-NEXT: hasInlineAsm: false
27 # CHECK-NEXT: ...
27 # CHECK: ...
2828 name: foo
2929 ...
3030 ---
3232 # CHECK-NEXT: alignment:
3333 # CHECK-NEXT: exposesReturnsTwice: false
3434 # CHECK-NEXT: hasInlineAsm: false
35 # CHECK-NEXT: ...
35 # CHECK: ...
3636 name: bar
3737 ...
3838 ---
4040 # CHECK-NEXT: alignment: 8
4141 # CHECK-NEXT: exposesReturnsTwice: false
4242 # CHECK-NEXT: hasInlineAsm: false
43 # CHECK-NEXT: ...
43 # CHECK: ...
4444 name: func
4545 alignment: 8
4646 ...
4949 # CHECK-NEXT: alignment: 16
5050 # CHECK-NEXT: exposesReturnsTwice: true
5151 # CHECK-NEXT: hasInlineAsm: true
52 # CHECK-NEXT: ...
52 # CHECK: ...
5353 name: func2
5454 alignment: 16
5555 exposesReturnsTwice: true
0 # RUN: llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s
1 # This test ensures that the MIR parser parses machine register info properties
2 # correctly.
3
4 --- |
5
6 define i32 @foo() {
7 entry:
8 ret i32 0
9 }
10
11 define i32 @bar() {
12 start:
13 ret i32 0
14 }
15
16 ...
17 ---
18 # CHECK: name: foo
19 # CHECK: isSSA: false
20 # CHECK-NEXT: tracksRegLiveness: false
21 # CHECK-NEXT: tracksSubRegLiveness: false
22 # CHECK: ...
23 name: foo
24 ...
25 ---
26 # CHECK: name: bar
27 # CHECK: isSSA: false
28 # CHECK-NEXT: tracksRegLiveness: true
29 # CHECK-NEXT: tracksSubRegLiveness: true
30 # CHECK: ...
31 name: bar
32 isSSA: false
33 tracksRegLiveness: true
34 tracksSubRegLiveness: true
35 ...