llvm.org GIT mirror llvm / c97ef61
Move getOpcodeName from the various target InstPrinters into the superclass MCInstPrinter. All implementations used the same code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153866 91177308-0d34-0410-b5e6-96231b3b80d8 Benjamin Kramer 8 years ago
14 changed file(s) with 3 addition(s) and 31 deletion(s). Raw diff Collapse all Expand all
5151
5252 /// getOpcodeName - Return the name of the specified opcode enum (e.g.
5353 /// "MOV32ri") or empty if we can't resolve it.
54 virtual StringRef getOpcodeName(unsigned Opcode) const;
54 StringRef getOpcodeName(unsigned Opcode) const;
5555
5656 /// printRegName - Print the assembler register name.
5757 virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
77 //===----------------------------------------------------------------------===//
88
99 #include "llvm/MC/MCInstPrinter.h"
10 #include "llvm/MC/MCInstrInfo.h"
1011 #include "llvm/MC/MCAsmInfo.h"
1112 #include "llvm/ADT/StringRef.h"
1213 #include "llvm/Support/ErrorHandling.h"
1920 /// getOpcodeName - Return the name of the specified opcode enum (e.g.
2021 /// "MOV32ri") or empty if we can't resolve it.
2122 StringRef MCInstPrinter::getOpcodeName(unsigned Opcode) const {
22 return "";
23 return MII.getName(Opcode);
2324 }
2425
2526 void MCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
4141 MCInstPrinter(MAI, MII, MRI) {
4242 // Initialize the set of available features.
4343 setAvailableFeatures(STI.getFeatureBits());
44 }
45
46 StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
47 return MII.getName(Opcode);
4844 }
4945
5046 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
2626 const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
2727
2828 virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
29 virtual StringRef getOpcodeName(unsigned Opcode) const;
3029 virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
3130
3231 // Autogenerated by tblgen.
5959 case FCOND_GT: return "ngt";
6060 }
6161 llvm_unreachable("Impossible condition code!");
62 }
63
64 StringRef MipsInstPrinter::getOpcodeName(unsigned Opcode) const {
65 return MII.getName(Opcode);
6662 }
6763
6864 void MipsInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
8484 void printInstruction(const MCInst *MI, raw_ostream &O);
8585 static const char *getRegisterName(unsigned RegNo);
8686
87 virtual StringRef getOpcodeName(unsigned Opcode) const;
8887 virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
8988 virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
9089
3333 MCInstPrinter(MAI, MII, MRI) {
3434 // Initialize the set of available features.
3535 setAvailableFeatures(STI.getFeatureBits());
36 }
37
38 StringRef PTXInstPrinter::getOpcodeName(unsigned Opcode) const {
39 return MII.getName(Opcode);
4036 }
4137
4238 void PTXInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
2626 const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
2727
2828 virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
29 virtual StringRef getOpcodeName(unsigned Opcode) const;
3029 virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
3130
3231 // Autogenerated by tblgen.
2121 using namespace llvm;
2222
2323 #include "PPCGenAsmWriter.inc"
24
25 StringRef PPCInstPrinter::getOpcodeName(unsigned Opcode) const {
26 return MII.getName(Opcode);
27 }
2824
2925 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
3026 OS << getRegisterName(RegNo);
3333
3434 virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
3535 virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
36 virtual StringRef getOpcodeName(unsigned Opcode) const;
3736
3837 // Autogenerated by tblgen.
3938 void printInstruction(const MCInst *MI, raw_ostream &O);
4747 // If verbose assembly is enabled, we can print some informative comments.
4848 if (CommentStream)
4949 EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
50 }
51
52 StringRef X86ATTInstPrinter::getOpcodeName(unsigned Opcode) const {
53 return MII.getName(Opcode);
5450 }
5551
5652 void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
2727
2828 virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
2929 virtual void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot);
30 virtual StringRef getOpcodeName(unsigned Opcode) const;
3130
3231 // Autogenerated by tblgen, returns true if we successfully printed an
3332 // alias.
3939 // If verbose assembly is enabled, we can print some informative comments.
4040 if (CommentStream)
4141 EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
42 }
43 StringRef X86IntelInstPrinter::getOpcodeName(unsigned Opcode) const {
44 return MII.getName(Opcode);
4542 }
4643
4744 void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
2828
2929 virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
3030 virtual void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot);
31 virtual StringRef getOpcodeName(unsigned Opcode) const;
3231
3332 // Autogenerated by tblgen.
3433 void printInstruction(const MCInst *MI, raw_ostream &O);