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[llvm-exegesis] ExegisX86Target::setRegToConstant() should depend on the subtarget features. Summary: This fixes PR38008. Reviewers: gchatelet, RKSimon Subscribers: tschuett, craig.topper, llvm-commits Differential Revision: https://reviews.llvm.org/D48820 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336171 91177308-0d34-0410-b5e6-96231b3b80d8 Clement Courbet 1 year, 4 months ago
4 changed file(s) with 161 addition(s) and 19 deletion(s). Raw diff Collapse all Expand all
2929
3030 static std::vector
3131 generateSnippetSetupCode(const llvm::ArrayRef RegsToDef,
32 const ExegesisTarget &ET, bool &IsComplete) {
32 const ExegesisTarget &ET,
33 const llvm::LLVMTargetMachine &TM, bool &IsComplete) {
3334 IsComplete = true;
3435 std::vector Result;
3536 for (const unsigned Reg : RegsToDef) {
3637 // Load a constant in the register.
37 const auto Code = ET.setRegToConstant(Reg);
38 const auto Code = ET.setRegToConstant(*TM.getMCSubtargetInfo(), Reg);
3839 if (Code.empty())
3940 IsComplete = false;
4041 Result.insert(Result.end(), Code.begin(), Code.end());
158159 Properties.reset(llvm::MachineFunctionProperties::Property::IsSSA);
159160 bool IsSnippetSetupComplete = false;
160161 std::vector SnippetWithSetup =
161 generateSnippetSetupCode(RegsToDef, ET, IsSnippetSetupComplete);
162 generateSnippetSetupCode(RegsToDef, ET, *TM, IsSnippetSetupComplete);
162163 if (!SnippetWithSetup.empty()) {
163164 SnippetWithSetup.insert(SnippetWithSetup.end(), Instructions.begin(),
164165 Instructions.end());
3333 virtual void addTargetSpecificPasses(llvm::PassManagerBase &PM) const {}
3434
3535 // Generates code to move a constant into a the given register.
36 virtual std::vector setRegToConstant(unsigned Reg) const {
36 virtual std::vector
37 setRegToConstant(const llvm::MCSubtargetInfo &STI, unsigned Reg) const {
3738 return {};
3839 }
3940
1313 #include "MCTargetDesc/X86MCTargetDesc.h"
1414 #include "X86.h"
1515 #include "X86RegisterInfo.h"
16 #include "X86Subtarget.h"
1617 #include "llvm/MC/MCInstBuilder.h"
1718
1819 namespace exegesis {
129130 PM.add(llvm::createX86FloatingPointStackifierPass());
130131 }
131132
132 std::vector
133 setRegToConstant(unsigned Reg) const override {
133 std::vector setRegToConstant(const llvm::MCSubtargetInfo &STI,
134 unsigned Reg) const override {
135 // GPR.
134136 if (llvm::X86::GR8RegClass.contains(Reg))
135137 return {llvm::MCInstBuilder(llvm::X86::MOV8ri).addReg(Reg).addImm(1)};
136138 if (llvm::X86::GR16RegClass.contains(Reg))
139141 return {llvm::MCInstBuilder(llvm::X86::MOV32ri).addReg(Reg).addImm(1)};
140142 if (llvm::X86::GR64RegClass.contains(Reg))
141143 return {llvm::MCInstBuilder(llvm::X86::MOV64ri32).addReg(Reg).addImm(1)};
142 if (llvm::X86::VR128XRegClass.contains(Reg))
143 return setVectorRegToConstant(Reg, 16, llvm::X86::VMOVDQUrm);
144 if (llvm::X86::VR256XRegClass.contains(Reg))
144 // MMX.
145 if (llvm::X86::VR64RegClass.contains(Reg))
146 return setVectorRegToConstant(Reg, 8, llvm::X86::MMX_MOVQ64rm);
147 // {X,Y,Z}MM.
148 if (llvm::X86::VR128XRegClass.contains(Reg)) {
149 if (STI.getFeatureBits()[llvm::X86::FeatureAVX512])
150 return setVectorRegToConstant(Reg, 16, llvm::X86::VMOVDQU32Z128rm);
151 if (STI.getFeatureBits()[llvm::X86::FeatureAVX])
152 return setVectorRegToConstant(Reg, 16, llvm::X86::VMOVDQUrm);
153 return setVectorRegToConstant(Reg, 16, llvm::X86::MOVDQUrm);
154 }
155 if (llvm::X86::VR256XRegClass.contains(Reg)) {
156 if (STI.getFeatureBits()[llvm::X86::FeatureAVX512])
157 return setVectorRegToConstant(Reg, 32, llvm::X86::VMOVDQU32Z256rm);
145158 return setVectorRegToConstant(Reg, 32, llvm::X86::VMOVDQUYrm);
159 }
146160 if (llvm::X86::VR512RegClass.contains(Reg))
147 return setVectorRegToConstant(Reg, 64, llvm::X86::VMOVDQU64Zrm);
161 return setVectorRegToConstant(Reg, 64, llvm::X86::VMOVDQU32Zrm);
162 // X87.
148163 if (llvm::X86::RFP32RegClass.contains(Reg) ||
149164 llvm::X86::RFP64RegClass.contains(Reg) ||
150165 llvm::X86::RFP80RegClass.contains(Reg))
154169
155170 std::unique_ptr
156171 createLatencyBenchmarkRunner(const LLVMState &State) const override {
157 return llvm::make_unique>(
158 State);
172 return llvm::make_unique>(State);
159173 }
160174
161175 std::unique_ptr
33 #include
44
55 #include "MCTargetDesc/X86MCTargetDesc.h"
6 #include "llvm/Support/TargetRegistry.h"
7 #include "llvm/Support/TargetSelect.h"
68 #include "gmock/gmock.h"
79 #include "gtest/gtest.h"
810
1618 using testing::NotNull;
1719 using testing::SizeIs;
1820
21 constexpr const char kTriple[] = "x86_64-unknown-linux";
22
1923 class X86TargetTest : public ::testing::Test {
2024 protected:
2125 X86TargetTest()
22 : Target_(ExegesisTarget::lookup(llvm::Triple("x86_64-unknown-linux"))) {
26 : ExegesisTarget_(ExegesisTarget::lookup(llvm::Triple(kTriple))) {
27 EXPECT_THAT(ExegesisTarget_, NotNull());
28 std::string error;
29 Target_ = llvm::TargetRegistry::lookupTarget(kTriple, error);
2330 EXPECT_THAT(Target_, NotNull());
2431 }
25 static void SetUpTestCase() { InitializeX86ExegesisTarget(); }
32 static void SetUpTestCase() {
33 LLVMInitializeX86TargetInfo();
34 LLVMInitializeX86Target();
35 LLVMInitializeX86TargetMC();
36 InitializeX86ExegesisTarget();
37 }
2638
27 const ExegesisTarget *const Target_;
39 const llvm::Target *Target_;
40 const ExegesisTarget *const ExegesisTarget_;
2841 };
2942
3043 TEST_F(X86TargetTest, SetRegToConstantGPR) {
31 const auto Insts = Target_->setRegToConstant(llvm::X86::EAX);
44 const std::unique_ptr STI(
45 Target_->createMCSubtargetInfo(kTriple, "core2", ""));
46 const auto Insts = ExegesisTarget_->setRegToConstant(*STI, llvm::X86::EAX);
3247 EXPECT_THAT(Insts, SizeIs(1));
3348 EXPECT_EQ(Insts[0].getOpcode(), llvm::X86::MOV32ri);
3449 EXPECT_EQ(Insts[0].getOperand(0).getReg(), llvm::X86::EAX);
3550 }
3651
37 TEST_F(X86TargetTest, SetRegToConstantXMM) {
38 const auto Insts = Target_->setRegToConstant(llvm::X86::XMM1);
39 EXPECT_THAT(Insts, SizeIs(Gt(0U)));
52 TEST_F(X86TargetTest, SetRegToConstantXMM_SSE2) {
53 const std::unique_ptr STI(
54 Target_->createMCSubtargetInfo(kTriple, "core2", ""));
55 const auto Insts = ExegesisTarget_->setRegToConstant(*STI, llvm::X86::XMM1);
56 EXPECT_THAT(Insts, SizeIs(7U));
57 EXPECT_EQ(Insts[0].getOpcode(), llvm::X86::SUB64ri8);
58 EXPECT_EQ(Insts[1].getOpcode(), llvm::X86::MOV32mi);
59 EXPECT_EQ(Insts[2].getOpcode(), llvm::X86::MOV32mi);
60 EXPECT_EQ(Insts[3].getOpcode(), llvm::X86::MOV32mi);
61 EXPECT_EQ(Insts[4].getOpcode(), llvm::X86::MOV32mi);
62 EXPECT_EQ(Insts[5].getOpcode(), llvm::X86::MOVDQUrm);
63 EXPECT_EQ(Insts[6].getOpcode(), llvm::X86::ADD64ri8);
64 }
65
66 TEST_F(X86TargetTest, SetRegToConstantXMM_AVX) {
67 const std::unique_ptr STI(
68 Target_->createMCSubtargetInfo(kTriple, "core2", "+avx"));
69 const auto Insts = ExegesisTarget_->setRegToConstant(*STI, llvm::X86::XMM1);
70 EXPECT_THAT(Insts, SizeIs(7U));
71 EXPECT_EQ(Insts[0].getOpcode(), llvm::X86::SUB64ri8);
72 EXPECT_EQ(Insts[1].getOpcode(), llvm::X86::MOV32mi);
73 EXPECT_EQ(Insts[2].getOpcode(), llvm::X86::MOV32mi);
74 EXPECT_EQ(Insts[3].getOpcode(), llvm::X86::MOV32mi);
75 EXPECT_EQ(Insts[4].getOpcode(), llvm::X86::MOV32mi);
76 EXPECT_EQ(Insts[5].getOpcode(), llvm::X86::VMOVDQUrm);
77 EXPECT_EQ(Insts[6].getOpcode(), llvm::X86::ADD64ri8);
78 }
79
80 TEST_F(X86TargetTest, SetRegToConstantXMM_AVX512) {
81 const std::unique_ptr STI(
82 Target_->createMCSubtargetInfo(kTriple, "core2", "+avx512vl"));
83 const auto Insts = ExegesisTarget_->setRegToConstant(*STI, llvm::X86::XMM1);
84 EXPECT_THAT(Insts, SizeIs(7U));
85 EXPECT_EQ(Insts[0].getOpcode(), llvm::X86::SUB64ri8);
86 EXPECT_EQ(Insts[1].getOpcode(), llvm::X86::MOV32mi);
87 EXPECT_EQ(Insts[2].getOpcode(), llvm::X86::MOV32mi);
88 EXPECT_EQ(Insts[3].getOpcode(), llvm::X86::MOV32mi);
89 EXPECT_EQ(Insts[4].getOpcode(), llvm::X86::MOV32mi);
90 EXPECT_EQ(Insts[5].getOpcode(), llvm::X86::VMOVDQU32Z128rm);
91 EXPECT_EQ(Insts[6].getOpcode(), llvm::X86::ADD64ri8);
92 }
93
94 TEST_F(X86TargetTest, SetRegToConstantMMX) {
95 const std::unique_ptr STI(
96 Target_->createMCSubtargetInfo(kTriple, "core2", ""));
97 const auto Insts = ExegesisTarget_->setRegToConstant(*STI, llvm::X86::MM1);
98 EXPECT_THAT(Insts, SizeIs(5U));
99 EXPECT_EQ(Insts[0].getOpcode(), llvm::X86::SUB64ri8);
100 EXPECT_EQ(Insts[1].getOpcode(), llvm::X86::MOV32mi);
101 EXPECT_EQ(Insts[2].getOpcode(), llvm::X86::MOV32mi);
102 EXPECT_EQ(Insts[3].getOpcode(), llvm::X86::MMX_MOVQ64rm);
103 EXPECT_EQ(Insts[4].getOpcode(), llvm::X86::ADD64ri8);
104 }
105
106 TEST_F(X86TargetTest, SetRegToConstantYMM_AVX) {
107 const std::unique_ptr STI(
108 Target_->createMCSubtargetInfo(kTriple, "core2", "+avx"));
109 const auto Insts = ExegesisTarget_->setRegToConstant(*STI, llvm::X86::YMM1);
110 EXPECT_THAT(Insts, SizeIs(11U));
111 EXPECT_EQ(Insts[0].getOpcode(), llvm::X86::SUB64ri8);
112 EXPECT_EQ(Insts[1].getOpcode(), llvm::X86::MOV32mi);
113 EXPECT_EQ(Insts[2].getOpcode(), llvm::X86::MOV32mi);
114 EXPECT_EQ(Insts[3].getOpcode(), llvm::X86::MOV32mi);
115 EXPECT_EQ(Insts[4].getOpcode(), llvm::X86::MOV32mi);
116 EXPECT_EQ(Insts[5].getOpcode(), llvm::X86::MOV32mi);
117 EXPECT_EQ(Insts[6].getOpcode(), llvm::X86::MOV32mi);
118 EXPECT_EQ(Insts[7].getOpcode(), llvm::X86::MOV32mi);
119 EXPECT_EQ(Insts[8].getOpcode(), llvm::X86::MOV32mi);
120 EXPECT_EQ(Insts[9].getOpcode(), llvm::X86::VMOVDQUYrm);
121 EXPECT_EQ(Insts[10].getOpcode(), llvm::X86::ADD64ri8);
122 }
123
124 TEST_F(X86TargetTest, SetRegToConstantYMM_AVX512) {
125 const std::unique_ptr STI(
126 Target_->createMCSubtargetInfo(kTriple, "core2", "+avx512vl"));
127 const auto Insts = ExegesisTarget_->setRegToConstant(*STI, llvm::X86::YMM1);
128 EXPECT_THAT(Insts, SizeIs(11U));
129 EXPECT_EQ(Insts[0].getOpcode(), llvm::X86::SUB64ri8);
130 EXPECT_EQ(Insts[1].getOpcode(), llvm::X86::MOV32mi);
131 EXPECT_EQ(Insts[2].getOpcode(), llvm::X86::MOV32mi);
132 EXPECT_EQ(Insts[3].getOpcode(), llvm::X86::MOV32mi);
133 EXPECT_EQ(Insts[4].getOpcode(), llvm::X86::MOV32mi);
134 EXPECT_EQ(Insts[5].getOpcode(), llvm::X86::MOV32mi);
135 EXPECT_EQ(Insts[6].getOpcode(), llvm::X86::MOV32mi);
136 EXPECT_EQ(Insts[7].getOpcode(), llvm::X86::MOV32mi);
137 EXPECT_EQ(Insts[8].getOpcode(), llvm::X86::MOV32mi);
138 EXPECT_EQ(Insts[9].getOpcode(), llvm::X86::VMOVDQU32Z256rm);
139 EXPECT_EQ(Insts[10].getOpcode(), llvm::X86::ADD64ri8);
140 }
141
142 TEST_F(X86TargetTest, SetRegToConstantZMM_AVX512) {
143 const std::unique_ptr STI(
144 Target_->createMCSubtargetInfo(kTriple, "core2", "+avx512vl"));
145 const auto Insts = ExegesisTarget_->setRegToConstant(*STI, llvm::X86::ZMM1);
146 EXPECT_THAT(Insts, SizeIs(19U));
147 EXPECT_EQ(Insts[0].getOpcode(), llvm::X86::SUB64ri8);
148 EXPECT_EQ(Insts[1].getOpcode(), llvm::X86::MOV32mi);
149 EXPECT_EQ(Insts[2].getOpcode(), llvm::X86::MOV32mi);
150 EXPECT_EQ(Insts[3].getOpcode(), llvm::X86::MOV32mi);
151 EXPECT_EQ(Insts[4].getOpcode(), llvm::X86::MOV32mi);
152 EXPECT_EQ(Insts[5].getOpcode(), llvm::X86::MOV32mi);
153 EXPECT_EQ(Insts[6].getOpcode(), llvm::X86::MOV32mi);
154 EXPECT_EQ(Insts[7].getOpcode(), llvm::X86::MOV32mi);
155 EXPECT_EQ(Insts[8].getOpcode(), llvm::X86::MOV32mi);
156 EXPECT_EQ(Insts[9].getOpcode(), llvm::X86::MOV32mi);
157 EXPECT_EQ(Insts[10].getOpcode(), llvm::X86::MOV32mi);
158 EXPECT_EQ(Insts[11].getOpcode(), llvm::X86::MOV32mi);
159 EXPECT_EQ(Insts[12].getOpcode(), llvm::X86::MOV32mi);
160 EXPECT_EQ(Insts[13].getOpcode(), llvm::X86::MOV32mi);
161 EXPECT_EQ(Insts[14].getOpcode(), llvm::X86::MOV32mi);
162 EXPECT_EQ(Insts[15].getOpcode(), llvm::X86::MOV32mi);
163 EXPECT_EQ(Insts[16].getOpcode(), llvm::X86::MOV32mi);
164 EXPECT_EQ(Insts[17].getOpcode(), llvm::X86::VMOVDQU32Zrm);
165 EXPECT_EQ(Insts[18].getOpcode(), llvm::X86::ADD64ri8);
40166 }
41167
42168 } // namespace