llvm.org GIT mirror llvm / c940365
Split the SDValue out of OutputArg so that SelectionDAG-independent code can do calling-convention queries. This obviates OutputArgReg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107786 91177308-0d34-0410-b5e6-96231b3b80d8 Dan Gohman 10 years ago
31 changed file(s) with 144 addition(s) and 122 deletion(s). Raw diff Collapse all Expand all
183183 /// incorporating info about the result values into this state.
184184 void AnalyzeReturn(const SmallVectorImpl &Outs,
185185 CCAssignFn Fn);
186 void AnalyzeReturn(const SmallVectorImpl &Outs,
187 CCAssignFn Fn);
188186
189187 /// CheckReturn - Analyze the return values of a function, returning
190188 /// true if the return can be performed without sret-demotion, and
196194 /// AnalyzeCallOperands - Analyze the outgoing arguments to a call,
197195 /// incorporating info about the passed values into this state.
198196 void AnalyzeCallOperands(const SmallVectorImpl &Outs,
199 CCAssignFn Fn);
200 void AnalyzeCallOperands(const SmallVectorImpl &Outs,
201197 CCAssignFn Fn);
202198
203199 /// AnalyzeCallOperands - Same as above except it takes vectors of types
1212
1313 #ifndef LLVM_TARGET_TARGETCALLINGCONV_H
1414 #define LLVM_TARGET_TARGETCALLINGCONV_H
15
16 #include "llvm/CodeGen/SelectionDAGNodes.h"
1715
1816 namespace llvm {
1917
111109 bool Used;
112110
113111 InputArg() : VT(MVT::Other), Used(false) {}
114 InputArg(ISD::ArgFlagsTy flags, EVT vt, bool used)
112 InputArg(ArgFlagsTy flags, EVT vt, bool used)
115113 : Flags(flags), VT(vt), Used(used) {
116114 assert(VT.isSimple() &&
117115 "InputArg value type must be Simple!");
124122 ///
125123 struct OutputArg {
126124 ArgFlagsTy Flags;
127 SDValue Val;
125 EVT VT;
128126
129127 /// IsFixed - Is this a "fixed" value, ie not passed through a vararg "...".
130128 bool IsFixed;
131129
132130 OutputArg() : IsFixed(false) {}
133 OutputArg(ISD::ArgFlagsTy flags, SDValue val, bool isfixed)
134 : Flags(flags), Val(val), IsFixed(isfixed) {
135 assert(Val.getValueType().isSimple() &&
131 OutputArg(ArgFlagsTy flags, EVT vt, bool isfixed)
132 : Flags(flags), VT(vt), IsFixed(isfixed) {
133 assert(VT.isSimple() &&
136134 "OutputArg value type must be Simple!");
137135 }
138 };
139
140 /// OutputArgReg - This struct carries flags and a register value for a
141 /// single outgoing (actual) argument or outgoing (from the perspective
142 /// of the caller) return value virtual register.
143 ///
144 struct OutputArgReg {
145 ArgFlagsTy Flags;
146 EVT VT;
147 unsigned Reg;
148
149 /// IsFixed - Is this a "fixed" value, ie not passed through a vararg "...".
150 bool IsFixed;
151
152 OutputArgReg() : IsFixed(false) {}
153 OutputArgReg(ISD::ArgFlagsTy flags, EVT vt, unsigned reg, bool isfixed)
154 : Flags(flags), VT(vt), Reg(reg), IsFixed(isfixed) {}
155136 };
156137 }
157138
11441144 LowerCall(SDValue Chain, SDValue Callee,
11451145 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
11461146 const SmallVectorImpl &Outs,
1147 const SmallVectorImpl &OutVals,
11471148 const SmallVectorImpl &Ins,
11481149 DebugLoc dl, SelectionDAG &DAG,
11491150 SmallVectorImpl &InVals) const {
11721173 virtual SDValue
11731174 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
11741175 const SmallVectorImpl &Outs,
1176 const SmallVectorImpl &OutVals,
11751177 DebugLoc dl, SelectionDAG &DAG) const {
11761178 assert(0 && "Not Implemented");
11771179 return SDValue(); // this is here to silence compiler errors
9898 CCAssignFn Fn) {
9999 // Determine which register each value should be copied into.
100100 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
101 EVT VT = Outs[i].Val.getValueType();
102 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
103 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) {
104 #ifndef NDEBUG
105 dbgs() << "Return operand #" << i << " has unhandled type "
106 << VT.getEVTString();
107 #endif
108 llvm_unreachable(0);
109 }
110 }
111 }
112
113 void CCState::AnalyzeReturn(const SmallVectorImpl &Outs,
114 CCAssignFn Fn) {
115 // Determine which register each value should be copied into.
116 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
117101 EVT VT = Outs[i].VT;
118102 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
119103 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) {
126110 }
127111 }
128112
129
130113 /// AnalyzeCallOperands - Analyze the outgoing arguments to a call,
131114 /// incorporating info about the passed values into this state.
132115 void CCState::AnalyzeCallOperands(const SmallVectorImpl &Outs,
133116 CCAssignFn Fn) {
134 unsigned NumOps = Outs.size();
135 for (unsigned i = 0; i != NumOps; ++i) {
136 EVT ArgVT = Outs[i].Val.getValueType();
137 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
138 if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
139 #ifndef NDEBUG
140 dbgs() << "Call operand #" << i << " has unhandled type "
141 << ArgVT.getEVTString();
142 #endif
143 llvm_unreachable(0);
144 }
145 }
146 }
147
148 /// AnalyzeCallOperands - Analyze the outgoing arguments to a call,
149 /// incorporating info about the passed values into this state.
150 void
151 CCState::AnalyzeCallOperands(const SmallVectorImpl &Outs,
152 CCAssignFn Fn) {
153117 unsigned NumOps = Outs.size();
154118 for (unsigned i = 0; i != NumOps; ++i) {
155119 EVT ArgVT = Outs[i].VT;
10261026 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
10271027 SDValue Chain = getControlRoot();
10281028 SmallVector Outs;
1029 SmallVector OutVals;
10291030
10301031 if (!FuncInfo.CanLowerReturn) {
10311032 unsigned DemoteReg = FuncInfo.DemoteRegister;
11041105 else if (F->paramHasAttr(0, Attribute::ZExt))
11051106 Flags.setZExt();
11061107
1107 for (unsigned i = 0; i < NumParts; ++i)
1108 Outs.push_back(ISD::OutputArg(Flags, Parts[i], /*isfixed=*/true));
1108 for (unsigned i = 0; i < NumParts; ++i) {
1109 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1110 /*isfixed=*/true));
1111 OutVals.push_back(Parts[i]);
1112 }
11091113 }
11101114 }
11111115 }
11141118 CallingConv::ID CallConv =
11151119 DAG.getMachineFunction().getFunction()->getCallingConv();
11161120 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
1117 Outs, getCurDebugLoc(), DAG);
1121 Outs, OutVals, getCurDebugLoc(), DAG);
11181122
11191123 // Verify that the target's LowerReturn behaved as expected.
11201124 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
57675771 DebugLoc dl) const {
57685772 // Handle all of the outgoing arguments.
57695773 SmallVector Outs;
5774 SmallVector OutVals;
57705775 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
57715776 SmallVector ValueVTs;
57725777 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
58205825
58215826 for (unsigned j = 0; j != NumParts; ++j) {
58225827 // if it isn't first piece, alignment must be 1
5823 ISD::OutputArg MyFlags(Flags, Parts[j], i < NumFixedArgs);
5828 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
5829 i < NumFixedArgs);
58245830 if (NumParts > 1 && j == 0)
58255831 MyFlags.Flags.setSplit();
58265832 else if (j != 0)
58275833 MyFlags.Flags.setOrigAlign(1);
58285834
58295835 Outs.push_back(MyFlags);
5836 OutVals.push_back(Parts[j]);
58305837 }
58315838 }
58325839 }
58555862
58565863 SmallVector InVals;
58575864 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
5858 Outs, Ins, dl, DAG, InVals);
5865 Outs, OutVals, Ins, dl, DAG, InVals);
58595866
58605867 // Verify that the target's LowerCall behaved as expected.
58615868 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
10291029 CallingConv::ID CallConv, bool isVarArg,
10301030 bool &isTailCall,
10311031 const SmallVectorImpl &Outs,
1032 const SmallVectorImpl &OutVals,
10321033 const SmallVectorImpl &Ins,
10331034 DebugLoc dl, SelectionDAG &DAG,
10341035 SmallVectorImpl &InVals) const {
10421043 // Check if it's really possible to do a tail call.
10431044 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
10441045 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1045 Outs, Ins, DAG);
1046 Outs, OutVals, Ins, DAG);
10461047 // We don't support GuaranteedTailCallOpt for ARM, only automatically
10471048 // detected sibcalls.
10481049 if (isTailCall) {
10821083 i != e;
10831084 ++i, ++realArgIdx) {
10841085 CCValAssign &VA = ArgLocs[i];
1085 SDValue Arg = Outs[realArgIdx].Val;
1086 SDValue Arg = OutVals[realArgIdx];
10861087 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
10871088
10881089 // Promote the value if needed.
13761377 bool isCalleeStructRet,
13771378 bool isCallerStructRet,
13781379 const SmallVectorImpl &Outs,
1380 const SmallVectorImpl &OutVals,
13791381 const SmallVectorImpl &Ins,
13801382 SelectionDAG& DAG) const {
13811383 const Function *CallerF = DAG.getMachineFunction().getFunction();
14691471 ++i, ++realArgIdx) {
14701472 CCValAssign &VA = ArgLocs[i];
14711473 EVT RegVT = VA.getLocVT();
1472 SDValue Arg = Outs[realArgIdx].Val;
1474 SDValue Arg = OutVals[realArgIdx];
14731475 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
14741476 if (VA.getLocInfo() == CCValAssign::Indirect)
14751477 return false;
15041506 ARMTargetLowering::LowerReturn(SDValue Chain,
15051507 CallingConv::ID CallConv, bool isVarArg,
15061508 const SmallVectorImpl &Outs,
1509 const SmallVectorImpl &OutVals,
15071510 DebugLoc dl, SelectionDAG &DAG) const {
15081511
15091512 // CCValAssign - represent the assignment of the return value to a location.
15341537 CCValAssign &VA = RVLocs[i];
15351538 assert(VA.isRegLoc() && "Can only return in registers!");
15361539
1537 SDValue Arg = Outs[realRVLocIdx].Val;
1540 SDValue Arg = OutVals[realRVLocIdx];
15381541
15391542 switch (VA.getLocInfo()) {
15401543 default: llvm_unreachable("Unknown loc info!");
336336 CallingConv::ID CallConv, bool isVarArg,
337337 bool &isTailCall,
338338 const SmallVectorImpl &Outs,
339 const SmallVectorImpl &OutVals,
339340 const SmallVectorImpl &Ins,
340341 DebugLoc dl, SelectionDAG &DAG,
341342 SmallVectorImpl &InVals) const;
349350 bool isCalleeStructRet,
350351 bool isCallerStructRet,
351352 const SmallVectorImpl &Outs,
353 const SmallVectorImpl &OutVals,
352354 const SmallVectorImpl &Ins,
353355 SelectionDAG& DAG) const;
354356 virtual SDValue
355357 LowerReturn(SDValue Chain,
356358 CallingConv::ID CallConv, bool isVarArg,
357359 const SmallVectorImpl &Outs,
360 const SmallVectorImpl &OutVals,
358361 DebugLoc dl, SelectionDAG &DAG) const;
359362
360363 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
223223 CallingConv::ID CallConv, bool isVarArg,
224224 bool &isTailCall,
225225 const SmallVectorImpl &Outs,
226 const SmallVectorImpl &OutVals,
226227 const SmallVectorImpl &Ins,
227228 DebugLoc dl, SelectionDAG &DAG,
228229 SmallVectorImpl &InVals) const {
250251 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
251252 CCValAssign &VA = ArgLocs[i];
252253
253 SDValue Arg = Outs[i].Val;
254 SDValue Arg = OutVals[i];
254255
255256 // Promote the value if needed.
256257 switch (VA.getLocInfo()) {
469470 AlphaTargetLowering::LowerReturn(SDValue Chain,
470471 CallingConv::ID CallConv, bool isVarArg,
471472 const SmallVectorImpl &Outs,
473 const SmallVectorImpl &OutVals,
472474 DebugLoc dl, SelectionDAG &DAG) const {
473475
474476 SDValue Copy = DAG.getCopyToReg(Chain, dl, Alpha::R26,
482484 break;
483485 //return SDValue(); // ret void is legal
484486 case 1: {
485 EVT ArgVT = Outs[0].Val.getValueType();
487 EVT ArgVT = Outs[0].VT;
486488 unsigned ArgReg;
487489 if (ArgVT.isInteger())
488490 ArgReg = Alpha::R0;
491493 ArgReg = Alpha::F0;
492494 }
493495 Copy = DAG.getCopyToReg(Copy, dl, ArgReg,
494 Outs[0].Val, Copy.getValue(1));
496 OutVals[0], Copy.getValue(1));
495497 if (DAG.getMachineFunction().getRegInfo().liveout_empty())
496498 DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg);
497499 break;
498500 }
499501 case 2: {
500 EVT ArgVT = Outs[0].Val.getValueType();
502 EVT ArgVT = Outs[0].VT;
501503 unsigned ArgReg1, ArgReg2;
502504 if (ArgVT.isInteger()) {
503505 ArgReg1 = Alpha::R0;
508510 ArgReg2 = Alpha::F1;
509511 }
510512 Copy = DAG.getCopyToReg(Copy, dl, ArgReg1,
511 Outs[0].Val, Copy.getValue(1));
513 OutVals[0], Copy.getValue(1));
512514 if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
513515 DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg1)
514516 == DAG.getMachineFunction().getRegInfo().liveout_end())
515517 DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg1);
516518 Copy = DAG.getCopyToReg(Copy, dl, ArgReg2,
517 Outs[1].Val, Copy.getValue(1));
519 OutVals[1], Copy.getValue(1));
518520 if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
519521 DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg2)
520522 == DAG.getMachineFunction().getRegInfo().liveout_end())
120120 LowerCall(SDValue Chain, SDValue Callee,
121121 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
122122 const SmallVectorImpl &Outs,
123 const SmallVectorImpl &OutVals,
123124 const SmallVectorImpl &Ins,
124125 DebugLoc dl, SelectionDAG &DAG,
125126 SmallVectorImpl &InVals) const;
128129 LowerReturn(SDValue Chain,
129130 CallingConv::ID CallConv, bool isVarArg,
130131 const SmallVectorImpl &Outs,
132 const SmallVectorImpl &OutVals,
131133 DebugLoc dl, SelectionDAG &DAG) const;
132134 };
133135 }
218218 BlackfinTargetLowering::LowerReturn(SDValue Chain,
219219 CallingConv::ID CallConv, bool isVarArg,
220220 const SmallVectorImpl &Outs,
221 const SmallVectorImpl &OutVals,
221222 DebugLoc dl, SelectionDAG &DAG) const {
222223
223224 // CCValAssign - represent the assignment of the return value to locations.
243244 for (unsigned i = 0; i != RVLocs.size(); ++i) {
244245 CCValAssign &VA = RVLocs[i];
245246 assert(VA.isRegLoc() && "Can only return in registers!");
246 SDValue Opi = Outs[i].Val;
247 SDValue Opi = OutVals[i];
247248
248249 // Expand to i32 if necessary
249250 switch (VA.getLocInfo()) {
276277 CallingConv::ID CallConv, bool isVarArg,
277278 bool &isTailCall,
278279 const SmallVectorImpl &Outs,
280 const SmallVectorImpl &OutVals,
279281 const SmallVectorImpl &Ins,
280282 DebugLoc dl, SelectionDAG &DAG,
281283 SmallVectorImpl &InVals) const {
299301 // Walk the register/memloc assignments, inserting copies/loads.
300302 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
301303 CCValAssign &VA = ArgLocs[i];
302 SDValue Arg = Outs[i].Val;
304 SDValue Arg = OutVals[i];
303305
304306 // Promote the value if needed.
305307 switch (VA.getLocInfo()) {
6262 LowerCall(SDValue Chain, SDValue Callee,
6363 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
6464 const SmallVectorImpl &Outs,
65 const SmallVectorImpl &OutVals,
6566 const SmallVectorImpl &Ins,
6667 DebugLoc dl, SelectionDAG &DAG,
6768 SmallVectorImpl &InVals) const;
7071 LowerReturn(SDValue Chain,
7172 CallingConv::ID CallConv, bool isVarArg,
7273 const SmallVectorImpl &Outs,
74 const SmallVectorImpl &OutVals,
7375 DebugLoc dl, SelectionDAG &DAG) const;
7476 };
7577 } // end namespace llvm
11341134 CallingConv::ID CallConv, bool isVarArg,
11351135 bool &isTailCall,
11361136 const SmallVectorImpl &Outs,
1137 const SmallVectorImpl &OutVals,
11371138 const SmallVectorImpl &Ins,
11381139 DebugLoc dl, SelectionDAG &DAG,
11391140 SmallVectorImpl &InVals) const {
11651166 SmallVector MemOpChains;
11661167
11671168 for (unsigned i = 0; i != NumOps; ++i) {
1168 SDValue Arg = Outs[i].Val;
1169 SDValue Arg = OutVals[i];
11691170
11701171 // PtrOff will be used to store the current argument to the stack if a
11711172 // register cannot be found for it.
13381339 SPUTargetLowering::LowerReturn(SDValue Chain,
13391340 CallingConv::ID CallConv, bool isVarArg,
13401341 const SmallVectorImpl &Outs,
1342 const SmallVectorImpl &OutVals,
13411343 DebugLoc dl, SelectionDAG &DAG) const {
13421344
13431345 SmallVector RVLocs;
13591361 CCValAssign &VA = RVLocs[i];
13601362 assert(VA.isRegLoc() && "Can only return in registers!");
13611363 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1362 Outs[i].Val, Flag);
1364 OutVals[i], Flag);
13631365 Flag = Chain.getValue(1);
13641366 }
13651367
158158 CallingConv::ID CallConv, bool isVarArg,
159159 bool &isTailCall,
160160 const SmallVectorImpl &Outs,
161 const SmallVectorImpl &OutVals,
161162 const SmallVectorImpl &Ins,
162163 DebugLoc dl, SelectionDAG &DAG,
163164 SmallVectorImpl &InVals) const;
166167 LowerReturn(SDValue Chain,
167168 CallingConv::ID CallConv, bool isVarArg,
168169 const SmallVectorImpl &Outs,
170 const SmallVectorImpl &OutVals,
169171 DebugLoc dl, SelectionDAG &DAG) const;
170172 };
171173 }
524524 LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
525525 bool isVarArg, bool &isTailCall,
526526 const SmallVectorImpl &Outs,
527 const SmallVectorImpl &OutVals,
527528 const SmallVectorImpl &Ins,
528529 DebugLoc dl, SelectionDAG &DAG,
529530 SmallVectorImpl &InVals) const {
555556 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
556557 CCValAssign &VA = ArgLocs[i];
557558 EVT RegVT = VA.getLocVT();
558 SDValue Arg = Outs[i].Val;
559 SDValue Arg = OutVals[i];
559560
560561 // Promote the value if needed.
561562 switch (VA.getLocInfo()) {
834835 SDValue MBlazeTargetLowering::
835836 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
836837 const SmallVectorImpl &Outs,
838 const SmallVectorImpl &OutVals,
837839 DebugLoc dl, SelectionDAG &DAG) const {
838840 // CCValAssign - represent the assignment of
839841 // the return value to a location
862864 assert(VA.isRegLoc() && "Can only return in registers!");
863865
864866 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
865 Outs[i].Val, Flag);
867 OutVals[i], Flag);
866868
867869 // guarantee that all emitted copies are
868870 // stuck together, avoiding something bad
108108 CallingConv::ID CallConv, bool isVarArg,
109109 bool &isTailCall,
110110 const SmallVectorImpl &Outs,
111 const SmallVectorImpl &OutVals,
111112 const SmallVectorImpl &Ins,
112113 DebugLoc dl, SelectionDAG &DAG,
113114 SmallVectorImpl &InVals) const;
116117 LowerReturn(SDValue Chain,
117118 CallingConv::ID CallConv, bool isVarArg,
118119 const SmallVectorImpl &Outs,
120 const SmallVectorImpl &OutVals,
119121 DebugLoc dl, SelectionDAG &DAG) const;
120122
121123 virtual MachineBasicBlock *
277277 CallingConv::ID CallConv, bool isVarArg,
278278 bool &isTailCall,
279279 const SmallVectorImpl &Outs,
280 const SmallVectorImpl &OutVals,
280281 const SmallVectorImpl &Ins,
281282 DebugLoc dl, SelectionDAG &DAG,
282283 SmallVectorImpl &InVals) const {
289290 case CallingConv::Fast:
290291 case CallingConv::C:
291292 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
292 Outs, Ins, dl, DAG, InVals);
293 Outs, OutVals, Ins, dl, DAG, InVals);
293294 case CallingConv::MSP430_INTR:
294295 report_fatal_error("ISRs cannot be called directly");
295296 return SDValue();
386387 MSP430TargetLowering::LowerReturn(SDValue Chain,
387388 CallingConv::ID CallConv, bool isVarArg,
388389 const SmallVectorImpl &Outs,
390 const SmallVectorImpl &OutVals,
389391 DebugLoc dl, SelectionDAG &DAG) const {
390392
391393 // CCValAssign - represent the assignment of the return value to a location
420422 assert(VA.isRegLoc() && "Can only return in registers!");
421423
422424 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
423 Outs[i].Val, Flag);
425 OutVals[i], Flag);
424426
425427 // Guarantee that all emitted copies are stuck together,
426428 // avoiding something bad.
446448 bool isTailCall,
447449 const SmallVectorImpl
448450 &Outs,
451 const SmallVectorImpl &OutVals,
449452 const SmallVectorImpl &Ins,
450453 DebugLoc dl, SelectionDAG &DAG,
451454 SmallVectorImpl &InVals) const {
470473 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
471474 CCValAssign &VA = ArgLocs[i];
472475
473 SDValue Arg = Outs[i].Val;
476 SDValue Arg = OutVals[i];
474477
475478 // Promote the value if needed.
476479 switch (VA.getLocInfo()) {
126126 CallingConv::ID CallConv, bool isVarArg,
127127 bool isTailCall,
128128 const SmallVectorImpl &Outs,
129 const SmallVectorImpl &OutVals,
129130 const SmallVectorImpl &Ins,
130131 DebugLoc dl, SelectionDAG &DAG,
131132 SmallVectorImpl &InVals) const;
154155 LowerCall(SDValue Chain, SDValue Callee,
155156 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
156157 const SmallVectorImpl &Outs,
158 const SmallVectorImpl &OutVals,
157159 const SmallVectorImpl &Ins,
158160 DebugLoc dl, SelectionDAG &DAG,
159161 SmallVectorImpl &InVals) const;
162164 LowerReturn(SDValue Chain,
163165 CallingConv::ID CallConv, bool isVarArg,
164166 const SmallVectorImpl &Outs,
167 const SmallVectorImpl &OutVals,
165168 DebugLoc dl, SelectionDAG &DAG) const;
166169
167170 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
766766 CallingConv::ID CallConv, bool isVarArg,
767767 bool &isTailCall,
768768 const SmallVectorImpl &Outs,
769 const SmallVectorImpl &OutVals,
769770 const SmallVectorImpl &Ins,
770771 DebugLoc dl, SelectionDAG &DAG,
771772 SmallVectorImpl &InVals) const {
806807
807808 // Walk the register/memloc assignments, inserting copies/loads.
808809 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
809 SDValue Arg = Outs[i].Val;
810 SDValue Arg = OutVals[i];
810811 CCValAssign &VA = ArgLocs[i];
811812
812813 // Promote the value if needed.
11671168 MipsTargetLowering::LowerReturn(SDValue Chain,
11681169 CallingConv::ID CallConv, bool isVarArg,
11691170 const SmallVectorImpl &Outs,
1171 const SmallVectorImpl &OutVals,
11701172 DebugLoc dl, SelectionDAG &DAG) const {
11711173
11721174 // CCValAssign - represent the assignment of
11961198 assert(VA.isRegLoc() && "Can only return in registers!");
11971199
11981200 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1199 Outs[i].Val, Flag);
1201 OutVals[i], Flag);
12001202
12011203 // guarantee that all emitted copies are
12021204 // stuck together, avoiding something bad
119119 CallingConv::ID CallConv, bool isVarArg,
120120 bool &isTailCall,
121121 const SmallVectorImpl &Outs,
122 const SmallVectorImpl &OutVals,
122123 const SmallVectorImpl &Ins,
123124 DebugLoc dl, SelectionDAG &DAG,
124125 SmallVectorImpl &InVals) const;
127128 LowerReturn(SDValue Chain,
128129 CallingConv::ID CallConv, bool isVarArg,
129130 const SmallVectorImpl &Outs,
131 const SmallVectorImpl &OutVals,
130132 DebugLoc dl, SelectionDAG &DAG) const;
131133
132134 virtual MachineBasicBlock *
11201120 LowerIndirectCallArguments(SDValue Chain, SDValue InFlag,
11211121 SDValue DataAddr_Lo, SDValue DataAddr_Hi,
11221122 const SmallVectorImpl &Outs,
1123 const SmallVectorImpl &OutVals,
11231124 const SmallVectorImpl &Ins,
11241125 DebugLoc dl, SelectionDAG &DAG) const {
11251126 unsigned NumOps = Outs.size();
11361137 unsigned RetVals = Ins.size();
11371138 for (unsigned i = 0, ArgOffset = RetVals; i < NumOps; i++) {
11381139 // Get the arguments
1139 Arg = Outs[i].Val;
1140 Arg = OutVals[i];
11401141
11411142 Ops.clear();
11421143 Ops.push_back(Chain);
11581159 SDValue PIC16TargetLowering::
11591160 LowerDirectCallArguments(SDValue ArgLabel, SDValue Chain, SDValue InFlag,
11601161 const SmallVectorImpl &Outs,
1162 const SmallVectorImpl &OutVals,
11611163 DebugLoc dl, SelectionDAG &DAG) const {
11621164 unsigned NumOps = Outs.size();
11631165 std::string Name;
11831185 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
11841186 for (unsigned i=0, Offset = 0; i
11851187 // Get the argument
1186 Arg = Outs[i].Val;
1188 Arg = OutVals[i];
11871189 StoreOffset = (Offset + AddressOffset);
11881190
11891191 // Store the argument on frame
12821284 PIC16TargetLowering::LowerReturn(SDValue Chain,
12831285 CallingConv::ID CallConv, bool isVarArg,
12841286 const SmallVectorImpl &Outs,
1287 const SmallVectorImpl &OutVals,
12851288 DebugLoc dl, SelectionDAG &DAG) const {
12861289
12871290 // Number of values to return
12981301 SDValue BS = DAG.getConstant(1, MVT::i8);
12991302 SDValue RetVal;
13001303 for(unsigned i=0;i
1301 RetVal = Outs[i].Val;
1304 RetVal = OutVals[i];
13021305 Chain = DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, RetVal,
13031306 ES, BS,
13041307 DAG.getConstant (i, MVT::i8));
13741377 CallingConv::ID CallConv, bool isVarArg,
13751378 bool &isTailCall,
13761379 const SmallVectorImpl &Outs,
1380 const SmallVectorImpl &OutVals,
13771381 const SmallVectorImpl &Ins,
13781382 DebugLoc dl, SelectionDAG &DAG,
13791383 SmallVectorImpl &InVals) const {
14611465 SDValue CallArgs;
14621466 if (IsDirectCall) {
14631467 CallArgs = LowerDirectCallArguments(ArgLabel, Chain, OperFlag,
1464 Outs, dl, DAG);
1468 Outs, OutVals, dl, DAG);
14651469 Chain = getChain(CallArgs);
14661470 OperFlag = getOutFlag(CallArgs);
14671471 } else {
14681472 CallArgs = LowerIndirectCallArguments(Chain, OperFlag, DataAddr_Lo,
1469 DataAddr_Hi, Outs, Ins, dl, DAG);
1473 DataAddr_Hi, Outs, OutVals, Ins,
1474 dl, DAG);
14701475 Chain = getChain(CallArgs);
14711476 OperFlag = getOutFlag(CallArgs);
14721477 }
105105 SDValue
106106 LowerDirectCallArguments(SDValue ArgLabel, SDValue Chain, SDValue InFlag,
107107 const SmallVectorImpl &Outs,
108 const SmallVectorImpl &OutVals,
108109 DebugLoc dl, SelectionDAG &DAG) const;
109110
110111 SDValue
111112 LowerIndirectCallArguments(SDValue Chain, SDValue InFlag,
112113 SDValue DataAddr_Lo, SDValue DataAddr_Hi,
113114 const SmallVectorImpl &Outs,
115 const SmallVectorImpl &OutVals,
114116 const SmallVectorImpl &Ins,
115117 DebugLoc dl, SelectionDAG &DAG) const;
116118
142144 LowerCall(SDValue Chain, SDValue Callee,
143145 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
144146 const SmallVectorImpl &Outs,
147 const SmallVectorImpl &OutVals,
145148 const SmallVectorImpl &Ins,
146149 DebugLoc dl, SelectionDAG &DAG,
147150 SmallVectorImpl &InVals) const;
150153 LowerReturn(SDValue Chain,
151154 CallingConv::ID CallConv, bool isVarArg,
152155 const SmallVectorImpl &Outs,
156 const SmallVectorImpl &OutVals,
153157 DebugLoc dl, SelectionDAG &DAG) const;
154158
155159 SDValue ExpandStore(SDNode *N, SelectionDAG &DAG) const;
21352135 unsigned CC,
21362136 const SmallVectorImpl
21372137 &Outs,
2138 const SmallVectorImpl &OutVals,
21382139 unsigned &nAltivecParamsAtEnd) {
21392140 // Count how many bytes are to be pushed on the stack, including the linkage
21402141 // area, and parameter passing area. We start with 24/48 bytes, which is
21512152 // 16-byte aligned.
21522153 nAltivecParamsAtEnd = 0;
21532154 for (unsigned i = 0; i != NumOps; ++i) {
2154 SDValue Arg = Outs[i].Val;
2155 SDValue Arg = OutVals[i];
21552156 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2156 EVT ArgVT = Arg.getValueType();
2157 EVT ArgVT = Outs[i].VT;
21572158 // Varargs Altivec parameters are padded to a 16 byte boundary.
21582159 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
21592160 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
27032704 CallingConv::ID CallConv, bool isVarArg,
27042705 bool &isTailCall,
27052706 const SmallVectorImpl &Outs,
2707 const SmallVectorImpl &OutVals,
27062708 const SmallVectorImpl &Ins,
27072709 DebugLoc dl, SelectionDAG &DAG,
27082710 SmallVectorImpl &InVals) const {
27122714
27132715 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) {
27142716 return LowerCall_SVR4(Chain, Callee, CallConv, isVarArg,
2715 isTailCall, Outs, Ins,
2717 isTailCall, Outs, OutVals, Ins,
27162718 dl, DAG, InVals);
27172719 } else {
27182720 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
2719 isTailCall, Outs, Ins,
2721 isTailCall, Outs, OutVals, Ins,
27202722 dl, DAG, InVals);
27212723 }
27222724 }
27262728 CallingConv::ID CallConv, bool isVarArg,
27272729 bool isTailCall,
27282730 const SmallVectorImpl &Outs,
2731 const SmallVectorImpl &OutVals,
27292732 const SmallVectorImpl &Ins,
27302733 DebugLoc dl, SelectionDAG &DAG,
27312734 SmallVectorImpl &InVals) const {
27662769 unsigned NumArgs = Outs.size();
27672770
27682771 for (unsigned i = 0; i != NumArgs; ++i) {
2769 EVT ArgVT = Outs[i].Val.getValueType();
2772 EVT ArgVT = Outs[i].VT;
27702773 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
27712774 bool Result;
27722775
28352838 i != e;
28362839 ++i) {
28372840 CCValAssign &VA = ArgLocs[i];
2838 SDValue Arg = Outs[i].Val;
2841 SDValue Arg = OutVals[i];
28392842 ISD::ArgFlagsTy Flags = Outs[i].Flags;
28402843
28412844 if (Flags.isByVal()) {
29312934 CallingConv::ID CallConv, bool isVarArg,
29322935 bool isTailCall,
29332936 const SmallVectorImpl &Outs,
2937 const SmallVectorImpl &OutVals,
29342938 const SmallVectorImpl &Ins,
29352939 DebugLoc dl, SelectionDAG &DAG,
29362940 SmallVectorImpl &InVals) const {
29582962 // prereserved space for [SP][CR][LR][3 x unused].
29592963 unsigned NumBytes =
29602964 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
2961 Outs,
2965 Outs, OutVals,
29622966 nAltivecParamsAtEnd);
29632967
29642968 // Calculate by how many bytes the stack has to be adjusted in case of tail
30223026
30233027 SmallVector MemOpChains;
30243028 for (unsigned i = 0; i != NumOps; ++i) {
3025 SDValue Arg = Outs[i].Val;
3029 SDValue Arg = OutVals[i];
30263030 ISD::ArgFlagsTy Flags = Outs[i].Flags;
30273031
30283032 // PtrOff will be used to store the current argument to the stack if a
32253229 ArgOffset = ((ArgOffset+15)/16)*16;
32263230 ArgOffset += 12*16;
32273231 for (unsigned i = 0; i != NumOps; ++i) {
3228 SDValue Arg = Outs[i].Val;
3229 EVT ArgType = Arg.getValueType();
3232 SDValue Arg = OutVals[i];
3233 EVT ArgType = Outs[i].VT;
32303234 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
32313235 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
32323236 if (++j > NumVRs) {
32943298 PPCTargetLowering::LowerReturn(SDValue Chain,
32953299 CallingConv::ID CallConv, bool isVarArg,
32963300 const SmallVectorImpl &Outs,
3301 const SmallVectorImpl &OutVals,
32973302 DebugLoc dl, SelectionDAG &DAG) const {
32983303
32993304 SmallVector RVLocs;
33153320 CCValAssign &VA = RVLocs[i];
33163321 assert(VA.isRegLoc() && "Can only return in registers!");
33173322 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3318 Outs[i].Val, Flag);
3323 OutVals[i], Flag);
33193324 Flag = Chain.getValue(1);
33203325 }
33213326
434434 LowerCall(SDValue Chain, SDValue Callee,
435435 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
436436 const SmallVectorImpl &Outs,
437 const SmallVectorImpl &OutVals,
437438 const SmallVectorImpl &Ins,
438439 DebugLoc dl, SelectionDAG &DAG,
439440 SmallVectorImpl &InVals) const;
442443 LowerReturn(SDValue Chain,
443444 CallingConv::ID CallConv, bool isVarArg,
444445 const SmallVectorImpl &Outs,
446 const SmallVectorImpl &OutVals,
445447 DebugLoc dl, SelectionDAG &DAG) const;
446448
447449 SDValue
461463 LowerCall_Darwin(SDValue Chain, SDValue Callee,
462464 CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
463465 const SmallVectorImpl &Outs,
466 const SmallVectorImpl &OutVals,
464467 const SmallVectorImpl &Ins,
465468 DebugLoc dl, SelectionDAG &DAG,
466469 SmallVectorImpl &InVals) const;
468471 LowerCall_SVR4(SDValue Chain, SDValue Callee,
469472 CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
470473 const SmallVectorImpl &Outs,
474 const SmallVectorImpl &OutVals,
471475 const SmallVectorImpl &Ins,
472476 DebugLoc dl, SelectionDAG &DAG,
473477 SmallVectorImpl &InVals) const;
3737 SparcTargetLowering::LowerReturn(SDValue Chain,
3838 CallingConv::ID CallConv, bool isVarArg,
3939 const SmallVectorImpl &Outs,
40 const SmallVectorImpl &OutVals,
4041 DebugLoc dl, SelectionDAG &DAG) const {
4142
4243 // CCValAssign - represent the assignment of the return value to locations.
6566 assert(VA.isRegLoc() && "Can only return in registers!");
6667
6768 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
68 Outs[i].Val, Flag);
69 OutVals[i], Flag);
6970
7071 // Guarantee that all emitted copies are stuck together with flags.
7172 Flag = Chain.getValue(1);
261262 CallingConv::ID CallConv, bool isVarArg,
262263 bool &isTailCall,
263264 const SmallVectorImpl &Outs,
265 const SmallVectorImpl &OutVals,
264266 const SmallVectorImpl &Ins,
265267 DebugLoc dl, SelectionDAG &DAG,
266268 SmallVectorImpl &InVals) const {
282284 // Count the size of the outgoing arguments.
283285 unsigned ArgsSize = 0;
284286 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
285 switch (Outs[i].Val.getValueType().getSimpleVT().SimpleTy) {
287 switch (Outs[i].VT.getSimpleVT().SimpleTy) {
286288 default: llvm_unreachable("Unknown value type!");
287289 case MVT::i1:
288290 case MVT::i8:
315317 // Walk the register/memloc assignments, inserting copies/loads.
316318 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
317319 CCValAssign &VA = ArgLocs[i];
318 SDValue Arg = Outs[i].Val;
320 SDValue Arg = OutVals[i];
319321
320322 // Promote the value if needed.
321323 switch (VA.getLocInfo()) {
357359 unsigned ArgOffset = 68;
358360
359361 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
360 SDValue Val = Outs[i].Val;
361 EVT ObjectVT = Val.getValueType();
362 SDValue Val = OutVals[i];
363 EVT ObjectVT = Outs[i].VT;
362364 SDValue ValToStore(0, 0);
363365 unsigned ObjSize;
364366 switch (ObjectVT.getSimpleVT().SimpleTy) {
8585 CallingConv::ID CallConv, bool isVarArg,
8686 bool &isTailCall,
8787 const SmallVectorImpl &Outs,
88 const SmallVectorImpl &OutVals,
8889 const SmallVectorImpl &Ins,
8990 DebugLoc dl, SelectionDAG &DAG,
9091 SmallVectorImpl &InVals) const;
9394 LowerReturn(SDValue Chain,
9495 CallingConv::ID CallConv, bool isVarArg,
9596 const SmallVectorImpl &Outs,
97 const SmallVectorImpl &OutVals,
9698 DebugLoc dl, SelectionDAG &DAG) const;
9799
98100 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
253253 CallingConv::ID CallConv, bool isVarArg,
254254 bool &isTailCall,
255255 const SmallVectorImpl &Outs,
256 const SmallVectorImpl &OutVals,
256257 const SmallVectorImpl &Ins,
257258 DebugLoc dl, SelectionDAG &DAG,
258259 SmallVectorImpl &InVals) const {
265266 case CallingConv::Fast:
266267 case CallingConv::C:
267268 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
268 Outs, Ins, dl, DAG, InVals);
269 Outs, OutVals, Ins, dl, DAG, InVals);
269270 }
270271 }
271272
371372 bool isTailCall,
372373 const SmallVectorImpl
373374 &Outs,
375 const SmallVectorImpl &OutVals,
374376 const SmallVectorImpl &Ins,
375377 DebugLoc dl, SelectionDAG &DAG,
376378 SmallVectorImpl &InVals) const {
401403 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
402404 CCValAssign &VA = ArgLocs[i];
403405
404 SDValue Arg = Outs[i].Val;
406 SDValue Arg = OutVals[i];
405407
406408 // Promote the value if needed.
407409 switch (VA.getLocInfo()) {
549551 SystemZTargetLowering::LowerReturn(SDValue Chain,
550552 CallingConv::ID CallConv, bool isVarArg,
551553 const SmallVectorImpl &Outs,
554 const SmallVectorImpl &OutVals,
552555 DebugLoc dl, SelectionDAG &DAG) const {
553556
554557 // CCValAssign - represent the assignment of the return value to a location
574577 // Copy the result values into the output registers.
575578 for (unsigned i = 0; i != RVLocs.size(); ++i) {
576579 CCValAssign &VA = RVLocs[i];
577 SDValue ResValue = Outs[i].Val;
580 SDValue ResValue = OutVals[i];
578581 assert(VA.isRegLoc() && "Can only return in registers!");
579582
580583 // If this is an 8/16/32-bit value, it is really should be passed promoted
9797 CallingConv::ID CallConv, bool isVarArg,
9898 bool isTailCall,
9999 const SmallVectorImpl &Outs,
100 const SmallVectorImpl &OutVals,
100101 const SmallVectorImpl &Ins,
101102 DebugLoc dl, SelectionDAG &DAG,
102103 SmallVectorImpl &InVals) const;
125126 LowerCall(SDValue Chain, SDValue Callee,
126127 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
127128 const SmallVectorImpl &Outs,
129 const SmallVectorImpl &OutVals,
128130 const SmallVectorImpl &Ins,
129131 DebugLoc dl, SelectionDAG &DAG,
130132 SmallVectorImpl &InVals) const;
133135 LowerReturn(SDValue Chain,
134136 CallingConv::ID CallConv, bool isVarArg,
135137 const SmallVectorImpl &Outs,
138 const SmallVectorImpl &OutVals,
136139 DebugLoc dl, SelectionDAG &DAG) const;
137140
138141 const SystemZSubtarget &Subtarget;
12301230 X86TargetLowering::LowerReturn(SDValue Chain,
12311231 CallingConv::ID CallConv, bool isVarArg,
12321232 const SmallVectorImpl &Outs,
1233 const SmallVectorImpl &OutVals,
12331234 DebugLoc dl, SelectionDAG &DAG) const {
12341235 MachineFunction &MF = DAG.getMachineFunction();
12351236 X86MachineFunctionInfo *FuncInfo = MF.getInfo();
12571258 for (unsigned i = 0; i != RVLocs.size(); ++i) {
12581259 CCValAssign &VA = RVLocs[i];
12591260 assert(VA.isRegLoc() && "Can only return in registers!");
1260 SDValue ValToCopy = Outs[i].Val;
1261 SDValue ValToCopy = OutVals[i];
12611262
12621263 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
12631264 // the RET instruction and handled by the FP Stackifier.
18151816 CallingConv::ID CallConv, bool isVarArg,
18161817 bool &isTailCall,
18171818 const SmallVectorImpl &Outs,
1819 const SmallVectorImpl &OutVals,
18181820 const SmallVectorImpl &Ins,
18191821 DebugLoc dl, SelectionDAG &DAG,
18201822 SmallVectorImpl &InVals) const {
18271829 // Check if it's really possible to do a tail call.
18281830 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
18291831 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1830 Outs, Ins, DAG);
1832 Outs, OutVals, Ins, DAG);
18311833
18321834 // Sibcalls are automatically detected tailcalls which do not require
18331835 // ABI changes.
18871889 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
18881890 CCValAssign &VA = ArgLocs[i];
18891891 EVT RegVT = VA.getLocVT();
1890 SDValue Arg = Outs[i].Val;
1892 SDValue Arg = OutVals[i];
18911893 ISD::ArgFlagsTy Flags = Outs[i].Flags;
18921894 bool isByVal = Flags.isByVal();
18931895
20262028 if (VA.isRegLoc())
20272029 continue;
20282030 assert(VA.isMemLoc());
2029 SDValue Arg = Outs[i].Val;
2031 SDValue Arg = OutVals[i];
20302032 ISD::ArgFlagsTy Flags = Outs[i].Flags;
20312033 // Create frame index.
20322034 int32_t Offset = VA.getLocMemOffset()+FPDiff;
23192321 bool isCalleeStructRet,
23202322 bool isCallerStructRet,
23212323 const SmallVectorImpl &Outs,
2324 const SmallVectorImpl &OutVals,
23222325 const SmallVectorImpl &Ins,
23232326 SelectionDAG& DAG) const {
23242327 if (!IsTailCallConvention(CalleeCC) &&
24322435 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
24332436 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
24342437 CCValAssign &VA = ArgLocs[i];
2435 SDValue Arg = Outs[i].Val;
2438 SDValue Arg = OutVals[i];
24362439 ISD::ArgFlagsTy Flags = Outs[i].Flags;
24372440 if (VA.getLocInfo() == CCValAssign::Indirect)
24382441 return false;
651651 bool isCalleeStructRet,
652652 bool isCallerStructRet,
653653 const SmallVectorImpl &Outs,
654 const SmallVectorImpl &OutVals,
654655 const SmallVectorImpl &Ins,
655656 SelectionDAG& DAG) const;
656657 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
733734 LowerCall(SDValue Chain, SDValue Callee,
734735 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
735736 const SmallVectorImpl &Outs,
737 const SmallVectorImpl &OutVals,
736738 const SmallVectorImpl &Ins,
737739 DebugLoc dl, SelectionDAG &DAG,
738740 SmallVectorImpl &InVals) const;
741743 LowerReturn(SDValue Chain,
742744 CallingConv::ID CallConv, bool isVarArg,
743745 const SmallVectorImpl &Outs,
746 const SmallVectorImpl &OutVals,
744747 DebugLoc dl, SelectionDAG &DAG) const;
745748
746749 virtual bool
811811 CallingConv::ID CallConv, bool isVarArg,
812812 bool &isTailCall,
813813 const SmallVectorImpl &Outs,
814 const SmallVectorImpl &OutVals,
814815 const SmallVectorImpl &Ins,
815816 DebugLoc dl, SelectionDAG &DAG,
816817 SmallVectorImpl &InVals) const {
825826 case CallingConv::Fast:
826827 case CallingConv::C:
827828 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
828 Outs, Ins, dl, DAG, InVals);
829 Outs, OutVals, Ins, dl, DAG, InVals);
829830 }
830831 }
831832
838839 CallingConv::ID CallConv, bool isVarArg,
839840 bool isTailCall,
840841 const SmallVectorImpl &Outs,
842 const SmallVectorImpl &OutVals,
841843 const SmallVectorImpl &Ins,
842844 DebugLoc dl, SelectionDAG &DAG,
843845 SmallVectorImpl &InVals) const {
865867 // Walk the register/memloc assignments, inserting copies/loads.
866868 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
867869 CCValAssign &VA = ArgLocs[i];
868 SDValue Arg = Outs[i].Val;
870 SDValue Arg = OutVals[i];
869871
870872 // Promote the value if needed.
871873 switch (VA.getLocInfo()) {
11451147 XCoreTargetLowering::LowerReturn(SDValue Chain,
11461148 CallingConv::ID CallConv, bool isVarArg,
11471149 const SmallVectorImpl &Outs,
1150 const SmallVectorImpl &OutVals,
11481151 DebugLoc dl, SelectionDAG &DAG) const {
11491152
11501153 // CCValAssign - represent the assignment of
11741177 assert(VA.isRegLoc() && "Can only return in registers!");
11751178
11761179 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1177 Outs[i].Val, Flag);
1180 OutVals[i], Flag);
11781181
11791182 // guarantee that all emitted copies are
11801183 // stuck together, avoiding something bad
119119 CallingConv::ID CallConv, bool isVarArg,
120120 bool isTailCall,
121121 const SmallVectorImpl &Outs,
122 const SmallVectorImpl &OutVals,
122123 const SmallVectorImpl &Ins,
123124 DebugLoc dl, SelectionDAG &DAG,
124125 SmallVectorImpl &InVals) const;
177178 CallingConv::ID CallConv, bool isVarArg,
178179 bool &isTailCall,
179180 const SmallVectorImpl &Outs,
181 const SmallVectorImpl &OutVals,
180182 const SmallVectorImpl &Ins,
181183 DebugLoc dl, SelectionDAG &DAG,
182184 SmallVectorImpl &InVals) const;
185187 LowerReturn(SDValue Chain,
186188 CallingConv::ID CallConv, bool isVarArg,
187189 const SmallVectorImpl &Outs,
190 const SmallVectorImpl &OutVals,
188191 DebugLoc dl, SelectionDAG &DAG) const;
189192
190193 virtual bool