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Define classes and multiclasses for FP binary instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141475 91177308-0d34-0410-b5e6-96231b3b80d8 Akira Hatanaka 8 years ago
2 changed file(s) with 15 addition(s) and 15 deletion(s). Raw diff Collapse all Expand all
9797 Requires<[IsFP64bit]>;
9898 }
9999
100 multiclass FFR1_4 funct, string asmstr, SDNode FOp, bit isComm = 0> {
100 multiclass FFR2P_M funct, string opstr, SDNode OpNode, bit isComm = 0> {
101101 let isCommutable = isComm in {
102 def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd),
103 (ins FGR32:$fs, FGR32:$ft),
104 !strconcat(asmstr, ".s\t$fd, $fs, $ft"),
105 [(set FGR32:$fd, (FOp FGR32:$fs, FGR32:$ft))]>;
106
107 def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd),
108 (ins AFGR64:$fs, AFGR64:$ft),
109 !strconcat(asmstr, ".d\t$fd, $fs, $ft"),
110 [(set AFGR64:$fd, (FOp AFGR64:$fs, AFGR64:$ft))]>,
111 Requires<[NotFP64bit]>;
102 def _S : FFR2P>;
103 def _D32 : FFR2P,
104 Requires<[NotFP64bit]>;
105 def _D64 : FFR2P,
106 Requires<[IsFP64bit]>;
112107 }
113108 }
114109
188183 "swc1\t$ft, $addr", [(store FGR32:$ft, addr:$addr)]>;
189184
190185 /// Floating-point Aritmetic
191 defm FADD : FFR1_4<0x10, "add", fadd, 1>;
192 defm FDIV : FFR1_4<0x03, "div", fdiv>;
193 defm FMUL : FFR1_4<0x02, "mul", fmul, 1>;
194 defm FSUB : FFR1_4<0x01, "sub", fsub>;
186 defm FADD : FFR2P_M<0x10, "add", fadd, 1>;
187 defm FDIV : FFR2P_M<0x03, "div", fdiv>;
188 defm FMUL : FFR2P_M<0x02, "mul", fmul, 1>;
189 defm FSUB : FFR2P_M<0x01, "sub", fsub>;
195190
196191 //===----------------------------------------------------------------------===//
197192 // Floating Point Branch Codes
244244 let ft = 0;
245245 }
246246
247 class FFR2P funct, bits<5> fmt, string opstr,
248 string fmtstr, RegisterClass RC, SDNode OpNode> :
249 FFR<0x11, funct, fmt, (outs RC:$fd), (ins RC:$fs, RC:$ft),
250 !strconcat(opstr, ".", fmtstr, "\t$fd, $fs, $ft"),
251 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))]>;