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[X86][AVX] Add v2f32 <-> v2i8/v2i16/v2i32 vector tests git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326494 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim 2 years ago
1 changed file(s) with 342 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=corei7-avx -mattr=+avx | FileCheck %s
2 ; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=corei7-avx -mattr=+avx -x86-experimental-vector-widening-legalization | FileCheck %s --check-prefix=CHECK-WIDE
3
4 define <2 x float> @cvt_v2i8_v2f32(<2 x i8> %src) {
5 ; CHECK-LABEL: cvt_v2i8_v2f32:
6 ; CHECK: ## %bb.0:
7 ; CHECK-NEXT: vpsllq $56, %xmm0, %xmm0
8 ; CHECK-NEXT: vpsrad $24, %xmm0, %xmm0
9 ; CHECK-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
10 ; CHECK-NEXT: vcvtdq2ps %xmm0, %xmm0
11 ; CHECK-NEXT: retl
12 ;
13 ; CHECK-WIDE-LABEL: cvt_v2i8_v2f32:
14 ; CHECK-WIDE: ## %bb.0:
15 ; CHECK-WIDE-NEXT: vpmovsxbd %xmm0, %xmm0
16 ; CHECK-WIDE-NEXT: vcvtdq2ps %xmm0, %xmm0
17 ; CHECK-WIDE-NEXT: retl
18 %res = sitofp <2 x i8> %src to <2 x float>
19 ret <2 x float> %res
20 }
21
22 define <2 x float> @cvt_v2i16_v2f32(<2 x i16> %src) {
23 ; CHECK-LABEL: cvt_v2i16_v2f32:
24 ; CHECK: ## %bb.0:
25 ; CHECK-NEXT: vpsllq $48, %xmm0, %xmm0
26 ; CHECK-NEXT: vpsrad $16, %xmm0, %xmm0
27 ; CHECK-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
28 ; CHECK-NEXT: vcvtdq2ps %xmm0, %xmm0
29 ; CHECK-NEXT: retl
30 ;
31 ; CHECK-WIDE-LABEL: cvt_v2i16_v2f32:
32 ; CHECK-WIDE: ## %bb.0:
33 ; CHECK-WIDE-NEXT: vpmovsxwd %xmm0, %xmm0
34 ; CHECK-WIDE-NEXT: vcvtdq2ps %xmm0, %xmm0
35 ; CHECK-WIDE-NEXT: retl
36 %res = sitofp <2 x i16> %src to <2 x float>
37 ret <2 x float> %res
38 }
39
40 define <2 x float> @cvt_v2i32_v2f32(<2 x i32> %src) {
41 ; CHECK-LABEL: cvt_v2i32_v2f32:
42 ; CHECK: ## %bb.0:
43 ; CHECK-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,2,3]
44 ; CHECK-NEXT: vcvtdq2ps %xmm0, %xmm0
45 ; CHECK-NEXT: retl
46 ;
47 ; CHECK-WIDE-LABEL: cvt_v2i32_v2f32:
48 ; CHECK-WIDE: ## %bb.0:
49 ; CHECK-WIDE-NEXT: vcvtdq2ps %xmm0, %xmm0
50 ; CHECK-WIDE-NEXT: retl
51 %res = sitofp <2 x i32> %src to <2 x float>
52 ret <2 x float> %res
53 }
54
55 define <2 x float> @cvt_v2u8_v2f32(<2 x i8> %src) {
56 ; CHECK-LABEL: cvt_v2u8_v2f32:
57 ; CHECK: ## %bb.0:
58 ; CHECK-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[u,u,u,u,u,u,u,u]
59 ; CHECK-NEXT: vcvtdq2ps %xmm0, %xmm0
60 ; CHECK-NEXT: retl
61 ;
62 ; CHECK-WIDE-LABEL: cvt_v2u8_v2f32:
63 ; CHECK-WIDE: ## %bb.0:
64 ; CHECK-WIDE-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
65 ; CHECK-WIDE-NEXT: vcvtdq2ps %xmm0, %xmm0
66 ; CHECK-WIDE-NEXT: retl
67 %res = uitofp <2 x i8> %src to <2 x float>
68 ret <2 x float> %res
69 }
70
71 define <2 x float> @cvt_v2u16_v2f32(<2 x i16> %src) {
72 ; CHECK-LABEL: cvt_v2u16_v2f32:
73 ; CHECK: ## %bb.0:
74 ; CHECK-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1],zero,zero,xmm0[8,9],zero,zero,xmm0[8,9],zero,zero,xmm0[10,11],zero,zero
75 ; CHECK-NEXT: vcvtdq2ps %xmm0, %xmm0
76 ; CHECK-NEXT: retl
77 ;
78 ; CHECK-WIDE-LABEL: cvt_v2u16_v2f32:
79 ; CHECK-WIDE: ## %bb.0:
80 ; CHECK-WIDE-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
81 ; CHECK-WIDE-NEXT: vcvtdq2ps %xmm0, %xmm0
82 ; CHECK-WIDE-NEXT: retl
83 %res = uitofp <2 x i16> %src to <2 x float>
84 ret <2 x float> %res
85 }
86
87 define <2 x float> @cvt_v2u32_v2f32(<2 x i32> %src) {
88 ; CHECK-LABEL: cvt_v2u32_v2f32:
89 ; CHECK: ## %bb.0:
90 ; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
91 ; CHECK-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
92 ; CHECK-NEXT: vmovaps {{.*#+}} xmm1 = [4.503600e+15,4.503600e+15]
93 ; CHECK-NEXT: vorps %xmm1, %xmm0, %xmm0
94 ; CHECK-NEXT: vsubpd %xmm1, %xmm0, %xmm0
95 ; CHECK-NEXT: vcvtpd2ps %xmm0, %xmm0
96 ; CHECK-NEXT: retl
97 ;
98 ; CHECK-WIDE-LABEL: cvt_v2u32_v2f32:
99 ; CHECK-WIDE: ## %bb.0:
100 ; CHECK-WIDE-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
101 ; CHECK-WIDE-NEXT: vmovdqa {{.*#+}} xmm1 = [4.503600e+15,4.503600e+15]
102 ; CHECK-WIDE-NEXT: vpor %xmm1, %xmm0, %xmm0
103 ; CHECK-WIDE-NEXT: vsubpd %xmm1, %xmm0, %xmm0
104 ; CHECK-WIDE-NEXT: vcvtpd2ps %xmm0, %xmm0
105 ; CHECK-WIDE-NEXT: retl
106 %res = uitofp <2 x i32> %src to <2 x float>
107 ret <2 x float> %res
108 }
109
110 define <2 x i8> @cvt_v2f32_v2i8(<2 x float> %src) {
111 ; CHECK-LABEL: cvt_v2f32_v2i8:
112 ; CHECK: ## %bb.0:
113 ; CHECK-NEXT: subl $68, %esp
114 ; CHECK-NEXT: .cfi_def_cfa_offset 72
115 ; CHECK-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp)
116 ; CHECK-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp)
117 ; CHECK-NEXT: flds {{[0-9]+}}(%esp)
118 ; CHECK-NEXT: fisttpll {{[0-9]+}}(%esp)
119 ; CHECK-NEXT: flds {{[0-9]+}}(%esp)
120 ; CHECK-NEXT: fisttpll (%esp)
121 ; CHECK-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
122 ; CHECK-NEXT: vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm0
123 ; CHECK-NEXT: vpinsrd $2, (%esp), %xmm0, %xmm0
124 ; CHECK-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0
125 ; CHECK-NEXT: addl $68, %esp
126 ; CHECK-NEXT: retl
127 ;
128 ; CHECK-WIDE-LABEL: cvt_v2f32_v2i8:
129 ; CHECK-WIDE: ## %bb.0:
130 ; CHECK-WIDE-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
131 ; CHECK-WIDE-NEXT: vcvttss2si %xmm1, %eax
132 ; CHECK-WIDE-NEXT: vcvttss2si %xmm0, %ecx
133 ; CHECK-WIDE-NEXT: vmovd %ecx, %xmm0
134 ; CHECK-WIDE-NEXT: vpinsrb $1, %eax, %xmm0, %xmm0
135 ; CHECK-WIDE-NEXT: retl
136 %res = fptosi <2 x float> %src to <2 x i8>
137 ret <2 x i8> %res
138 }
139
140 define <2 x i16> @cvt_v2f32_v2i16(<2 x float> %src) {
141 ; CHECK-LABEL: cvt_v2f32_v2i16:
142 ; CHECK: ## %bb.0:
143 ; CHECK-NEXT: subl $68, %esp
144 ; CHECK-NEXT: .cfi_def_cfa_offset 72
145 ; CHECK-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp)
146 ; CHECK-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp)
147 ; CHECK-NEXT: flds {{[0-9]+}}(%esp)
148 ; CHECK-NEXT: fisttpll {{[0-9]+}}(%esp)
149 ; CHECK-NEXT: flds {{[0-9]+}}(%esp)
150 ; CHECK-NEXT: fisttpll (%esp)
151 ; CHECK-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
152 ; CHECK-NEXT: vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm0
153 ; CHECK-NEXT: vpinsrd $2, (%esp), %xmm0, %xmm0
154 ; CHECK-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0
155 ; CHECK-NEXT: addl $68, %esp
156 ; CHECK-NEXT: retl
157 ;
158 ; CHECK-WIDE-LABEL: cvt_v2f32_v2i16:
159 ; CHECK-WIDE: ## %bb.0:
160 ; CHECK-WIDE-NEXT: ## kill: def $xmm0 killed $xmm0 def $ymm0
161 ; CHECK-WIDE-NEXT: vcvttps2dq %ymm0, %ymm0
162 ; CHECK-WIDE-NEXT: vextractf128 $1, %ymm0, %xmm1
163 ; CHECK-WIDE-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
164 ; CHECK-WIDE-NEXT: vzeroupper
165 ; CHECK-WIDE-NEXT: retl
166 %res = fptosi <2 x float> %src to <2 x i16>
167 ret <2 x i16> %res
168 }
169
170 define <2 x i32> @cvt_v2f32_v2i32(<2 x float> %src) {
171 ; CHECK-LABEL: cvt_v2f32_v2i32:
172 ; CHECK: ## %bb.0:
173 ; CHECK-NEXT: vcvttps2dq %xmm0, %xmm0
174 ; CHECK-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
175 ; CHECK-NEXT: retl
176 ;
177 ; CHECK-WIDE-LABEL: cvt_v2f32_v2i32:
178 ; CHECK-WIDE: ## %bb.0:
179 ; CHECK-WIDE-NEXT: vcvttps2dq %xmm0, %xmm0
180 ; CHECK-WIDE-NEXT: retl
181 %res = fptosi <2 x float> %src to <2 x i32>
182 ret <2 x i32> %res
183 }
184
185 define <2 x i8> @cvt_v2f32_v2u8(<2 x float> %src) {
186 ; CHECK-LABEL: cvt_v2f32_v2u8:
187 ; CHECK: ## %bb.0:
188 ; CHECK-NEXT: subl $68, %esp
189 ; CHECK-NEXT: .cfi_def_cfa_offset 72
190 ; CHECK-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
191 ; CHECK-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
192 ; CHECK-NEXT: vcmpltss %xmm2, %xmm1, %xmm3
193 ; CHECK-NEXT: vsubss %xmm2, %xmm1, %xmm4
194 ; CHECK-NEXT: vblendvps %xmm3, %xmm1, %xmm4, %xmm3
195 ; CHECK-NEXT: vmovss %xmm3, {{[0-9]+}}(%esp)
196 ; CHECK-NEXT: vcmpltss %xmm2, %xmm0, %xmm3
197 ; CHECK-NEXT: vsubss %xmm2, %xmm0, %xmm4
198 ; CHECK-NEXT: vblendvps %xmm3, %xmm0, %xmm4, %xmm3
199 ; CHECK-NEXT: vmovss %xmm3, {{[0-9]+}}(%esp)
200 ; CHECK-NEXT: flds {{[0-9]+}}(%esp)
201 ; CHECK-NEXT: fisttpll (%esp)
202 ; CHECK-NEXT: flds {{[0-9]+}}(%esp)
203 ; CHECK-NEXT: fisttpll {{[0-9]+}}(%esp)
204 ; CHECK-NEXT: xorl %eax, %eax
205 ; CHECK-NEXT: vucomiss %xmm2, %xmm1
206 ; CHECK-NEXT: setae %al
207 ; CHECK-NEXT: shll $31, %eax
208 ; CHECK-NEXT: xorl {{[0-9]+}}(%esp), %eax
209 ; CHECK-NEXT: xorl %ecx, %ecx
210 ; CHECK-NEXT: vucomiss %xmm2, %xmm0
211 ; CHECK-NEXT: setae %cl
212 ; CHECK-NEXT: shll $31, %ecx
213 ; CHECK-NEXT: xorl {{[0-9]+}}(%esp), %ecx
214 ; CHECK-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
215 ; CHECK-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0
216 ; CHECK-NEXT: vpinsrd $2, (%esp), %xmm0, %xmm0
217 ; CHECK-NEXT: vpinsrd $3, %eax, %xmm0, %xmm0
218 ; CHECK-NEXT: addl $68, %esp
219 ; CHECK-NEXT: retl
220 ;
221 ; CHECK-WIDE-LABEL: cvt_v2f32_v2u8:
222 ; CHECK-WIDE: ## %bb.0:
223 ; CHECK-WIDE-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
224 ; CHECK-WIDE-NEXT: vcvttss2si %xmm1, %eax
225 ; CHECK-WIDE-NEXT: vcvttss2si %xmm0, %ecx
226 ; CHECK-WIDE-NEXT: vmovd %ecx, %xmm0
227 ; CHECK-WIDE-NEXT: vpinsrb $1, %eax, %xmm0, %xmm0
228 ; CHECK-WIDE-NEXT: retl
229 %res = fptoui <2 x float> %src to <2 x i8>
230 ret <2 x i8> %res
231 }
232
233 define <2 x i16> @cvt_v2f32_v2u16(<2 x float> %src) {
234 ; CHECK-LABEL: cvt_v2f32_v2u16:
235 ; CHECK: ## %bb.0:
236 ; CHECK-NEXT: subl $68, %esp
237 ; CHECK-NEXT: .cfi_def_cfa_offset 72
238 ; CHECK-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
239 ; CHECK-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
240 ; CHECK-NEXT: vcmpltss %xmm2, %xmm1, %xmm3
241 ; CHECK-NEXT: vsubss %xmm2, %xmm1, %xmm4
242 ; CHECK-NEXT: vblendvps %xmm3, %xmm1, %xmm4, %xmm3
243 ; CHECK-NEXT: vmovss %xmm3, {{[0-9]+}}(%esp)
244 ; CHECK-NEXT: vcmpltss %xmm2, %xmm0, %xmm3
245 ; CHECK-NEXT: vsubss %xmm2, %xmm0, %xmm4
246 ; CHECK-NEXT: vblendvps %xmm3, %xmm0, %xmm4, %xmm3
247 ; CHECK-NEXT: vmovss %xmm3, {{[0-9]+}}(%esp)
248 ; CHECK-NEXT: flds {{[0-9]+}}(%esp)
249 ; CHECK-NEXT: fisttpll (%esp)
250 ; CHECK-NEXT: flds {{[0-9]+}}(%esp)
251 ; CHECK-NEXT: fisttpll {{[0-9]+}}(%esp)
252 ; CHECK-NEXT: xorl %eax, %eax
253 ; CHECK-NEXT: vucomiss %xmm2, %xmm1
254 ; CHECK-NEXT: setae %al
255 ; CHECK-NEXT: shll $31, %eax
256 ; CHECK-NEXT: xorl {{[0-9]+}}(%esp), %eax
257 ; CHECK-NEXT: xorl %ecx, %ecx
258 ; CHECK-NEXT: vucomiss %xmm2, %xmm0
259 ; CHECK-NEXT: setae %cl
260 ; CHECK-NEXT: shll $31, %ecx
261 ; CHECK-NEXT: xorl {{[0-9]+}}(%esp), %ecx
262 ; CHECK-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
263 ; CHECK-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0
264 ; CHECK-NEXT: vpinsrd $2, (%esp), %xmm0, %xmm0
265 ; CHECK-NEXT: vpinsrd $3, %eax, %xmm0, %xmm0
266 ; CHECK-NEXT: addl $68, %esp
267 ; CHECK-NEXT: retl
268 ;
269 ; CHECK-WIDE-LABEL: cvt_v2f32_v2u16:
270 ; CHECK-WIDE: ## %bb.0:
271 ; CHECK-WIDE-NEXT: ## kill: def $xmm0 killed $xmm0 def $ymm0
272 ; CHECK-WIDE-NEXT: vcvttps2dq %ymm0, %ymm0
273 ; CHECK-WIDE-NEXT: vextractf128 $1, %ymm0, %xmm1
274 ; CHECK-WIDE-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
275 ; CHECK-WIDE-NEXT: vzeroupper
276 ; CHECK-WIDE-NEXT: retl
277 %res = fptoui <2 x float> %src to <2 x i16>
278 ret <2 x i16> %res
279 }
280
281 define <2 x i32> @cvt_v2f32_v2u32(<2 x float> %src) {
282 ; CHECK-LABEL: cvt_v2f32_v2u32:
283 ; CHECK: ## %bb.0:
284 ; CHECK-NEXT: subl $68, %esp
285 ; CHECK-NEXT: .cfi_def_cfa_offset 72
286 ; CHECK-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
287 ; CHECK-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
288 ; CHECK-NEXT: vcmpltss %xmm2, %xmm1, %xmm3
289 ; CHECK-NEXT: vsubss %xmm2, %xmm1, %xmm4
290 ; CHECK-NEXT: vblendvps %xmm3, %xmm1, %xmm4, %xmm3
291 ; CHECK-NEXT: vmovss %xmm3, {{[0-9]+}}(%esp)
292 ; CHECK-NEXT: vcmpltss %xmm2, %xmm0, %xmm3
293 ; CHECK-NEXT: vsubss %xmm2, %xmm0, %xmm4
294 ; CHECK-NEXT: vblendvps %xmm3, %xmm0, %xmm4, %xmm3
295 ; CHECK-NEXT: vmovss %xmm3, {{[0-9]+}}(%esp)
296 ; CHECK-NEXT: flds {{[0-9]+}}(%esp)
297 ; CHECK-NEXT: fisttpll (%esp)
298 ; CHECK-NEXT: flds {{[0-9]+}}(%esp)
299 ; CHECK-NEXT: fisttpll {{[0-9]+}}(%esp)
300 ; CHECK-NEXT: xorl %eax, %eax
301 ; CHECK-NEXT: vucomiss %xmm2, %xmm1
302 ; CHECK-NEXT: setae %al
303 ; CHECK-NEXT: shll $31, %eax
304 ; CHECK-NEXT: xorl {{[0-9]+}}(%esp), %eax
305 ; CHECK-NEXT: xorl %ecx, %ecx
306 ; CHECK-NEXT: vucomiss %xmm2, %xmm0
307 ; CHECK-NEXT: setae %cl
308 ; CHECK-NEXT: shll $31, %ecx
309 ; CHECK-NEXT: xorl {{[0-9]+}}(%esp), %ecx
310 ; CHECK-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
311 ; CHECK-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0
312 ; CHECK-NEXT: vpinsrd $2, (%esp), %xmm0, %xmm0
313 ; CHECK-NEXT: vpinsrd $3, %eax, %xmm0, %xmm0
314 ; CHECK-NEXT: addl $68, %esp
315 ; CHECK-NEXT: retl
316 ;
317 ; CHECK-WIDE-LABEL: cvt_v2f32_v2u32:
318 ; CHECK-WIDE: ## %bb.0:
319 ; CHECK-WIDE-NEXT: subl $68, %esp
320 ; CHECK-WIDE-NEXT: .cfi_def_cfa_offset 72
321 ; CHECK-WIDE-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp)
322 ; CHECK-WIDE-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp)
323 ; CHECK-WIDE-NEXT: vextractps $2, %xmm0, {{[0-9]+}}(%esp)
324 ; CHECK-WIDE-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp)
325 ; CHECK-WIDE-NEXT: flds {{[0-9]+}}(%esp)
326 ; CHECK-WIDE-NEXT: fisttpll {{[0-9]+}}(%esp)
327 ; CHECK-WIDE-NEXT: flds {{[0-9]+}}(%esp)
328 ; CHECK-WIDE-NEXT: fisttpll {{[0-9]+}}(%esp)
329 ; CHECK-WIDE-NEXT: flds {{[0-9]+}}(%esp)
330 ; CHECK-WIDE-NEXT: fisttpll {{[0-9]+}}(%esp)
331 ; CHECK-WIDE-NEXT: flds {{[0-9]+}}(%esp)
332 ; CHECK-WIDE-NEXT: fisttpll (%esp)
333 ; CHECK-WIDE-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
334 ; CHECK-WIDE-NEXT: vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm0
335 ; CHECK-WIDE-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm0
336 ; CHECK-WIDE-NEXT: vpinsrd $3, (%esp), %xmm0, %xmm0
337 ; CHECK-WIDE-NEXT: addl $68, %esp
338 ; CHECK-WIDE-NEXT: retl
339 %res = fptoui <2 x float> %src to <2 x i32>
340 ret <2 x i32> %res
341 }