llvm.org GIT mirror llvm / c8f4587
transition to using let instead of set git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7564 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 17 years ago
3 changed file(s) with 85 addition(s) and 100 deletion(s). Raw diff Collapse all Expand all
44 //
55 //===----------------------------------------------------------------------===//
66
7 // Get the target independent interfaces which we are implementing...
7 // Get the target-independent interfaces which we are implementing...
88 //
99 include "../Target.td"
1010
2121 include "X86InstrInfo.td"
2222
2323 def X86InstrInfo : InstrInfo {
24 set PHIInst = PHI;
25 set NOOPInst = NOOP;
24 let PHIInst = PHI;
25 let NOOPInst = NOOP;
2626
2727 // Define how we want to layout our TargetSpecific information field... This
2828 // should be kept up-to-date with the fields in the X86InstrInfo.h file.
29 set TSFlagsFields = ["FormBits", "isVoid", "hasOpSizePrefix", "Prefix",
29 let TSFlagsFields = ["FormBits", "hasOpSizePrefix", "Prefix",
3030 "TypeBits", "FPFormBits", "printImplicitUses", "Opcode"];
31 set TSFlagsShifts = [ 0, 5, 6, 7,
31 let TSFlagsShifts = [ 0, 6, 7,
3232 11, 14, 17, 18];
3333 }
3434
3535 def X86 : Target {
3636 // Specify the callee saved registers.
37 set CalleeSavedRegisters = [ESI, EDI, EBX, EBP];
37 let CalleeSavedRegisters = [ESI, EDI, EBX, EBP];
3838
3939 // Yes, pointers are 32-bits in size.
40 set PointerType = i32;
40 let PointerType = i32;
4141
4242 // Information about the instructions...
43 set InstructionSet = X86InstrInfo;
43 let InstructionSet = X86InstrInfo;
4444 }
44 // code emission, and analysis.
55 //
66 //===----------------------------------------------------------------------===//
7
8
97
108 // Format specifies the encoding used by the instruction. This is part of the
119 // ad-hoc solution used to emit machine instruction encodings by our machine
5452
5553
5654 class X86Inst opcod, Format f, ArgType a> : Instruction {
57 set Namespace = "X86";
58
59 set Name = nam;
55 let Namespace = "X86";
56
57 let Name = nam;
6058 bits<8> Opcode = opcod;
6159 Format Form = f;
6260 bits<5> FormBits = Form.Value;
6462 bits<3> TypeBits = Type.Value;
6563
6664 // Attributes specific to X86 instructions...
67 bit isVoid = 0; // Does this inst ignore the return value?
6865 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
6966 bit printImplicitUses = 0; // Should we print implicit uses of this inst?
7067
10097
10198 def PHI : X86Inst<"PHI", 0, Pseudo, NoArg>; // PHI node...
10299
103 set isVoid = 1 in
104 def NOOP : X86Inst<"nop", 0x90, RawFrm, NoArg>; // nop
100 def NOOP : X86Inst<"nop", 0x90, RawFrm, NoArg>; // nop
105101
106102 def ADJCALLSTACKDOWN : X86Inst<"ADJCALLSTACKDOWN", 0, Pseudo, NoArg>;
107103 def ADJCALLSTACKUP : X86Inst<"ADJCALLSTACKUP", 0, Pseudo, NoArg>;
112108 //
113109
114110 // Return instruction...
115 set isTerminator = 1, isVoid = 1, isReturn = 1 in
111 let isTerminator = 1, isReturn = 1 in
116112 def RET : X86Inst<"ret", 0xC3, RawFrm, NoArg>;
117113
118114 // All branches are RawFrm, Void, Branch, and Terminators
119 set isVoid = 1, isBranch = 1, isTerminator = 1 in
115 let isBranch = 1, isTerminator = 1 in
120116 class IBr opcode> : X86Inst;
121117
122118 def JMP : IBr<"jmp", 0xE9>;
135131 //===----------------------------------------------------------------------===//
136132 // Call Instructions...
137133 //
138 set isCall = 1, isVoid = 1 in
134 let isCall = 1 in
139135 // All calls clobber the non-callee saved registers...
140 set Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6] in {
136 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6] in {
141137 def CALLpcrel32 : X86Inst<"call", 0xE8, RawFrm, NoArg>;
142138 def CALLr32 : X86Inst<"call", 0xFF, MRMS2r, Arg32>;
143139 def CALLm32 : X86Inst<"call", 0xFF, MRMS2m, Arg32>;
149145 //
150146 def LEAVE : X86Inst<"leave", 0xC9, RawFrm, NoArg>, Imp<[EBP], [EBP]>;
151147
152 set isTwoAddress = 1 in // R32 = bswap R32
148 let isTwoAddress = 1 in // R32 = bswap R32
153149 def BSWAPr32 : X86Inst<"bswap", 0xC8, AddRegFrm, Arg32>, TB;
154150
155151 def XCHGrr8 : X86Inst<"xchg", 0x86, MRMDestReg, Arg8>; // xchg R8, R8
176172 def MOVmr16 : X86Inst<"mov", 0x8B, MRMSrcMem , Arg16>, OpSize; // R16 = [mem]
177173 def MOVmr32 : X86Inst<"mov", 0x8B, MRMSrcMem , Arg32>; // R32 = [mem]
178174
179 set isVoid = 1 in {
180 def MOVrm8 : X86Inst<"mov", 0x88, MRMDestMem, Arg8>; // R8 = [mem]
181 def MOVrm16 : X86Inst<"mov", 0x89, MRMDestMem, Arg16>, OpSize; // R16 = [mem]
182 def MOVrm32 : X86Inst<"mov", 0x89, MRMDestMem, Arg32>; // R32 = [mem]
183 }
175 def MOVrm8 : X86Inst<"mov", 0x88, MRMDestMem, Arg8>; // [mem] = R8
176 def MOVrm16 : X86Inst<"mov", 0x89, MRMDestMem, Arg16>, OpSize; // [mem] = R16
177 def MOVrm32 : X86Inst<"mov", 0x89, MRMDestMem, Arg32>; // [mem] = R32
184178
185179 //===----------------------------------------------------------------------===//
186180 // Fixed-Register Multiplication and Division Instructions...
187181 //
188 set isVoid = 1 in {
189 // Extra precision multiplication
190 def MULr8 : X86Inst<"mul", 0xF6, MRMS4r, Arg8 >, Imp<[AL],[AX]>; // AL,AH = AL*R8
191 def MULr16 : X86Inst<"mul", 0xF7, MRMS4r, Arg16>, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16
192 def MULr32 : X86Inst<"mul", 0xF7, MRMS4r, Arg32>, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32
193
194 // unsigned division/remainder
195 def DIVr8 : X86Inst<"div", 0xF6, MRMS6r, Arg8 >, Imp<[AX],[AX]>; // AX/r8 = AL,AH
196 def DIVr16 : X86Inst<"div", 0xF7, MRMS6r, Arg16>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX
197 def DIVr32 : X86Inst<"div", 0xF7, MRMS6r, Arg32>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX
198
199 // signed division/remainder
200 def IDIVr8 : X86Inst<"idiv",0xF6, MRMS7r, Arg8 >, Imp<[AX],[AX]>; // AX/r8 = AL,AH
201 def IDIVr16: X86Inst<"idiv",0xF7, MRMS7r, Arg16>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX
202 def IDIVr32: X86Inst<"idiv",0xF7, MRMS7r, Arg32>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX
203
204 // Sign-extenders for division
205 def CBW : X86Inst<"cbw", 0x98, RawFrm, Arg8 >, Imp<[AL],[AH]>; // AX = signext(AL)
206 def CWD : X86Inst<"cwd", 0x99, RawFrm, Arg8 >, Imp<[AX],[DX]>; // DX:AX = signext(AX)
207 def CDQ : X86Inst<"cdq", 0x99, RawFrm, Arg8 >, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX)
208 }
182
183 // Extra precision multiplication
184 def MULr8 : X86Inst<"mul", 0xF6, MRMS4r, Arg8 >, Imp<[AL],[AX]>; // AL,AH = AL*R8
185 def MULr16 : X86Inst<"mul", 0xF7, MRMS4r, Arg16>, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16
186 def MULr32 : X86Inst<"mul", 0xF7, MRMS4r, Arg32>, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32
187
188 // unsigned division/remainder
189 def DIVr8 : X86Inst<"div", 0xF6, MRMS6r, Arg8 >, Imp<[AX],[AX]>; // AX/r8 = AL,AH
190 def DIVr16 : X86Inst<"div", 0xF7, MRMS6r, Arg16>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX
191 def DIVr32 : X86Inst<"div", 0xF7, MRMS6r, Arg32>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX
192
193 // signed division/remainder
194 def IDIVr8 : X86Inst<"idiv",0xF6, MRMS7r, Arg8 >, Imp<[AX],[AX]>; // AX/r8 = AL,AH
195 def IDIVr16: X86Inst<"idiv",0xF7, MRMS7r, Arg16>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX
196 def IDIVr32: X86Inst<"idiv",0xF7, MRMS7r, Arg32>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX
197
198 // Sign-extenders for division
199 def CBW : X86Inst<"cbw", 0x98, RawFrm, Arg8 >, Imp<[AL],[AH]>; // AX = signext(AL)
200 def CWD : X86Inst<"cwd", 0x99, RawFrm, Arg8 >, Imp<[AX],[DX]>; // DX:AX = signext(AX)
201 def CDQ : X86Inst<"cdq", 0x99, RawFrm, Arg8 >, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX)
209202
210203
211204 //===----------------------------------------------------------------------===//
212205 // Two address Instructions...
213206 //
214 set isTwoAddress = 1 in { // Define some helper classes to make defs shorter.
207 let isTwoAddress = 1 in { // Define some helper classes to make defs shorter.
215208 class I2A8 o, Format F> : X86Inst;
216209 class I2A16 o, Format F> : X86Inst;
217210 class I2A32 o, Format F> : X86Inst;
236229
237230 def SBBrr32 : I2A32<"sbb", 0x19, MRMDestReg>; // R32 -= R32+Carry
238231
239 def IMULr16 : I2A16<"imul", 0xAF, MRMSrcReg>, TB, OpSize; // R16 *= R16
240 def IMULr32 : I2A32<"imul", 0xAF, MRMSrcReg>, TB; // R32 *= R32
232 def IMULr16 : I2A16<"imul", 0xAF, MRMSrcReg>, TB, OpSize; // R16 *= R16
233 def IMULr32 : I2A32<"imul", 0xAF, MRMSrcReg>, TB; // R32 *= R32
241234
242235 // Logical operators...
243236 def ANDrr8 : I2A8 <"and", 0x20, MRMDestReg>; // R8 &= R8
315308 def CMOVNErr32: I2A32<"cmovne",0x45, MRMSrcReg>, TB; // if !=, R32 = R32
316309
317310 // Integer comparisons
318 set isVoid = 1 in {
319 def CMPrr8 : X86Inst<"cmp", 0x38, MRMDestReg, Arg8 >; // compare R8, R8
320 def CMPrr16 : X86Inst<"cmp", 0x39, MRMDestReg, Arg16>, OpSize; // compare R16, R16
321 def CMPrr32 : X86Inst<"cmp", 0x39, MRMDestReg, Arg32>; // compare R32, R32
322 def CMPri8 : X86Inst<"cmp", 0x80, MRMS7r , Arg8 >; // compare R8, imm8
323 def CMPri16 : X86Inst<"cmp", 0x81, MRMS7r , Arg16>, OpSize; // compare R16, imm16
324 def CMPri32 : X86Inst<"cmp", 0x81, MRMS7r , Arg32>; // compare R32, imm32
325 }
311 def CMPrr8 : X86Inst<"cmp", 0x38, MRMDestReg, Arg8 >; // compare R8, R8
312 def CMPrr16 : X86Inst<"cmp", 0x39, MRMDestReg, Arg16>, OpSize; // compare R16, R16
313 def CMPrr32 : X86Inst<"cmp", 0x39, MRMDestReg, Arg32>; // compare R32, R32
314 def CMPri8 : X86Inst<"cmp", 0x80, MRMS7r , Arg8 >; // compare R8, imm8
315 def CMPri16 : X86Inst<"cmp", 0x81, MRMS7r , Arg16>, OpSize; // compare R16, imm16
316 def CMPri32 : X86Inst<"cmp", 0x81, MRMS7r , Arg32>; // compare R32, imm32
326317
327318 // Sign/Zero extenders
328319 def MOVSXr16r8 : X86Inst<"movsx", 0xBE, MRMSrcReg, Arg8>, TB, OpSize; // R16 = signext(R8)
341332
342333 // Floating point pseudo instructions...
343334 class FPInst o, Format F, ArgType t, FPFormat fp>
344 : X86Inst { set FPForm = fp; set FPFormBits = FPForm.Value; }
335 : X86Inst { let FPForm = fp; let FPFormBits = FPForm.Value; }
345336
346337 def FpMOV : FPInst<"FMOV", 0, Pseudo, ArgF80, SpecialFP>; // f1 = fmov f2
347338 def FpADD : FPInst<"FADD", 0, Pseudo, ArgF80, TwoArgFP>; // f1 = fadd f2, f3
349340 def FpMUL : FPInst<"FMUL", 0, Pseudo, ArgF80, TwoArgFP>; // f1 = fmul f2, f3
350341 def FpDIV : FPInst<"FDIV", 0, Pseudo, ArgF80, TwoArgFP>; // f1 = fdiv f2, f3
351342
352 set isVoid = 1 in
353 def FpUCOM : FPInst<"FUCOM", 0, Pseudo, ArgF80, TwoArgFP>; // FPSW = fucom f1, f2
343 def FpUCOM : FPInst<"FUCOM", 0, Pseudo, ArgF80, TwoArgFP>; // FPSW = fucom f1, f2
354344
355345 def FpGETRESULT : FPInst<"FGETRESULT",0, Pseudo, ArgF80, SpecialFP>; // FPR = ST(0)
356346
357 set isVoid = 1 in
358 def FpSETRESULT : FPInst<"FSETRESULT",0, Pseudo, ArgF80, SpecialFP>; // ST(0) = FPR
347 def FpSETRESULT : FPInst<"FSETRESULT",0, Pseudo, ArgF80, SpecialFP>; // ST(0) = FPR
359348
360349 // Floating point loads & stores...
361350 def FLDrr : FPInst<"fld" , 0xC0, AddRegFrm, ArgF80, NotFP>, D9; // push(ST(i))
362 def FLDr32 : FPInst<"fld" , 0xD9, MRMS0m , ArgF32, ZeroArgFP>; // load float
363 def FLDr64 : FPInst<"fld" , 0xDD, MRMS0m , ArgF64, ZeroArgFP>; // load double
364 def FLDr80 : FPInst<"fld" , 0xDB, MRMS5m , ArgF80, ZeroArgFP>; // load extended
365 def FILDr16 : FPInst<"fild" , 0xDF, MRMS0m , Arg16 , ZeroArgFP>; // load signed short
366 def FILDr32 : FPInst<"fild" , 0xDB, MRMS0m , Arg32 , ZeroArgFP>; // load signed int
367 def FILDr64 : FPInst<"fild" , 0xDF, MRMS5m , Arg64 , ZeroArgFP>; // load signed long
368
369 set isVoid = 1 in {
370 def FSTr32 : FPInst<"fst" , 0xD9, MRMS2m , ArgF32, OneArgFP>; // store float
371 def FSTr64 : FPInst<"fst" , 0xDD, MRMS2m , ArgF64, OneArgFP>; // store double
372 def FSTPr32 : FPInst<"fstp", 0xD9, MRMS3m , ArgF32, OneArgFP>; // store float, pop
373 def FSTPr64 : FPInst<"fstp", 0xDD, MRMS3m , ArgF64, OneArgFP>; // store double, pop
374 def FSTPr80 : FPInst<"fstp", 0xDB, MRMS7m , ArgF80, OneArgFP>; // store extended, pop
375 def FSTrr : FPInst<"fst" , 0xD0, AddRegFrm, ArgF80, NotFP >, DD; // ST(i) = ST(0)
376 def FSTPrr : FPInst<"fstp", 0xD8, AddRegFrm, ArgF80, NotFP >, DD; // ST(i) = ST(0), pop
377
378 def FISTr16 : FPInst<"fist", 0xDF, MRMS2m, Arg16 , OneArgFP>; // store signed short
379 def FISTr32 : FPInst<"fist", 0xDB, MRMS2m, Arg32 , OneArgFP>; // store signed int
380 def FISTPr16 : FPInst<"fistp", 0xDF, MRMS3m, Arg16 , NotFP >; // store signed short, pop
381 def FISTPr32 : FPInst<"fistp", 0xDB, MRMS3m, Arg32 , NotFP >; // store signed int, pop
382 def FISTPr64 : FPInst<"fistpll", 0xDF, MRMS7m, Arg64 , OneArgFP>; // store signed long, pop
383
384 def FXCH : FPInst<"fxch", 0xC8, AddRegFrm, ArgF80, NotFP>, D9; // fxch ST(i), ST(0)
385 }
351 def FLDr32 : FPInst<"fld" , 0xD9, MRMS0m , ArgF32, ZeroArgFP>; // load float
352 def FLDr64 : FPInst<"fld" , 0xDD, MRMS0m , ArgF64, ZeroArgFP>; // load double
353 def FLDr80 : FPInst<"fld" , 0xDB, MRMS5m , ArgF80, ZeroArgFP>; // load extended
354 def FILDr16 : FPInst<"fild" , 0xDF, MRMS0m , Arg16 , ZeroArgFP>; // load signed short
355 def FILDr32 : FPInst<"fild" , 0xDB, MRMS0m , Arg32 , ZeroArgFP>; // load signed int
356 def FILDr64 : FPInst<"fild" , 0xDF, MRMS5m , Arg64 , ZeroArgFP>; // load signed long
357
358 def FSTr32 : FPInst<"fst" , 0xD9, MRMS2m , ArgF32, OneArgFP>; // store float
359 def FSTr64 : FPInst<"fst" , 0xDD, MRMS2m , ArgF64, OneArgFP>; // store double
360 def FSTPr32 : FPInst<"fstp", 0xD9, MRMS3m , ArgF32, OneArgFP>; // store float, pop
361 def FSTPr64 : FPInst<"fstp", 0xDD, MRMS3m , ArgF64, OneArgFP>; // store double, pop
362 def FSTPr80 : FPInst<"fstp", 0xDB, MRMS7m , ArgF80, OneArgFP>; // store extended, pop
363 def FSTrr : FPInst<"fst" , 0xD0, AddRegFrm, ArgF80, NotFP >, DD; // ST(i) = ST(0)
364 def FSTPrr : FPInst<"fstp", 0xD8, AddRegFrm, ArgF80, NotFP >, DD; // ST(i) = ST(0), pop
365
366 def FISTr16 : FPInst<"fist", 0xDF, MRMS2m, Arg16 , OneArgFP>; // store signed short
367 def FISTr32 : FPInst<"fist", 0xDB, MRMS2m, Arg32 , OneArgFP>; // store signed int
368 def FISTPr16 : FPInst<"fistp", 0xDF, MRMS3m, Arg16 , NotFP >; // store signed short, pop
369 def FISTPr32 : FPInst<"fistp", 0xDB, MRMS3m, Arg32 , NotFP >; // store signed int, pop
370 def FISTPr64 : FPInst<"fistpll", 0xDF, MRMS7m, Arg64 , OneArgFP>; // store signed long, pop
371
372 def FXCH : FPInst<"fxch", 0xC8, AddRegFrm, ArgF80, NotFP>, D9; // fxch ST(i), ST(0)
386373
387374 // Floating point constant loads...
388375 def FLD0 : FPInst<"fldz", 0xEE, RawFrm, ArgF80, ZeroArgFP>, D9;
429416 def FDIVRPrST0 : FPrST0PInst<"fdivrp", 0xF0>; // ST(i) = ST(0) / ST(i), pop
430417
431418 // Floating point compares
432 set isVoid = 1 in {
433 def FUCOMr : X86Inst<"fucom" , 0xE0, AddRegFrm, ArgF80>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i)
434 def FUCOMPr : X86Inst<"fucomp" , 0xE8, AddRegFrm, ArgF80>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i), pop
435 def FUCOMPPr : X86Inst<"fucompp", 0xE9, RawFrm , ArgF80>, DA, Imp<[ST0],[]>; // compare ST(0) with ST(1), pop, pop
436
437 // Floating point flag ops
438 def FNSTSWr8 : X86Inst<"fnstsw" , 0xE0, RawFrm , ArgF80>, DF, Imp<[],[AX]>; // AX = fp flags
439 def FNSTCWm16 : X86Inst<"fnstcw" , 0xD9, MRMS7m , Arg16 >; // [mem16] = X87 control world
440 def FLDCWm16 : X86Inst<"fldcw" , 0xD9, MRMS5m , Arg16 >; // X87 control world = [mem16]
441 }
419 def FUCOMr : X86Inst<"fucom" , 0xE0, AddRegFrm, ArgF80>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i)
420 def FUCOMPr : X86Inst<"fucomp" , 0xE8, AddRegFrm, ArgF80>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i), pop
421 def FUCOMPPr : X86Inst<"fucompp", 0xE9, RawFrm , ArgF80>, DA, Imp<[ST0],[]>; // compare ST(0) with ST(1), pop, pop
422
423 // Floating point flag ops
424 def FNSTSWr8 : X86Inst<"fnstsw" , 0xE0, RawFrm , ArgF80>, DF, Imp<[],[AX]>; // AX = fp flags
425 def FNSTCWm16 : X86Inst<"fnstcw" , 0xD9, MRMS7m , Arg16 >; // [mem16] = X87 control world
426 def FLDCWm16 : X86Inst<"fldcw" , 0xD9, MRMS5m , Arg16 >; // X87 control world = [mem16]
88 //===----------------------------------------------------------------------===//
99 // Register definitions...
1010 //
11 set Namespace = "X86" in {
11 let Namespace = "X86" in {
1212 // 32-bit registers
1313 def EAX : Register; def ECX : Register;
1414 def EDX : Register; def EBX : Register;
7070 //
7171 def r8 : RegisterClass;
7272 def r16 : RegisterClass {
73 set Methods = [{
73 let Methods = [{
7474 iterator allocation_order_end(MachineFunction &MF) const {
7575 if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
7676 return end()-2; // If so, don't allocate SP or BP
8181 }
8282
8383 def r32 : RegisterClass {
84 set Methods = [{
84 let Methods = [{
8585 iterator allocation_order_end(MachineFunction &MF) const {
8686 if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
8787 return end()-2; // If so, don't allocate ESP or EBP