llvm.org GIT mirror llvm / c8893fc
* Order includes according to style guide * Convert tabs to spaces * Make code fit within 80 columns git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9416 91177308-0d34-0410-b5e6-96231b3b80d8 Misha Brukman 16 years ago
2 changed file(s) with 212 addition(s) and 210 deletion(s). Raw diff Collapse all Expand all
1111 //===----------------------------------------------------------------------===//
1212
1313 #include "X86.h"
14 #include "X86InstrBuilder.h"
1415 #include "X86InstrInfo.h"
15 #include "X86InstrBuilder.h"
16 #include "llvm/Constants.h"
17 #include "llvm/DerivedTypes.h"
1618 #include "llvm/Function.h"
1719 #include "llvm/Instructions.h"
18 #include "llvm/DerivedTypes.h"
19 #include "llvm/Constants.h"
20 #include "llvm/Intrinsics.h"
2021 #include "llvm/Pass.h"
21 #include "llvm/Intrinsics.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
2224 #include "llvm/CodeGen/MachineFunction.h"
2325 #include "llvm/CodeGen/MachineInstrBuilder.h"
2426 #include "llvm/CodeGen/SSARegMap.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/Target/MRegisterInfo.h"
2728 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/Target/MRegisterInfo.h"
2929 #include "llvm/Support/InstVisitor.h"
3030
3131 /// BMI - A special BuildMI variant that takes an iterator to insert the
135135 ValueRecord(Value *V) : Val(V), Reg(0), Ty(V->getType()) {}
136136 };
137137 void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
138 const std::vector &Args);
138 const std::vector &Args);
139139 void visitCallInst(CallInst &I);
140140 void visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &I);
141141
145145 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
146146 void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
147147 unsigned DestReg, const Type *DestTy,
148 unsigned Op0Reg, unsigned Op1Reg);
148 unsigned Op0Reg, unsigned Op1Reg);
149149 void doMultiplyConst(MachineBasicBlock *MBB,
150150 MachineBasicBlock::iterator &MBBI,
151151 unsigned DestReg, const Type *DestTy,
243243 const X86RegisterInfo *MRI =
244244 static_cast(TM.getRegisterInfo());
245245 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
246 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
247 // Create the lower part
248 F->getSSARegMap()->createVirtualRegister(RC);
249 // Create the upper part.
250 return F->getSSARegMap()->createVirtualRegister(RC)-1;
246 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
247 // Create the lower part
248 F->getSSARegMap()->createVirtualRegister(RC);
249 // Create the upper part.
250 return F->getSSARegMap()->createVirtualRegister(RC)-1;
251251 }
252252
253253 // Add the mapping of regnumber => reg class to MachineFunction
463463 case cFP:
464464 unsigned Opcode;
465465 if (I->getType() == Type::FloatTy) {
466 Opcode = X86::FLDr32;
467 FI = MFI->CreateFixedObject(4, ArgOffset);
466 Opcode = X86::FLDr32;
467 FI = MFI->CreateFixedObject(4, ArgOffset);
468468 } else {
469 Opcode = X86::FLDr64;
470 FI = MFI->CreateFixedObject(8, ArgOffset);
471 ArgOffset += 4; // doubles require 4 additional bytes
469 Opcode = X86::FLDr64;
470 FI = MFI->CreateFixedObject(8, ArgOffset);
471 ArgOffset += 4; // doubles require 4 additional bytes
472472 }
473473 addFrameReference(BuildMI(BB, Opcode, 4, Reg), FI);
474474 break;
509509
510510 MachineInstr *LongPhiMI = 0;
511511 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy) {
512 LongPhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg+1);
513 MBB->insert(MBB->begin()+NumPHIs++, LongPhiMI);
512 LongPhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg+1);
513 MBB->insert(MBB->begin()+NumPHIs++, LongPhiMI);
514514 }
515515
516516 // PHIValues - Map of blocks to incoming virtual registers. We use this
557557 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
558558 }
559559
560 PhiMI->addRegOperand(ValReg);
560 PhiMI->addRegOperand(ValReg);
561561 PhiMI->addMachineBasicBlockOperand(PredMBB);
562 if (LongPhiMI) {
563 LongPhiMI->addRegOperand(ValReg+1);
564 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
565 }
562 if (LongPhiMI) {
563 LongPhiMI->addRegOperand(ValReg+1);
564 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
565 }
566566 }
567567 }
568568 }
825825 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(RetReg);
826826 BuildMI(BB, X86::MOVrr32, 1, X86::EDX).addReg(RetReg+1);
827827 // Declare that EAX & EDX are live on exit
828 BuildMI(BB, X86::IMPLICIT_USE, 3).addReg(X86::EAX).addReg(X86::EDX).addReg(X86::ESP);
828 BuildMI(BB, X86::IMPLICIT_USE, 3).addReg(X86::EAX).addReg(X86::EDX)
829 .addReg(X86::ESP);
829830 break;
830831 default:
831832 visitInstruction(I);
876877
877878 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
878879 MachineBasicBlock::iterator MII = BB->end();
879 OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB, MII);
880 OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
880881
881882 const Type *CompTy = SCI->getOperand(0)->getType();
882883 bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
919920 /// it inserts the specified CallMI instruction into the stream.
920921 ///
921922 void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
922 const std::vector &Args) {
923 const std::vector &Args) {
923924
924925 // Count how many bytes are to be pushed on the stack...
925926 unsigned NumBytes = 0;
928929 for (unsigned i = 0, e = Args.size(); i != e; ++i)
929930 switch (getClassB(Args[i].Ty)) {
930931 case cByte: case cShort: case cInt:
931 NumBytes += 4; break;
932 NumBytes += 4; break;
932933 case cLong:
933 NumBytes += 8; break;
934 NumBytes += 8; break;
934935 case cFP:
935 NumBytes += Args[i].Ty == Type::FloatTy ? 4 : 8;
936 break;
936 NumBytes += Args[i].Ty == Type::FloatTy ? 4 : 8;
937 break;
937938 default: assert(0 && "Unknown class!");
938939 }
939940
947948 switch (getClassB(Args[i].Ty)) {
948949 case cByte:
949950 case cShort: {
950 // Promote arg to 32 bits wide into a temporary register...
951 unsigned R = makeAnotherReg(Type::UIntTy);
952 promote32(R, Args[i]);
953 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
954 X86::ESP, ArgOffset).addReg(R);
955 break;
951 // Promote arg to 32 bits wide into a temporary register...
952 unsigned R = makeAnotherReg(Type::UIntTy);
953 promote32(R, Args[i]);
954 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
955 X86::ESP, ArgOffset).addReg(R);
956 break;
956957 }
957958 case cInt:
958 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
959 X86::ESP, ArgOffset).addReg(ArgReg);
960 break;
959 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
960 X86::ESP, ArgOffset).addReg(ArgReg);
961 break;
961962 case cLong:
962 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
963 X86::ESP, ArgOffset).addReg(ArgReg);
964 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
965 X86::ESP, ArgOffset+4).addReg(ArgReg+1);
966 ArgOffset += 4; // 8 byte entry, not 4.
967 break;
968
963 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
964 X86::ESP, ArgOffset).addReg(ArgReg);
965 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
966 X86::ESP, ArgOffset+4).addReg(ArgReg+1);
967 ArgOffset += 4; // 8 byte entry, not 4.
968 break;
969
969970 case cFP:
970 if (Args[i].Ty == Type::FloatTy) {
971 addRegOffset(BuildMI(BB, X86::FSTr32, 5),
972 X86::ESP, ArgOffset).addReg(ArgReg);
973 } else {
974 assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
975 addRegOffset(BuildMI(BB, X86::FSTr64, 5),
976 X86::ESP, ArgOffset).addReg(ArgReg);
977 ArgOffset += 4; // 8 byte entry, not 4.
978 }
979 break;
971 if (Args[i].Ty == Type::FloatTy) {
972 addRegOffset(BuildMI(BB, X86::FSTr32, 5),
973 X86::ESP, ArgOffset).addReg(ArgReg);
974 } else {
975 assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
976 addRegOffset(BuildMI(BB, X86::FSTr64, 5),
977 X86::ESP, ArgOffset).addReg(ArgReg);
978 ArgOffset += 4; // 8 byte entry, not 4.
979 }
980 break;
980981
981982 default: assert(0 && "Unknown class!");
982983 }
10021003 // Integral results are in %eax, or the appropriate portion
10031004 // thereof.
10041005 static const unsigned regRegMove[] = {
1005 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32
1006 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32
10061007 };
10071008 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
10081009 BuildMI(BB, regRegMove[DestClass], 1, Ret.Reg).addReg(AReg[DestClass]);
10441045
10451046 unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
10461047 doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args);
1047 }
1048 }
10481049
10491050
10501051 void ISel::visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &CI) {
13191320
13201321 unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
13211322 BuildMI(BB, X86::ADDrr32, 2, // AH*BL+(AL*BL >> 32)
1322 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
1323 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
13231324
13241325 MBBI = BB->end();
13251326 unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
13261327 BMI(BB, MBBI, X86::IMULrr32, 2, ALBHReg).addReg(Op0Reg).addReg(Op1Reg+1);
13271328
13281329 BuildMI(BB, X86::ADDrr32, 2, // AL*BH + AH*BL + (AL*BL >> 32)
1329 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
1330 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
13301331 }
13311332 }
13321333
13481349 BuildMI(BB, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
13491350 } else { // Floating point remainder...
13501351 MachineInstr *TheCall =
1351 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true);
1352 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true);
13521353 std::vector Args;
13531354 Args.push_back(ValueRecord(I.getOperand(0)));
13541355 Args.push_back(ValueRecord(I.getOperand(1)));
14501451 if (ConstantUInt *CUI = dyn_cast(I.getOperand(1))) {
14511452 unsigned Amount = CUI->getValue();
14521453 if (Amount < 32) {
1453 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
1454 if (isLeftShift) {
1455 BuildMI(BB, Opc[3], 3,
1456 DestReg+1).addReg(SrcReg+1).addReg(SrcReg).addZImm(Amount);
1457 BuildMI(BB, Opc[2], 2, DestReg).addReg(SrcReg).addZImm(Amount);
1458 } else {
1459 BuildMI(BB, Opc[3], 3,
1460 DestReg).addReg(SrcReg ).addReg(SrcReg+1).addZImm(Amount);
1461 BuildMI(BB, Opc[2], 2, DestReg+1).addReg(SrcReg+1).addZImm(Amount);
1462 }
1454 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
1455 if (isLeftShift) {
1456 BuildMI(BB, Opc[3], 3,
1457 DestReg+1).addReg(SrcReg+1).addReg(SrcReg).addZImm(Amount);
1458 BuildMI(BB, Opc[2], 2, DestReg).addReg(SrcReg).addZImm(Amount);
1459 } else {
1460 BuildMI(BB, Opc[3], 3,
1461 DestReg).addReg(SrcReg ).addReg(SrcReg+1).addZImm(Amount);
1462 BuildMI(BB, Opc[2], 2, DestReg+1).addReg(SrcReg+1).addZImm(Amount);
1463 }
14631464 } else { // Shifting more than 32 bits
1464 Amount -= 32;
1465 if (isLeftShift) {
1466 BuildMI(BB, X86::SHLir32, 2,DestReg+1).addReg(SrcReg).addZImm(Amount);
1467 BuildMI(BB, X86::MOVir32, 1,DestReg ).addZImm(0);
1468 } else {
1469 unsigned Opcode = isSigned ? X86::SARir32 : X86::SHRir32;
1470 BuildMI(BB, Opcode, 2, DestReg).addReg(SrcReg+1).addZImm(Amount);
1471 BuildMI(BB, X86::MOVir32, 1, DestReg+1).addZImm(0);
1472 }
1465 Amount -= 32;
1466 if (isLeftShift) {
1467 BuildMI(BB, X86::SHLir32, 2,DestReg+1).addReg(SrcReg).addZImm(Amount);
1468 BuildMI(BB, X86::MOVir32, 1,DestReg ).addZImm(0);
1469 } else {
1470 unsigned Opcode = isSigned ? X86::SARir32 : X86::SHRir32;
1471 BuildMI(BB, Opcode, 2, DestReg).addReg(SrcReg+1).addZImm(Amount);
1472 BuildMI(BB, X86::MOVir32, 1, DestReg+1).addZImm(0);
1473 }
14731474 }
14741475 } else {
14751476 unsigned TmpReg = makeAnotherReg(Type::IntTy);
16961697 BMI(BB, IP, RegRegMove[SrcClass], 1, DestReg).addReg(SrcReg);
16971698 } else if (SrcClass == cFP) {
16981699 if (SrcTy == Type::FloatTy) { // double -> float
1699 assert(DestTy == Type::DoubleTy && "Unknown cFP member!");
1700 BMI(BB, IP, X86::FpMOV, 1, DestReg).addReg(SrcReg);
1700 assert(DestTy == Type::DoubleTy && "Unknown cFP member!");
1701 BMI(BB, IP, X86::FpMOV, 1, DestReg).addReg(SrcReg);
17011702 } else { // float -> double
1702 assert(SrcTy == Type::DoubleTy && DestTy == Type::FloatTy &&
1703 "Unknown cFP member!");
1704 // Truncate from double to float by storing to memory as short, then
1705 // reading it back.
1706 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
1703 assert(SrcTy == Type::DoubleTy && DestTy == Type::FloatTy &&
1704 "Unknown cFP member!");
1705 // Truncate from double to float by storing to memory as short, then
1706 // reading it back.
1707 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
17071708 int FrameIdx = F->getFrameInfo()->CreateStackObject(4, FltAlign);
1708 addFrameReference(BMI(BB, IP, X86::FSTr32, 5), FrameIdx).addReg(SrcReg);
1709 addFrameReference(BMI(BB, IP, X86::FLDr32, 5, DestReg), FrameIdx);
1709 addFrameReference(BMI(BB, IP, X86::FSTr32, 5), FrameIdx).addReg(SrcReg);
1710 addFrameReference(BMI(BB, IP, X86::FLDr32, 5, DestReg), FrameIdx);
17101711 }
17111712 } else if (SrcClass == cLong) {
17121713 BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg);
17361737
17371738 if (isLong) { // Handle upper 32 bits as appropriate...
17381739 if (isUnsigned) // Zero out top bits...
1739 BMI(BB, IP, X86::MOVir32, 1, DestReg+1).addZImm(0);
1740 BMI(BB, IP, X86::MOVir32, 1, DestReg+1).addZImm(0);
17401741 else // Sign extend bottom half...
1741 BMI(BB, IP, X86::SARir32, 2, DestReg+1).addReg(DestReg).addZImm(31);
1742 BMI(BB, IP, X86::SARir32, 2, DestReg+1).addReg(DestReg).addZImm(31);
17421743 }
17431744 return;
17441745 }
18151816 if (SrcClass == cLong) {
18161817 addFrameReference(BMI(BB, IP, X86::MOVrm32, 5), FrameIdx).addReg(SrcReg);
18171818 addFrameReference(BMI(BB, IP, X86::MOVrm32, 5),
1818 FrameIdx, 4).addReg(SrcReg+1);
1819 FrameIdx, 4).addReg(SrcReg+1);
18191820 } else {
18201821 static const unsigned Op1[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
18211822 addFrameReference(BMI(BB, IP, Op1[SrcClass], 5), FrameIdx).addReg(SrcReg);
18471848
18481849 // Restore the memory image of control word to original value
18491850 addFrameReference(BMI(BB, IP, X86::MOVrm8, 5),
1850 CWFrameIdx, 1).addReg(HighPartOfCW);
1851 CWFrameIdx, 1).addReg(HighPartOfCW);
18511852
18521853 // We don't have the facilities for directly storing byte sized data to
18531854 // memory. Promote it to 16 bits. We also must promote unsigned values to
19721973 // which names the field. This index must have ubyte type.
19731974 const ConstantUInt *CUI = cast(idx);
19741975 assert(CUI->getType() == Type::UByteTy
1975 && "Funny-looking structure index in GEP");
1976 && "Funny-looking structure index in GEP");
19761977 // Use the TargetData structure to pick out what the layout of
19771978 // the structure is in memory. Since the structure index must
19781979 // be constant, we can get its value and use it to find the
19811982 unsigned idxValue = CUI->getValue();
19821983 unsigned FieldOff = TD.getStructLayout(StTy)->MemberOffsets[idxValue];
19831984 if (FieldOff) {
1984 NextReg = makeAnotherReg(Type::UIntTy);
1985 // Emit an ADD to add FieldOff to the basePtr.
1986 BMI(MBB, IP, X86::ADDri32, 2,NextReg).addReg(BaseReg).addZImm(FieldOff);
1985 NextReg = makeAnotherReg(Type::UIntTy);
1986 // Emit an ADD to add FieldOff to the basePtr.
1987 BMI(MBB, IP, X86::ADDri32, 2,NextReg).addReg(BaseReg).addZImm(FieldOff);
19871988 }
19881989 // The next type is the member of the structure selected by the
19891990 // index.
20132014 if (ConstantSInt *CSI = dyn_cast(idx)) {
20142015 if (!CSI->isNullValue()) {
20152016 unsigned Offset = elementSize*CSI->getValue();
2016 NextReg = makeAnotherReg(Type::UIntTy);
2017 NextReg = makeAnotherReg(Type::UIntTy);
20172018 BMI(MBB, IP, X86::ADDri32, 2,NextReg).addReg(BaseReg).addZImm(Offset);
20182019 }
20192020 } else if (elementSize == 1) {
20202021 // If the element size is 1, we don't have to multiply, just add
20212022 unsigned idxReg = getReg(idx, MBB, IP);
2022 NextReg = makeAnotherReg(Type::UIntTy);
2023 NextReg = makeAnotherReg(Type::UIntTy);
20232024 BMI(MBB, IP, X86::ADDrr32, 2, NextReg).addReg(BaseReg).addReg(idxReg);
20242025 } else {
20252026 unsigned idxReg = getReg(idx, MBB, IP);
20282029 doMultiplyConst(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSize);
20292030
20302031 // Emit an ADD to add OffsetReg to the basePtr.
2031 NextReg = makeAnotherReg(Type::UIntTy);
2032 NextReg = makeAnotherReg(Type::UIntTy);
20322033 BMI(MBB, IP, X86::ADDrr32, 2,NextReg).addReg(BaseReg).addReg(OffsetReg);
20332034 }
20342035 }
21152116 std::vector Args;
21162117 Args.push_back(ValueRecord(Arg, Type::UIntTy));
21172118 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
2118 1).addExternalSymbol("malloc", true);
2119 1).addExternalSymbol("malloc", true);
21192120 doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args);
21202121 }
21212122
21272128 std::vector Args;
21282129 Args.push_back(ValueRecord(I.getOperand(0)));
21292130 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
2130 1).addExternalSymbol("free", true);
2131 1).addExternalSymbol("free", true);
21312132 doCall(ValueRecord(0, Type::VoidTy), TheCall, Args);
21322133 }
21332134
1111 //===----------------------------------------------------------------------===//
1212
1313 #include "X86.h"
14 #include "X86InstrBuilder.h"
1415 #include "X86InstrInfo.h"
15 #include "X86InstrBuilder.h"
16 #include "llvm/Constants.h"
17 #include "llvm/DerivedTypes.h"
1618 #include "llvm/Function.h"
1719 #include "llvm/Instructions.h"
18 #include "llvm/DerivedTypes.h"
19 #include "llvm/Constants.h"
20 #include "llvm/Intrinsics.h"
2021 #include "llvm/Pass.h"
21 #include "llvm/Intrinsics.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
2224 #include "llvm/CodeGen/MachineFunction.h"
2325 #include "llvm/CodeGen/MachineInstrBuilder.h"
2426 #include "llvm/CodeGen/SSARegMap.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/Target/MRegisterInfo.h"
2728 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/Target/MRegisterInfo.h"
2929 #include "llvm/Support/InstVisitor.h"
3030
3131 /// BMI - A special BuildMI variant that takes an iterator to insert the
135135 ValueRecord(Value *V) : Val(V), Reg(0), Ty(V->getType()) {}
136136 };
137137 void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
138 const std::vector &Args);
138 const std::vector &Args);
139139 void visitCallInst(CallInst &I);
140140 void visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &I);
141141
145145 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
146146 void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
147147 unsigned DestReg, const Type *DestTy,
148 unsigned Op0Reg, unsigned Op1Reg);
148 unsigned Op0Reg, unsigned Op1Reg);
149149 void doMultiplyConst(MachineBasicBlock *MBB,
150150 MachineBasicBlock::iterator &MBBI,
151151 unsigned DestReg, const Type *DestTy,
243243 const X86RegisterInfo *MRI =
244244 static_cast(TM.getRegisterInfo());
245245 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
246 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
247 // Create the lower part
248 F->getSSARegMap()->createVirtualRegister(RC);
249 // Create the upper part.
250 return F->getSSARegMap()->createVirtualRegister(RC)-1;
246 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
247 // Create the lower part
248 F->getSSARegMap()->createVirtualRegister(RC);
249 // Create the upper part.
250 return F->getSSARegMap()->createVirtualRegister(RC)-1;
251251 }
252252
253253 // Add the mapping of regnumber => reg class to MachineFunction
463463 case cFP:
464464 unsigned Opcode;
465465 if (I->getType() == Type::FloatTy) {
466 Opcode = X86::FLDr32;
467 FI = MFI->CreateFixedObject(4, ArgOffset);
466 Opcode = X86::FLDr32;
467 FI = MFI->CreateFixedObject(4, ArgOffset);
468468 } else {
469 Opcode = X86::FLDr64;
470 FI = MFI->CreateFixedObject(8, ArgOffset);
471 ArgOffset += 4; // doubles require 4 additional bytes
469 Opcode = X86::FLDr64;
470 FI = MFI->CreateFixedObject(8, ArgOffset);
471 ArgOffset += 4; // doubles require 4 additional bytes
472472 }
473473 addFrameReference(BuildMI(BB, Opcode, 4, Reg), FI);
474474 break;
509509
510510 MachineInstr *LongPhiMI = 0;
511511 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy) {
512 LongPhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg+1);
513 MBB->insert(MBB->begin()+NumPHIs++, LongPhiMI);
512 LongPhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg+1);
513 MBB->insert(MBB->begin()+NumPHIs++, LongPhiMI);
514514 }
515515
516516 // PHIValues - Map of blocks to incoming virtual registers. We use this
557557 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
558558 }
559559
560 PhiMI->addRegOperand(ValReg);
560 PhiMI->addRegOperand(ValReg);
561561 PhiMI->addMachineBasicBlockOperand(PredMBB);
562 if (LongPhiMI) {
563 LongPhiMI->addRegOperand(ValReg+1);
564 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
565 }
562 if (LongPhiMI) {
563 LongPhiMI->addRegOperand(ValReg+1);
564 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
565 }
566566 }
567567 }
568568 }
825825 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(RetReg);
826826 BuildMI(BB, X86::MOVrr32, 1, X86::EDX).addReg(RetReg+1);
827827 // Declare that EAX & EDX are live on exit
828 BuildMI(BB, X86::IMPLICIT_USE, 3).addReg(X86::EAX).addReg(X86::EDX).addReg(X86::ESP);
828 BuildMI(BB, X86::IMPLICIT_USE, 3).addReg(X86::EAX).addReg(X86::EDX)
829 .addReg(X86::ESP);
829830 break;
830831 default:
831832 visitInstruction(I);
876877
877878 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
878879 MachineBasicBlock::iterator MII = BB->end();
879 OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB, MII);
880 OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
880881
881882 const Type *CompTy = SCI->getOperand(0)->getType();
882883 bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
919920 /// it inserts the specified CallMI instruction into the stream.
920921 ///
921922 void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
922 const std::vector &Args) {
923 const std::vector &Args) {
923924
924925 // Count how many bytes are to be pushed on the stack...
925926 unsigned NumBytes = 0;
928929 for (unsigned i = 0, e = Args.size(); i != e; ++i)
929930 switch (getClassB(Args[i].Ty)) {
930931 case cByte: case cShort: case cInt:
931 NumBytes += 4; break;
932 NumBytes += 4; break;
932933 case cLong:
933 NumBytes += 8; break;
934 NumBytes += 8; break;
934935 case cFP:
935 NumBytes += Args[i].Ty == Type::FloatTy ? 4 : 8;
936 break;
936 NumBytes += Args[i].Ty == Type::FloatTy ? 4 : 8;
937 break;
937938 default: assert(0 && "Unknown class!");
938939 }
939940
947948 switch (getClassB(Args[i].Ty)) {
948949 case cByte:
949950 case cShort: {
950 // Promote arg to 32 bits wide into a temporary register...
951 unsigned R = makeAnotherReg(Type::UIntTy);
952 promote32(R, Args[i]);
953 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
954 X86::ESP, ArgOffset).addReg(R);
955 break;
951 // Promote arg to 32 bits wide into a temporary register...
952 unsigned R = makeAnotherReg(Type::UIntTy);
953 promote32(R, Args[i]);
954 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
955 X86::ESP, ArgOffset).addReg(R);
956 break;
956957 }
957958 case cInt:
958 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
959 X86::ESP, ArgOffset).addReg(ArgReg);
960 break;
959 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
960 X86::ESP, ArgOffset).addReg(ArgReg);
961 break;
961962 case cLong:
962 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
963 X86::ESP, ArgOffset).addReg(ArgReg);
964 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
965 X86::ESP, ArgOffset+4).addReg(ArgReg+1);
966 ArgOffset += 4; // 8 byte entry, not 4.
967 break;
968
963 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
964 X86::ESP, ArgOffset).addReg(ArgReg);
965 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
966 X86::ESP, ArgOffset+4).addReg(ArgReg+1);
967 ArgOffset += 4; // 8 byte entry, not 4.
968 break;
969
969970 case cFP:
970 if (Args[i].Ty == Type::FloatTy) {
971 addRegOffset(BuildMI(BB, X86::FSTr32, 5),
972 X86::ESP, ArgOffset).addReg(ArgReg);
973 } else {
974 assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
975 addRegOffset(BuildMI(BB, X86::FSTr64, 5),
976 X86::ESP, ArgOffset).addReg(ArgReg);
977 ArgOffset += 4; // 8 byte entry, not 4.
978 }
979 break;
971 if (Args[i].Ty == Type::FloatTy) {
972 addRegOffset(BuildMI(BB, X86::FSTr32, 5),
973 X86::ESP, ArgOffset).addReg(ArgReg);
974 } else {
975 assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
976 addRegOffset(BuildMI(BB, X86::FSTr64, 5),
977 X86::ESP, ArgOffset).addReg(ArgReg);
978 ArgOffset += 4; // 8 byte entry, not 4.
979 }
980 break;
980981
981982 default: assert(0 && "Unknown class!");
982983 }
10021003 // Integral results are in %eax, or the appropriate portion
10031004 // thereof.
10041005 static const unsigned regRegMove[] = {
1005 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32
1006 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32
10061007 };
10071008 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
10081009 BuildMI(BB, regRegMove[DestClass], 1, Ret.Reg).addReg(AReg[DestClass]);
10441045
10451046 unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
10461047 doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args);
1047 }
1048 }
10481049
10491050
10501051 void ISel::visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &CI) {
13191320
13201321 unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
13211322 BuildMI(BB, X86::ADDrr32, 2, // AH*BL+(AL*BL >> 32)
1322 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
1323 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
13231324
13241325 MBBI = BB->end();
13251326 unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
13261327 BMI(BB, MBBI, X86::IMULrr32, 2, ALBHReg).addReg(Op0Reg).addReg(Op1Reg+1);
13271328
13281329 BuildMI(BB, X86::ADDrr32, 2, // AL*BH + AH*BL + (AL*BL >> 32)
1329 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
1330 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
13301331 }
13311332 }
13321333
13481349 BuildMI(BB, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
13491350 } else { // Floating point remainder...
13501351 MachineInstr *TheCall =
1351 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true);
1352 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true);
13521353 std::vector Args;
13531354 Args.push_back(ValueRecord(I.getOperand(0)));
13541355 Args.push_back(ValueRecord(I.getOperand(1)));
14501451 if (ConstantUInt *CUI = dyn_cast(I.getOperand(1))) {
14511452 unsigned Amount = CUI->getValue();
14521453 if (Amount < 32) {
1453 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
1454 if (isLeftShift) {
1455 BuildMI(BB, Opc[3], 3,
1456 DestReg+1).addReg(SrcReg+1).addReg(SrcReg).addZImm(Amount);
1457 BuildMI(BB, Opc[2], 2, DestReg).addReg(SrcReg).addZImm(Amount);
1458 } else {
1459 BuildMI(BB, Opc[3], 3,
1460 DestReg).addReg(SrcReg ).addReg(SrcReg+1).addZImm(Amount);
1461 BuildMI(BB, Opc[2], 2, DestReg+1).addReg(SrcReg+1).addZImm(Amount);
1462 }
1454 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
1455 if (isLeftShift) {
1456 BuildMI(BB, Opc[3], 3,
1457 DestReg+1).addReg(SrcReg+1).addReg(SrcReg).addZImm(Amount);
1458 BuildMI(BB, Opc[2], 2, DestReg).addReg(SrcReg).addZImm(Amount);
1459 } else {
1460 BuildMI(BB, Opc[3], 3,
1461 DestReg).addReg(SrcReg ).addReg(SrcReg+1).addZImm(Amount);
1462 BuildMI(BB, Opc[2], 2, DestReg+1).addReg(SrcReg+1).addZImm(Amount);
1463 }
14631464 } else { // Shifting more than 32 bits
1464 Amount -= 32;
1465 if (isLeftShift) {
1466 BuildMI(BB, X86::SHLir32, 2,DestReg+1).addReg(SrcReg).addZImm(Amount);
1467 BuildMI(BB, X86::MOVir32, 1,DestReg ).addZImm(0);
1468 } else {
1469 unsigned Opcode = isSigned ? X86::SARir32 : X86::SHRir32;
1470 BuildMI(BB, Opcode, 2, DestReg).addReg(SrcReg+1).addZImm(Amount);
1471 BuildMI(BB, X86::MOVir32, 1, DestReg+1).addZImm(0);
1472 }
1465 Amount -= 32;
1466 if (isLeftShift) {
1467 BuildMI(BB, X86::SHLir32, 2,DestReg+1).addReg(SrcReg).addZImm(Amount);
1468 BuildMI(BB, X86::MOVir32, 1,DestReg ).addZImm(0);
1469 } else {
1470 unsigned Opcode = isSigned ? X86::SARir32 : X86::SHRir32;
1471 BuildMI(BB, Opcode, 2, DestReg).addReg(SrcReg+1).addZImm(Amount);
1472 BuildMI(BB, X86::MOVir32, 1, DestReg+1).addZImm(0);
1473 }
14731474 }
14741475 } else {
14751476 unsigned TmpReg = makeAnotherReg(Type::IntTy);
16961697 BMI(BB, IP, RegRegMove[SrcClass], 1, DestReg).addReg(SrcReg);
16971698 } else if (SrcClass == cFP) {
16981699 if (SrcTy == Type::FloatTy) { // double -> float
1699 assert(DestTy == Type::DoubleTy && "Unknown cFP member!");
1700 BMI(BB, IP, X86::FpMOV, 1, DestReg).addReg(SrcReg);
1700 assert(DestTy == Type::DoubleTy && "Unknown cFP member!");
1701 BMI(BB, IP, X86::FpMOV, 1, DestReg).addReg(SrcReg);
17011702 } else { // float -> double
1702 assert(SrcTy == Type::DoubleTy && DestTy == Type::FloatTy &&
1703 "Unknown cFP member!");
1704 // Truncate from double to float by storing to memory as short, then
1705 // reading it back.
1706 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
1703 assert(SrcTy == Type::DoubleTy && DestTy == Type::FloatTy &&
1704 "Unknown cFP member!");
1705 // Truncate from double to float by storing to memory as short, then
1706 // reading it back.
1707 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
17071708 int FrameIdx = F->getFrameInfo()->CreateStackObject(4, FltAlign);
1708 addFrameReference(BMI(BB, IP, X86::FSTr32, 5), FrameIdx).addReg(SrcReg);
1709 addFrameReference(BMI(BB, IP, X86::FLDr32, 5, DestReg), FrameIdx);
1709 addFrameReference(BMI(BB, IP, X86::FSTr32, 5), FrameIdx).addReg(SrcReg);
1710 addFrameReference(BMI(BB, IP, X86::FLDr32, 5, DestReg), FrameIdx);
17101711 }
17111712 } else if (SrcClass == cLong) {
17121713 BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg);
17361737
17371738 if (isLong) { // Handle upper 32 bits as appropriate...
17381739 if (isUnsigned) // Zero out top bits...
1739 BMI(BB, IP, X86::MOVir32, 1, DestReg+1).addZImm(0);
1740 BMI(BB, IP, X86::MOVir32, 1, DestReg+1).addZImm(0);
17401741 else // Sign extend bottom half...
1741 BMI(BB, IP, X86::SARir32, 2, DestReg+1).addReg(DestReg).addZImm(31);
1742 BMI(BB, IP, X86::SARir32, 2, DestReg+1).addReg(DestReg).addZImm(31);
17421743 }
17431744 return;
17441745 }
18151816 if (SrcClass == cLong) {
18161817 addFrameReference(BMI(BB, IP, X86::MOVrm32, 5), FrameIdx).addReg(SrcReg);
18171818 addFrameReference(BMI(BB, IP, X86::MOVrm32, 5),
1818 FrameIdx, 4).addReg(SrcReg+1);
1819 FrameIdx, 4).addReg(SrcReg+1);
18191820 } else {
18201821 static const unsigned Op1[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
18211822 addFrameReference(BMI(BB, IP, Op1[SrcClass], 5), FrameIdx).addReg(SrcReg);
18471848
18481849 // Restore the memory image of control word to original value
18491850 addFrameReference(BMI(BB, IP, X86::MOVrm8, 5),
1850 CWFrameIdx, 1).addReg(HighPartOfCW);
1851 CWFrameIdx, 1).addReg(HighPartOfCW);
18511852
18521853 // We don't have the facilities for directly storing byte sized data to
18531854 // memory. Promote it to 16 bits. We also must promote unsigned values to
19721973 // which names the field. This index must have ubyte type.
19731974 const ConstantUInt *CUI = cast(idx);
19741975 assert(CUI->getType() == Type::UByteTy
1975 && "Funny-looking structure index in GEP");
1976 && "Funny-looking structure index in GEP");
19761977 // Use the TargetData structure to pick out what the layout of
19771978 // the structure is in memory. Since the structure index must
19781979 // be constant, we can get its value and use it to find the
19811982 unsigned idxValue = CUI->getValue();
19821983 unsigned FieldOff = TD.getStructLayout(StTy)->MemberOffsets[idxValue];
19831984 if (FieldOff) {
1984 NextReg = makeAnotherReg(Type::UIntTy);
1985 // Emit an ADD to add FieldOff to the basePtr.
1986 BMI(MBB, IP, X86::ADDri32, 2,NextReg).addReg(BaseReg).addZImm(FieldOff);
1985 NextReg = makeAnotherReg(Type::UIntTy);
1986 // Emit an ADD to add FieldOff to the basePtr.
1987 BMI(MBB, IP, X86::ADDri32, 2,NextReg).addReg(BaseReg).addZImm(FieldOff);
19871988 }
19881989 // The next type is the member of the structure selected by the
19891990 // index.
20132014 if (ConstantSInt *CSI = dyn_cast(idx)) {
20142015 if (!CSI->isNullValue()) {
20152016 unsigned Offset = elementSize*CSI->getValue();
2016 NextReg = makeAnotherReg(Type::UIntTy);
2017 NextReg = makeAnotherReg(Type::UIntTy);
20172018 BMI(MBB, IP, X86::ADDri32, 2,NextReg).addReg(BaseReg).addZImm(Offset);
20182019 }
20192020 } else if (elementSize == 1) {
20202021 // If the element size is 1, we don't have to multiply, just add
20212022 unsigned idxReg = getReg(idx, MBB, IP);
2022 NextReg = makeAnotherReg(Type::UIntTy);
2023 NextReg = makeAnotherReg(Type::UIntTy);
20232024 BMI(MBB, IP, X86::ADDrr32, 2, NextReg).addReg(BaseReg).addReg(idxReg);
20242025 } else {
20252026 unsigned idxReg = getReg(idx, MBB, IP);
20282029 doMultiplyConst(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSize);
20292030
20302031 // Emit an ADD to add OffsetReg to the basePtr.
2031 NextReg = makeAnotherReg(Type::UIntTy);
2032 NextReg = makeAnotherReg(Type::UIntTy);
20322033 BMI(MBB, IP, X86::ADDrr32, 2,NextReg).addReg(BaseReg).addReg(OffsetReg);
20332034 }
20342035 }
21152116 std::vector Args;
21162117 Args.push_back(ValueRecord(Arg, Type::UIntTy));
21172118 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
2118 1).addExternalSymbol("malloc", true);
2119 1).addExternalSymbol("malloc", true);
21192120 doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args);
21202121 }
21212122
21272128 std::vector Args;
21282129 Args.push_back(ValueRecord(I.getOperand(0)));
21292130 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
2130 1).addExternalSymbol("free", true);
2131 1).addExternalSymbol("free", true);
21312132 doCall(ValueRecord(0, Type::VoidTy), TheCall, Args);
21322133 }
21332134