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[C++] Use 'nullptr'. Target edition. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207197 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 5 years ago
189 changed file(s) with 1088 addition(s) and 1065 deletion(s). Raw diff Collapse all Expand all
449449 /// displacement field.
450450 bool AArch64BranchFixup::fixupImmediateBr(ImmBranch &Br) {
451451 MachineInstr *MI = Br.MI;
452 MachineBasicBlock *DestBB = 0;
452 MachineBasicBlock *DestBB = nullptr;
453453 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
454454 if (MI->getOperand(i).isMBB()) {
455455 DestBB = MI->getOperand(i).getMBB();
260260 } else {
261261 // Can't handle it in one instruction. There's scope for permitting two (or
262262 // more) instructions, but that'll need more thought.
263 return NULL;
263 return nullptr;
264264 }
265265
266266 ResNode = CurDAG->getMachineNode(MOVOpcode, dl, MOVType,
736736 if (isUpdating)
737737 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
738738
739 return NULL;
739 return nullptr;
740740 }
741741
742742 SDNode *AArch64DAGToDAGISel::SelectVST(SDNode *N, bool isUpdating,
861861 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
862862 if (isUpdating)
863863 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
864 return NULL;
864 return nullptr;
865865 }
866866
867867 // We only have 128-bit vector type of load/store lane instructions.
955955 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
956956 if (isUpdating)
957957 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
958 return NULL;
958 return nullptr;
959959 }
960960
961961 unsigned AArch64DAGToDAGISel::getTBLOpc(bool IsExt, bool Is64Bit,
10301030 if (Node->isMachineOpcode()) {
10311031 DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");
10321032 Node->setNodeId(-1);
1033 return NULL;
1033 return nullptr;
10341034 }
10351035
10361036 switch (Node->getOpcode()) {
11141114 TFI, CurDAG->getTargetConstant(0, PtrTy));
11151115 }
11161116 case ISD::Constant: {
1117 SDNode *ResNode = 0;
1117 SDNode *ResNode = nullptr;
11181118 if (cast(Node)->getZExtValue() == 0) {
11191119 // XZR and WZR are probably even better than an actual move: most of the
11201120 // time they can be folded into another instruction with *no* cost.
588588 // would fail to figure out the register pressure correctly.
589589 std::pair
590590 AArch64TargetLowering::findRepresentativeClass(MVT VT) const{
591 const TargetRegisterClass *RRC = 0;
591 const TargetRegisterClass *RRC = nullptr;
592592 uint8_t Cost = 1;
593593 switch (VT.SimpleTy) {
594594 default:
11841184 case AArch64ISD::NEON_VEXTRACT:
11851185 return "AArch64ISD::NEON_VEXTRACT";
11861186 default:
1187 return NULL;
1187 return nullptr;
11881188 }
11891189 }
11901190
21582158
21592159 // If softenSetCCOperands returned a scalar, we need to compare the result
21602160 // against zero to select between true and false values.
2161 if (RHS.getNode() == 0) {
2161 if (!RHS.getNode()) {
21622162 RHS = DAG.getConstant(0, LHS.getValueType());
21632163 CC = ISD::SETNE;
21642164 }
30183018 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
30193019
30203020 // If softenSetCCOperands returned a scalar, use it.
3021 if (RHS.getNode() == 0) {
3021 if (!RHS.getNode()) {
30223022 assert(LHS.getValueType() == Op.getValueType() &&
30233023 "Unexpected setcc expansion!");
30243024 return LHS;
31663166
31673167 // If softenSetCCOperands returned a scalar, we need to compare the result
31683168 // against zero to select between true and false values.
3169 if (RHS.getNode() == 0) {
3169 if (!RHS.getNode()) {
31703170 RHS = DAG.getConstant(0, LHS.getValueType());
31713171 CC = ISD::SETNE;
31723172 }
45344534 VT.getVectorElementType())
45354535 return false;
45364536
4537 if (V0.getNode() == 0) {
4537 if (!V0.getNode()) {
45384538 V0 = Elt.getOperand(0);
45394539 V0NumElts = V0.getValueType().getVectorNumElements();
45404540 }
45414541 if (Elt.getOperand(0) == V0) {
45424542 Mask[i] = (cast(Elt->getOperand(1))->getZExtValue());
45434543 continue;
4544 } else if (V1.getNode() == 0) {
4544 } else if (!V1.getNode()) {
45454545 V1 = Elt.getOperand(0);
45464546 }
45474547 if (Elt.getOperand(0) == V1) {
52425242 std::string &Constraint,
52435243 std::vector &Ops,
52445244 SelectionDAG &DAG) const {
5245 SDValue Result(0, 0);
5245 SDValue Result;
52465246
52475247 // Only length 1 constraints are C_Other.
52485248 if (Constraint.size() != 1) return;
390390 MachineBasicBlock *FBB,
391391 const SmallVectorImpl &Cond,
392392 DebugLoc DL) const {
393 if (FBB == 0 && Cond.empty()) {
393 if (!FBB && Cond.empty()) {
394394 BuildMI(&MBB, DL, get(AArch64::Bimm)).addMBB(TBB);
395395 return 1;
396 } else if (FBB == 0) {
396 } else if (!FBB) {
397397 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
398398 for (int i = 1, e = Cond.size(); i != e; ++i)
399399 MIB.addOperand(Cond[i]);
2929 MCOperand
3030 AArch64AsmPrinter::lowerSymbolOperand(const MachineOperand &MO,
3131 const MCSymbol *Sym) const {
32 const MCExpr *Expr = 0;
32 const MCExpr *Expr = nullptr;
3333
3434 Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None, OutContext);
3535
3737 const AArch64TargetLowering *TLI;
3838
3939 public:
40 AArch64TTI() : ImmutablePass(ID), ST(0), TLI(0) {
40 AArch64TTI() : ImmutablePass(ID), ST(nullptr), TLI(nullptr) {
4141 llvm_unreachable("This pass cannot be directly constructed");
4242 }
4343
13121312 case AsmToken::Colon: {
13131313 SMLoc StartLoc = Parser.getTok().getLoc();
13141314 SMLoc EndLoc;
1315 const MCExpr *ImmVal = 0;
1315 const MCExpr *ImmVal = nullptr;
13161316
13171317 if (ParseImmediate(ImmVal) != MatchOperand_Success)
13181318 return MatchOperand_ParseFail;
13241324 case AsmToken::Hash: { // Immediates
13251325 SMLoc StartLoc = Parser.getTok().getLoc();
13261326 SMLoc EndLoc;
1327 const MCExpr *ImmVal = 0;
1327 const MCExpr *ImmVal = nullptr;
13281328 Parser.Lex();
13291329
13301330 if (ParseImmediate(ImmVal) != MatchOperand_Success)
6262
6363 MCAsmInfo *MAI = new AArch64ELFMCAsmInfo(TT);
6464 unsigned Reg = MRI.getDwarfRegNum(AArch64::XSP, true);
65 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(0, Reg, 0);
65 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
6666 MAI->addInitialFrameState(Inst);
6767
6868 return MAI;
113113 const MCSubtargetInfo &STI) {
114114 if (SyntaxVariant == 0)
115115 return new AArch64InstPrinter(MAI, MII, MRI, STI);
116 return 0;
116 return nullptr;
117117 }
118118
119119 namespace {
259259 if (DPRMI && SPRMI) {
260260 // See if the first operand of this insert_subreg is IMPLICIT_DEF
261261 MachineInstr *ECDef = elideCopies(DPRMI);
262 if (ECDef != 0 && ECDef->isImplicitDef()) {
262 if (ECDef && ECDef->isImplicitDef()) {
263263 // Another corner case - if we're inserting something that is purely
264264 // a subreg copy of a DPR, just use that DPR.
265265
348348 if (!MI->isFullCopy())
349349 return MI;
350350 if (!TRI->isVirtualRegister(MI->getOperand(1).getReg()))
351 return NULL;
351 return nullptr;
352352 MachineInstr *Def = MRI->getVRegDef(MI->getOperand(1).getReg());
353353 if (!Def)
354 return NULL;
354 return nullptr;
355355 return elideCopies(Def);
356356 }
357357
383383 // If either end mode is unknown (EndInfo == NULL) or different than
384384 // the start mode, then restore the start mode.
385385 const bool WasThumb = isThumb(StartInfo);
386 if (EndInfo == NULL || WasThumb != isThumb(*EndInfo)) {
386 if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
387387 OutStreamer.EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
388388 }
389389 }
723723 MachineModuleInfoImpl::StubValueTy &StubSym =
724724 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
725725 MMIMachO.getGVStubEntry(MCSym);
726 if (StubSym.getPointer() == 0)
726 if (!StubSym.getPointer())
727727 StubSym = MachineModuleInfoImpl::
728728 StubValueTy(getSymbol(GV), !GV->hasInternalLinkage());
729729 return MCSym;
126126 // FIXME: Thumb2 support.
127127
128128 if (!EnableARM3Addr)
129 return NULL;
129 return nullptr;
130130
131131 MachineInstr *MI = MBBI;
132132 MachineFunction &MF = *MI->getParent()->getParent();
133133 uint64_t TSFlags = MI->getDesc().TSFlags;
134134 bool isPre = false;
135135 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
136 default: return NULL;
136 default: return nullptr;
137137 case ARMII::IndexModePre:
138138 isPre = true;
139139 break;
145145 // operation.
146146 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
147147 if (MemOpc == 0)
148 return NULL;
149
150 MachineInstr *UpdateMI = NULL;
151 MachineInstr *MemMI = NULL;
148 return nullptr;
149
150 MachineInstr *UpdateMI = nullptr;
151 MachineInstr *MemMI = nullptr;
152152 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
153153 const MCInstrDesc &MCID = MI->getDesc();
154154 unsigned NumOps = MCID.getNumOperands();
170170 if (ARM_AM::getSOImmVal(Amt) == -1)
171171 // Can't encode it in a so_imm operand. This transformation will
172172 // add more than 1 instruction. Abandon!
173 return NULL;
173 return nullptr;
174174 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
175175 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
176176 .addReg(BaseReg).addImm(Amt)
274274 MachineBasicBlock *&FBB,
275275 SmallVectorImpl &Cond,
276276 bool AllowModify) const {
277 TBB = 0;
278 FBB = 0;
277 TBB = nullptr;
278 FBB = nullptr;
279279
280280 MachineBasicBlock::iterator I = MBB.end();
281281 if (I == MBB.begin())
332332 I->isReturn())) {
333333 // Forget any previous condition branch information - it no longer applies.
334334 Cond.clear();
335 FBB = 0;
335 FBB = nullptr;
336336
337337 // If we can modify the function, delete everything below this
338338 // unconditional branch.
406406 assert((Cond.size() == 2 || Cond.size() == 0) &&
407407 "ARM branch conditions have two components!");
408408
409 if (FBB == 0) {
409 if (!FBB) {
410410 if (Cond.empty()) { // Unconditional branch?
411411 if (isThumb)
412412 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
12511251 static_cast(MCPE.Val.MachineCPVal);
12521252
12531253 unsigned PCLabelId = AFI->createPICLabelUId();
1254 ARMConstantPoolValue *NewCPV = 0;
1254 ARMConstantPoolValue *NewCPV = nullptr;
12551255
12561256 // FIXME: The below assumes PIC relocation model and that the function
12571257 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
16621662 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg);
16631663 // MOVCC AL can't be inverted. Shouldn't happen.
16641664 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
1665 return NULL;
1665 return nullptr;
16661666 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
16671667 if (!MI)
1668 return NULL;
1668 return nullptr;
16691669 // After swapping the MOVCC operands, also invert the condition.
16701670 MI->getOperand(MI->findFirstPredOperandIdx())
16711671 .setImm(ARMCC::getOppositeCondition(CC));
16811681 const MachineRegisterInfo &MRI,
16821682 const TargetInstrInfo *TII) {
16831683 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1684 return 0;
1684 return nullptr;
16851685 if (!MRI.hasOneNonDBGUse(Reg))
1686 return 0;
1686 return nullptr;
16871687 MachineInstr *MI = MRI.getVRegDef(Reg);
16881688 if (!MI)
1689 return 0;
1689 return nullptr;
16901690 // MI is folded into the MOVCC by predicating it.
16911691 if (!MI->isPredicable())
1692 return 0;
1692 return nullptr;
16931693 // Check if MI has any non-dead defs or physreg uses. This also detects
16941694 // predicated instructions which will be reading CPSR.
16951695 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
16961696 const MachineOperand &MO = MI->getOperand(i);
16971697 // Reject frame index operands, PEI can't handle the predicated pseudos.
16981698 if (MO.isFI() || MO.isCPI() || MO.isJTI())
1699 return 0;
1699 return nullptr;
17001700 if (!MO.isReg())
17011701 continue;
17021702 // MI can't have any tied operands, that would conflict with predication.
17031703 if (MO.isTied())
1704 return 0;
1704 return nullptr;
17051705 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
1706 return 0;
1706 return nullptr;
17071707 if (MO.isDef() && !MO.isDead())
1708 return 0;
1708 return nullptr;
17091709 }
17101710 bool DontMoveAcrossStores = true;
1711 if (!MI->isSafeToMove(TII, /* AliasAnalysis = */ 0, DontMoveAcrossStores))
1712 return 0;
1711 if (!MI->isSafeToMove(TII, /* AliasAnalysis = */ nullptr,
1712 DontMoveAcrossStores))
1713 return nullptr;
17131714 return MI;
17141715 }
17151716
17441745 if (!DefMI)
17451746 DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this);
17461747 if (!DefMI)
1747 return 0;
1748 return nullptr;
17481749
17491750 // Find new register class to use.
17501751 MachineOperand FalseReg = MI->getOperand(Invert ? 2 : 1);
17511752 unsigned DestReg = MI->getOperand(0).getReg();
17521753 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
17531754 if (!MRI.constrainRegClass(DestReg, PreviousClass))
1754 return 0;
1755 return nullptr;
17551756
17561757 // Create a new predicated version of DefMI.
17571758 // Rfalse is the first use.
22572258 // Masked compares sometimes use the same register as the corresponding 'and'.
22582259 if (CmpMask != ~0) {
22592260 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) {
2260 MI = 0;
2261 MI = nullptr;
22612262 for (MachineRegisterInfo::use_instr_iterator
22622263 UI = MRI->use_instr_begin(SrcReg), UE = MRI->use_instr_end();
22632264 UI != UE; ++UI) {
22842285 // One is MI, the other is a SUB instruction.
22852286 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
22862287 // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue).
2287 MachineInstr *Sub = NULL;
2288 MachineInstr *Sub = nullptr;
22882289 if (SrcReg2 != 0)
22892290 // MI is not a candidate for CMPrr.
2290 MI = NULL;
2291 MI = nullptr;
22912292 else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) {
22922293 // Conservatively refuse to convert an instruction which isn't in the same
22932294 // BB as the comparison.
22942295 // For CMPri, we need to check Sub, thus we can't return here.
22952296 if (CmpInstr->getOpcode() == ARM::CMPri ||
22962297 CmpInstr->getOpcode() == ARM::t2CMPri)
2297 MI = NULL;
2298 MI = nullptr;
22982299 else
22992300 return false;
23002301 }
32983299
32993300 if (Idx == -1) {
33003301 Dist = 0;
3301 return 0;
3302 return nullptr;
33023303 }
33033304
33043305 UseIdx = Idx;
106106 // should return NULL
107107 if (CC == CallingConv::GHC)
108108 // This is academic becase all GHC calls are (supposed to be) tail calls
109 return NULL;
109 return nullptr;
110110 return (STI.isTargetIOS() && !STI.isAAPCS_ABI())
111111 ? CSR_iOS_ThisReturn_RegMask : CSR_AAPCS_ThisReturn_RegMask;
112112 }
172172 const TargetRegisterClass *
173173 ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
174174 if (RC == &ARM::CCRRegClass)
175 return 0; // Can't copy CCR registers.
175 return nullptr; // Can't copy CCR registers.
176176 return RC;
177177 }
178178
6565 static char ID;
6666 public:
6767 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68 : MachineFunctionPass(ID), JTI(0),
68 : MachineFunctionPass(ID), JTI(nullptr),
6969 II((const ARMBaseInstrInfo *)tm.getInstrInfo()),
7070 TD(tm.getDataLayout()), TM(tm),
71 MCE(mce), MCPEs(0), MJTEs(0),
71 MCE(mce), MCPEs(nullptr), MJTEs(nullptr),
7272 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
7373
7474 /// getBinaryCodeForInstr - This function, generated by the
373373
374374 Subtarget = &TM.getSubtarget();
375375 MCPEs = &MF.getConstantPool()->getConstants();
376 MJTEs = 0;
376 MJTEs = nullptr;
377377 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
378378 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
379379 IsThumb = MF.getInfo()->isThumbFunction();
593593 if (CPEs[i].CPEMI == CPEMI)
594594 return &CPEs[i];
595595 }
596 return NULL;
596 return nullptr;
597597 }
598598
599599 /// getCPELogAlign - Returns the required alignment of the constant pool entry
11021102 assert(CPE && "Unexpected!");
11031103 if (--CPE->RefCount == 0) {
11041104 removeDeadCPEMI(CPEMI);
1105 CPE->CPEMI = NULL;
1105 CPE->CPEMI = nullptr;
11061106 --NumCPEs;
11071107 return true;
11081108 }
11351135 if (CPEs[i].CPEMI == CPEMI)
11361136 continue;
11371137 // Removing CPEs can leave empty entries, skip
1138 if (CPEs[i].CPEMI == NULL)
1138 if (CPEs[i].CPEMI == nullptr)
11391139 continue;
11401140 if (isCPEntryInRange(UserMI, UserOffset, CPEs[i].CPEMI, U.getMaxDisp(),
11411141 U.NegOk)) {
13171317 ++MI;
13181318 unsigned CPUIndex = CPUserIndex+1;
13191319 unsigned NumCPUsers = CPUsers.size();
1320 MachineInstr *LastIT = 0;
1320 MachineInstr *LastIT = nullptr;
13211321 for (unsigned Offset = UserOffset+TII->GetInstSizeInBytes(UserMI);
13221322 Offset < BaseInsertOffset;
13231323 Offset += TII->GetInstSizeInBytes(MI), MI = std::next(MI)) {
14911491 for (unsigned j = 0, ee = CPEs.size(); j != ee; ++j) {
14921492 if (CPEs[j].RefCount == 0 && CPEs[j].CPEMI) {
14931493 removeDeadCPEMI(CPEs[j].CPEMI);
1494 CPEs[j].CPEMI = NULL;
1494 CPEs[j].CPEMI = nullptr;
14951495 MadeChange = true;
14961496 }
14971497 }
18441844 // FIXME: After the tables are shrunk, can we get rid some of the
18451845 // constantpool tables?
18461846 MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1847 if (MJTI == 0) return false;
1847 if (!MJTI) return false;
18481848
18491849 const std::vector &JT = MJTI->getJumpTables();
18501850 for (unsigned i = 0, e = T2JumpTables.size(); i != e; ++i) {
19701970 bool MadeChange = false;
19711971
19721972 MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1973 if (MJTI == 0) return false;
1973 if (!MJTI) return false;
19741974
19751975 const std::vector &JT = MJTI->getJumpTables();
19761976 for (unsigned i = 0, e = T2JumpTables.size(); i != e; ++i) {
20122012 // try to move it; otherwise, create a new block following the jump
20132013 // table that branches back to the actual target. This is a very simple
20142014 // heuristic. FIXME: We can definitely improve it.
2015 MachineBasicBlock *TBB = 0, *FBB = 0;
2015 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
20162016 SmallVector Cond;
20172017 SmallVector CondPrior;
20182018 MachineFunction::iterator BBi = BB;
20322032 // Update numbering to account for the block being moved.
20332033 MF->RenumberBlocks();
20342034 ++NumJTMoved;
2035 return NULL;
2035 return nullptr;
20362036 }
20372037
20382038 // Create a new MBB for the code after the jump BB.
345345 std::lower_bound(NEONLdStTable, NEONLdStTable + NumEntries, Opcode);
346346 if (I != NEONLdStTable + NumEntries && I->PseudoOpc == Opcode)
347347 return I;
348 return NULL;
348 return nullptr;
349349 }
350350
351351 /// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register,
749749 // Computes the address to get to an object.
750750 bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
751751 // Some boilerplate from the X86 FastISel.
752 const User *U = NULL;
752 const User *U = nullptr;
753753 unsigned Opcode = Instruction::UserOp1;
754754 if (const Instruction *I = dyn_cast(Obj)) {
755755 // Don't walk into other basic blocks unless the object is an alloca from
21622162 if (!LCREVT.isSimple()) return 0;
21632163
21642164 GlobalValue *GV = new GlobalVariable(M, Type::getInt32Ty(*Context), false,
2165 GlobalValue::ExternalLinkage, 0, Name);
2165 GlobalValue::ExternalLinkage, nullptr,
2166 Name);
21662167 assert(GV->getType() == GVTy && "We miscomputed the type for the global!");
21672168 return ARMMaterializeGV(GV, LCREVT.getSimpleVT());
21682169 }
22662267 }
22672268
22682269 bool ARMFastISel::SelectCall(const Instruction *I,
2269 const char *IntrMemName = 0) {
2270 const char *IntrMemName = nullptr) {
22702271 const CallInst *CI = cast(I);
22712272 const Value *Callee = CI->getCalledValue();
22722273
30723073 TM.Options.NoFramePointerElim = true;
30733074 return new ARMFastISel(funcInfo, libInfo);
30743075 }
3075 return 0;
3076 }
3077 }
3076 return nullptr;
3077 }
3078 }
7676 }
7777
7878 void ARMHazardRecognizer::Reset() {
79 LastMI = 0;
79 LastMI = nullptr;
8080 FpMLxStalls = 0;
8181 ScoreboardHazardRecognizer::Reset();
8282 }
9494 void ARMHazardRecognizer::AdvanceCycle() {
9595 if (FpMLxStalls && --FpMLxStalls == 0)
9696 // Stalled for 4 cycles but still can't schedule any other instructions.
97 LastMI = 0;
97 LastMI = nullptr;
9898 ScoreboardHazardRecognizer::AdvanceCycle();
9999 }
100100
14401440 LoadSDNode *LD = cast(N);
14411441 ISD::MemIndexedMode AM = LD->getAddressingMode();
14421442 if (AM == ISD::UNINDEXED)
1443 return NULL;
1443 return nullptr;
14441444
14451445 EVT LoadedVT = LD->getMemoryVT();
14461446 SDValue Offset, AMOpc;
15061506 }
15071507 }
15081508
1509 return NULL;
1509 return nullptr;
15101510 }
15111511
15121512 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
15131513 LoadSDNode *LD = cast(N);
15141514 ISD::MemIndexedMode AM = LD->getAddressingMode();
15151515 if (AM == ISD::UNINDEXED)
1516 return NULL;
1516 return nullptr;
15171517
15181518 EVT LoadedVT = LD->getMemoryVT();
15191519 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
15401540 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
15411541 break;
15421542 default:
1543 return NULL;
1543 return nullptr;
15441544 }
15451545 Match = true;
15461546 }
15541554 MVT::Other, Ops);
15551555 }
15561556
1557 return NULL;
1557 return nullptr;
15581558 }
15591559
15601560 /// \brief Form a GPRPair pseudo register from a pair of GPR regs.
17761776 SDValue MemAddr, Align;
17771777 unsigned AddrOpIdx = isUpdating ? 1 : 2;
17781778 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1779 return NULL;
1779 return nullptr;
17801780
17811781 SDValue Chain = N->getOperand(0);
17821782 EVT VT = N->getValueType(0);
18951895 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
18961896 if (isUpdating)
18971897 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
1898 return NULL;
1898 return nullptr;
18991899 }
19001900
19011901 SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
19091909 unsigned AddrOpIdx = isUpdating ? 1 : 2;
19101910 unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
19111911 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1912 return NULL;
1912 return nullptr;
19131913
19141914 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
19151915 MemOp[0] = cast(N)->getMemOperand();
20552055 unsigned AddrOpIdx = isUpdating ? 1 : 2;
20562056 unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
20572057 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
2058 return NULL;
2058 return nullptr;
20592059
20602060 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
20612061 MemOp[0] = cast(N)->getMemOperand();
21602160 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
21612161 if (isUpdating)
21622162 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
2163 return NULL;
2163 return nullptr;
21642164 }
21652165
21662166 SDNode *ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating,
21712171
21722172 SDValue MemAddr, Align;
21732173 if (!SelectAddrMode6(N, N->getOperand(1), MemAddr, Align))
2174 return NULL;
2174 return nullptr;
21752175
21762176 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
21772177 MemOp[0] = cast(N)->getMemOperand();
22432243 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
22442244 if (isUpdating)
22452245 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
2246 return NULL;
2246 return nullptr;
22472247 }
22482248
22492249 SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
22822282 SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
22832283 bool isSigned) {
22842284 if (!Subtarget->hasV6T2Ops())
2285 return NULL;
2285 return nullptr;
22862286
22872287 unsigned Opc = isSigned
22882288 ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
22952295
22962296 // The immediate is a mask of the low bits iff imm & (imm+1) == 0
22972297 if (And_imm & (And_imm + 1))
2298 return NULL;
2298 return nullptr;
22992299
23002300 unsigned Srl_imm = 0;
23012301 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
23352335 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
23362336 }
23372337 }
2338 return NULL;
2338 return nullptr;
23392339 }
23402340
23412341 // Otherwise, we're looking for a shift of a shift
23492349 unsigned Width = 32 - Srl_imm - 1;
23502350 int LSB = Srl_imm - Shl_imm;
23512351 if (LSB < 0)
2352 return NULL;
2352 return nullptr;
23532353 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
23542354 SDValue Ops[] = { N->getOperand(0).getOperand(0),
23552355 CurDAG->getTargetConstant(LSB, MVT::i32),
23582358 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
23592359 }
23602360 }
2361 return NULL;
2361 return nullptr;
23622362 }
23632363
23642364 /// Target-specific DAG combining for ISD::XOR.
23772377 EVT VT = N->getValueType(0);
23782378
23792379 if (Subtarget->isThumb1Only())
2380 return NULL;
2380 return nullptr;
23812381
23822382 if (XORSrc0.getOpcode() != ISD::ADD || XORSrc1.getOpcode() != ISD::SRA)
2383 return NULL;
2383 return nullptr;
23842384
23852385 SDValue ADDSrc0 = XORSrc0.getOperand(0);
23862386 SDValue ADDSrc1 = XORSrc0.getOperand(1);
23912391 unsigned Size = XType.getSizeInBits() - 1;
23922392
23932393 if (ADDSrc1 == XORSrc1 && ADDSrc0 == SRASrc0 &&
2394 XType.isInteger() && SRAConstant != NULL &&
2394 XType.isInteger() && SRAConstant != nullptr &&
23952395 Size == SRAConstant->getZExtValue()) {
23962396 unsigned Opcode = Subtarget->isThumb2() ? ARM::t2ABS : ARM::ABS;
23972397 return CurDAG->SelectNodeTo(N, Opcode, VT, ADDSrc0);
23982398 }
23992399
2400 return NULL;
2400 return nullptr;
24012401 }
24022402
24032403 SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
24142414
24152415 if (N->isMachineOpcode()) {
24162416 N->setNodeId(-1);
2417 return NULL; // Already selected.
2417 return nullptr; // Already selected.
24182418 }
24192419
24202420 switch (N->getOpcode()) {
24782478 Ops);
24792479 }
24802480 ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
2481 return NULL;
2481 return nullptr;
24822482 }
24832483
24842484 // Other cases are autogenerated.
26602660 }
26612661 }
26622662 case ISD::LOAD: {
2663 SDNode *ResNode = 0;
2663 SDNode *ResNode = nullptr;
26642664 if (Subtarget->isThumb() && Subtarget->hasThumb2())
26652665 ResNode = SelectT2IndexedLoad(N);
26662666 else
27072707 }
27082708 ReplaceUses(SDValue(N, 0),
27092709 SDValue(Chain.getNode(), Chain.getResNo()));
2710 return NULL;
2710 return nullptr;
27112711 }
27122712 case ARMISD::VZIP: {
27132713 unsigned Opc = 0;
27142714 EVT VT = N->getValueType(0);
27152715 switch (VT.getSimpleVT().SimpleTy) {
2716 default: return NULL;
2716 default: return nullptr;
27172717 case MVT::v8i8: Opc = ARM::VZIPd8; break;
27182718 case MVT::v4i16: Opc = ARM::VZIPd16; break;
27192719 case MVT::v2f32:
27332733 unsigned Opc = 0;
27342734 EVT VT = N->getValueType(0);
27352735 switch (VT.getSimpleVT().SimpleTy) {
2736 default: return NULL;
2736 default: return nullptr;
27372737 case MVT::v8i8: Opc = ARM::VUZPd8; break;
27382738 case MVT::v4i16: Opc = ARM::VUZPd16; break;
27392739 case MVT::v2f32:
27532753 unsigned Opc = 0;
27542754 EVT VT = N->getValueType(0);
27552755 switch (VT.getSimpleVT().SimpleTy) {
2756 default: return NULL;
2756 default: return nullptr;
27572757 case MVT::v8i8: Opc = ARM::VTRNd8; break;
27582758 case MVT::v4i16: Opc = ARM::VTRNd16; break;
27592759 case MVT::v2f32:
28342834 ARM::VLD1q16wb_fixed,
28352835 ARM::VLD1q32wb_fixed,
28362836 ARM::VLD1q64wb_fixed };
2837 return SelectVLD(N, true, 1, DOpcodes, QOpcodes, 0);
2837 return SelectVLD(N, true, 1, DOpcodes, QOpcodes, nullptr);
28382838 }
28392839
28402840 case ARMISD::VLD2_UPD: {
28452845 static const uint16_t QOpcodes[] = { ARM::VLD2q8PseudoWB_fixed,
28462846 ARM::VLD2q16PseudoWB_fixed,
28472847 ARM::VLD2q32PseudoWB_fixed };
2848 return SelectVLD(N, true, 2, DOpcodes, QOpcodes, 0);
2848 return SelectVLD(N, true, 2, DOpcodes, QOpcodes, nullptr);
28492849 }
28502850
28512851 case ARMISD::VLD3_UPD: {
29122912 ARM::VST1q16wb_fixed,
29132913 ARM::VST1q32wb_fixed,
29142914 ARM::VST1q64wb_fixed };
2915 return SelectVST(N, true, 1, DOpcodes, QOpcodes, 0);
2915 return SelectVST(N, true, 1, DOpcodes, QOpcodes, nullptr);
29162916 }
29172917
29182918 case ARMISD::VST2_UPD: {
29232923 static const uint16_t QOpcodes[] = { ARM::VST2q8PseudoWB_fixed,
29242924 ARM::VST2q16PseudoWB_fixed,
29252925 ARM::VST2q32PseudoWB_fixed };
2926 return SelectVST(N, true, 2, DOpcodes, QOpcodes, 0);
2926 return SelectVST(N, true, 2, DOpcodes, QOpcodes, nullptr);
29272927 }
29282928
29292929 case ARMISD::VST3_UPD: {
30473047 ReplaceUses(SDValue(N, 1), Result);
30483048 }
30493049 ReplaceUses(SDValue(N, 2), OutChain);
3050 return NULL;
3050 return nullptr;
30513051 }
30523052 case Intrinsic::arm_stlexd:
30533053 case Intrinsic::arm_strexd: {
30933093 ARM::VLD1d32, ARM::VLD1d64 };
30943094 static const uint16_t QOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16,
30953095 ARM::VLD1q32, ARM::VLD1q64};
3096 return SelectVLD(N, false, 1, DOpcodes, QOpcodes, 0);
3096 return SelectVLD(N, false, 1, DOpcodes, QOpcodes, nullptr);
30973097 }
30983098
30993099 case Intrinsic::arm_neon_vld2: {
31013101 ARM::VLD2d32, ARM::VLD1q64 };
31023102 static const uint16_t QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
31033103 ARM::VLD2q32Pseudo };
3104 return SelectVLD(N, false, 2, DOpcodes, QOpcodes, 0);
3104 return SelectVLD(N, false, 2, DOpcodes, QOpcodes, nullptr);
31053105 }
31063106
31073107 case Intrinsic::arm_neon_vld3: {
31643164 ARM::VST1d32, ARM::VST1d64 };
31653165 static const uint16_t QOpcodes[] = { ARM::VST1q8, ARM::VST1q16,
31663166 ARM::VST1q32, ARM::VST1q64 };
3167 return SelectVST(N, false, 1, DOpcodes, QOpcodes, 0);
3167 return SelectVST(N, false, 1, DOpcodes, QOpcodes, nullptr);
31683168 }
31693169
31703170 case Intrinsic::arm_neon_vst2: {
31723172 ARM::VST2d32, ARM::VST1q64 };
31733173 static uint16_t QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
31743174 ARM::VST2q32Pseudo };
3175 return SelectVST(N, false, 2, DOpcodes, QOpcodes, 0);
3175 return SelectVST(N, false, 2, DOpcodes, QOpcodes, nullptr);
31763176 }
31773177
31783178 case Intrinsic::arm_neon_vst3: {
33063306 // them into a GPRPair.
33073307
33083308 SDLoc dl(N);
3309 SDValue Glue = N->getGluedNode() ? N->getOperand(NumOps-1) : SDValue(0,0);
3309 SDValue Glue = N->getGluedNode() ? N->getOperand(NumOps-1)
3310 : SDValue(nullptr,0);
33103311
33113312 SmallVector OpChanged;
33123313 // Glue node will be appended late.
34353436 if (Glue.getNode())
34363437 AsmNodeOperands.push_back(Glue);
34373438 if (!Changed)
3438 return NULL;
3439 return nullptr;
34393440
34403441 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N),
34413442 CurDAG->getVTList(MVT::Other, MVT::Glue), &AsmNodeOperands[0],
247247 }
248248
249249 // These libcalls are not available in 32-bit.
250 setLibcallName(RTLIB::SHL_I128, 0);
251 setLibcallName(RTLIB::SRL_I128, 0);
252 setLibcallName(RTLIB::SRA_I128, 0);
250 setLibcallName(RTLIB::SHL_I128, nullptr);
251 setLibcallName(RTLIB::SRL_I128, nullptr);
252 setLibcallName(RTLIB::SRA_I128, nullptr);
253253
254254 if (Subtarget->isAAPCS_ABI() && !Subtarget->isTargetMachO() &&
255255 !Subtarget->isTargetWindows()) {
914914 // and extractions.
915915 std::pair
916916 ARMTargetLowering::findRepresentativeClass(MVT VT) const{
917 const TargetRegisterClass *RRC = 0;
917 const TargetRegisterClass *RRC = nullptr;
918918 uint8_t Cost = 1;
919919 switch (VT.SimpleTy) {
920920 default:
951951
952952 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
953953 switch (Opcode) {
954 default: return 0;
954 default: return nullptr;
955955 case ARMISD::Wrapper: return "ARMISD::Wrapper";
956956 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
957957 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
13581358 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
13591359 else {
13601360 assert(NextVA.isMemLoc());
1361 if (StackPtr.getNode() == 0)
1361 if (!StackPtr.getNode())
13621362 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
13631363
13641364 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
28382838 // If there is no regs to be stored, just point address after last
28392839 // argument passed via stack.
28402840 int FrameIndex =
2841 StoreByValRegs(CCInfo, DAG, dl, Chain, 0, CCInfo.getInRegsParamsCount(),
2842 0, ArgOffset, 0, ForceMutable, 0, TotalArgRegsSaveSize);
2841 StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
2842 CCInfo.getInRegsParamsCount(), 0, ArgOffset, 0, ForceMutable,
2843 0, TotalArgRegsSaveSize);
28432844
28442845 AFI->setVarArgsFrameIndex(FrameIndex);
28452846 }
67596760 MachineFunction *MF = BB->getParent();
67606761 MachineRegisterInfo &MRI = MF->getRegInfo();
67616762 unsigned UnitSize = 0;
6762 const TargetRegisterClass *TRC = 0;
6763 const TargetRegisterClass *VecTRC = 0;
6763 const TargetRegisterClass *TRC = nullptr;
6764 const TargetRegisterClass *VecTRC = nullptr;
67646765
67656766 bool IsThumb1 = Subtarget->isThumb1Only();
67666767 bool IsThumb2 = Subtarget->isThumb2();
67946795 ? (const TargetRegisterClass *)&ARM::DPairRegClass
67956796 : UnitSize == 8
67966797 ? (const TargetRegisterClass *)&ARM::DPRRegClass
6797 : 0;
6798 : nullptr;
67986799
67996800 unsigned BytesLeft = SizeVal % UnitSize;
68006801 unsigned LoopSize = SizeVal - BytesLeft;
75857586
75867587 // Look for the glued ADDE.
75877588 SDNode* AddeNode = AddcNode->getGluedUser();
7588 if (AddeNode == NULL)
7589 if (!AddeNode)
75897590 return SDValue();
75907591
75917592 // Make sure it is really an ADDE.
76207621
76217622 // Figure out the high and low input values to the MLAL node.
76227623 SDValue* HiMul = &MULOp;
7623 SDValue* HiAdd = NULL;
7624 SDValue* LoMul = NULL;
7625 SDValue* LowAdd = NULL;
7624 SDValue* HiAdd = nullptr;
7625 SDValue* LoMul = nullptr;
7626 SDValue* LowAdd = nullptr;
76267627
76277628 if (IsLeftOperandMUL)
76287629 HiAdd = &AddeOp1;
76397640 LowAdd = &AddcOp0;
76407641 }
76417642
7642 if (LoMul == NULL)
7643 if (!LoMul)
76437644 return SDValue();
76447645
76457646 if (LoMul->getNode() != HiMul->getNode())
1005710058 Value *CallOperandVal = info.CallOperandVal;
1005810059 // If we don't have a value, we can't do a match,
1005910060 // but allow it at the lowest weight.
10060 if (CallOperandVal == NULL)
10061 if (!CallOperandVal)
1006110062 return CW_Default;
1006210063 Type *type = CallOperandVal->getType();
1006310064 // Look at the constraint type.
1013610137 std::string &Constraint,
1013710138 std::vector&Ops,
1013810139 SelectionDAG &DAG) const {
10139 SDValue Result(0, 0);
10140 SDValue Result;
1014010141
1014110142 // Currently only support length 1 constraints.
1014210143 if (Constraint.length() != 1) return;
17461746 while (Ops.size() > 1) {
17471747 unsigned FirstLoc = ~0U;
17481748 unsigned LastLoc = 0;
1749 MachineInstr *FirstOp = 0;
1750 MachineInstr *LastOp = 0;
1749 MachineInstr *FirstOp = nullptr;
1750 MachineInstr *LastOp = nullptr;
17511751 int LastOffset = 0;
17521752 unsigned LastOpcode = 0;
17531753 unsigned LastBytes = 0;
3030 InitializeELF(isAAPCS_ABI);
3131
3232 if (isAAPCS_ABI) {
33 LSDASection = NULL;
33 LSDASection = nullptr;
3434 }
3535
3636 AttributesSection =
4242 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
4343
4444 public:
45 ARMTTI() : ImmutablePass(ID), TM(0), ST(0), TLI(0) {
45 ARMTTI() : ImmutablePass(ID), TM(nullptr), ST(nullptr), TLI(nullptr) {
4646 llvm_unreachable("This pass cannot be directly constructed");
4747 }
4848
10981098 if (!isMem())
10991099 return false;
11001100 // No offset of any kind.
1101 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
1101 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
11021102 (alignOK || Memory.Alignment == Alignment);
11031103 }
11041104 bool isMemPCRelImm12() const {
17071707
17081708 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
17091709 // Add as immediates when possible. Null MCExpr = 0.
1710 if (Expr == 0)
1710 if (!Expr)
17111711 Inst.addOperand(MCOperand::CreateImm(0));
17121712 else if (const MCConstantExpr *CE = dyn_cast(Expr))
17131713 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
29922992 Parser.getTok().is(AsmToken::Dollar)) {
29932993 Parser.Lex(); // Eat hash.
29942994 SMLoc ImmLoc = Parser.getTok().getLoc();
2995 const MCExpr *ShiftExpr = 0;
2995 const MCExpr *ShiftExpr = nullptr;
29962996 if (getParser().parseExpression(ShiftExpr, EndLoc)) {
29972997 Error(ImmLoc, "invalid immediate shift value");
29982998 return -1;
44904490 E = Tok.getEndLoc();
44914491 Parser.Lex(); // Eat right bracket token.
44924492
4493 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4494 0, 0, false, S, E));
4493 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4494 ARM_AM::no_shift, 0, 0, false,
4495 S, E));
44954496
44964497 // If there's a pre-indexing writeback marker, '!', just add it as a token
44974498 // operand. It's rather odd, but syntactically valid.
45464547
45474548 // Don't worry about range checking the value here. That's handled by
45484549 // the is*() predicates.
4549 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4550 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
45504551 ARM_AM::no_shift, 0, Align,
45514552 false, S, E, AlignmentLoc));
45524553
46394640 E = Parser.getTok().getEndLoc();
46404641 Parser.Lex(); // Eat right bracket token.
46414642
4642 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4643 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
46434644 ShiftType, ShiftImm, 0, isNegative,
46444645 S, E));
46454646
6161 #define ARM_FPU_NAME(NAME, ID) case ARM::ID: return NAME;
6262 #include "ARMFPUName.def"
6363 }
64 return NULL;
64 return nullptr;
6565 }
6666
6767 static const char *GetArchName(unsigned ID) {
7474 #define ARM_ARCH_ALIAS(NAME, ID) /* empty */
7575 #include "ARMArchName.def"
7676 }
77 return NULL;
77 return nullptr;
7878 }
7979
8080 static const char *GetArchDefaultCPUName(unsigned ID) {
8787 #define ARM_ARCH_ALIAS(NAME, ID) /* empty */
8888 #include "ARMArchName.def"
8989 }
90 return NULL;
90 return nullptr;
9191 }
9292
9393 static unsigned GetArchDefaultCPUArch(unsigned ID) {
309309 for (size_t i = 0; i < Contents.size(); ++i)
310310 if (Contents[i].Tag == Attribute)
311311 return &Contents[i];
312 return 0;
312 return nullptr;
313313 }
314314
315315 void setAttributeItem(unsigned Attribute, unsigned Value,
414414 ARMTargetELFStreamer(MCStreamer &S)
415415 : ARMTargetStreamer(S), CurrentVendor("aeabi"), FPU(ARM::INVALID_FPU),
416416 Arch(ARM::INVALID_ARCH), EmittedArch(ARM::INVALID_ARCH),
417 AttributeSection(0) {}
417 AttributeSection(nullptr) {}
418418 };
419419
420420 /// Extend the generic ELFStreamer class so that it can emit mapping symbols at
10121012 }
10131013
10141014 // Get .ARM.extab or .ARM.exidx section
1015 const MCSectionELF *EHSection = NULL;
1015 const MCSectionELF *EHSection = nullptr;
10161016 if (const MCSymbol *Group = FnSection.getGroup()) {
10171017 EHSection = getContext().getELFSection(
10181018 EHSecName, Type, Flags | ELF::SHF_GROUP, Kind,
10491049 }
10501050
10511051 void ARMELFStreamer::Reset() {
1052 ExTab = NULL;
1053 FnStart = NULL;
1054 Personality = NULL;
1052 ExTab = nullptr;
1053 FnStart = nullptr;
1054 Personality = nullptr;
10551055 PersonalityIndex = ARM::EHABI::NUM_PERSONALITY_INDEX;
10561056 FPReg = ARM::SP;
10571057 FPOffset = 0;
2424 (TheTriple.getArch() == Triple::thumbeb))
2525 IsLittleEndian = false;
2626
27 Data64bitsDirective = 0;
27 Data64bitsDirective = nullptr;
2828 CommentString = "@";
2929 Code16Directive = ".code\t16";
3030 Code32Directive = ".code\t32";
4949 // ".comm align is in bytes but .align is pow-2."
5050 AlignmentIsInBytes = false;
5151
52 Data64bitsDirective = 0;
52 Data64bitsDirective = nullptr;
5353 CommentString = "@";
5454 Code16Directive = ".code\t16";
5555 Code32Directive = ".code\t32";
246246 }
247247
248248 unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
249 MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(0, Reg, 0));
249 MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0));
250250
251251 return MAI;
252252 }
296296 const MCSubtargetInfo &STI) {
297297 if (SyntaxVariant == 0)
298298 return new ARMInstPrinter(MAI, MII, MRI, STI);
299 return 0;
299 return nullptr;
300300 }
301301
302302 static MCRelocationInfo *createARMMCRelocationInfo(StringRef TT,
377377 }
378378
379379 // Get the symbol data, if any.
380 const MCSymbolData *SD = 0;
380 const MCSymbolData *SD = nullptr;
381381 if (Target.getSymA())
382382 SD = &Asm.getSymbolData(Target.getSymA()->getSymbol());
383383
108108 AssemblerConstantPools::getConstantPool(const MCSection *Section) {
109109 ConstantPoolMapTy::iterator CP = ConstantPools.find(Section);
110110 if (CP == ConstantPools.end())
111 return 0;
111 return nullptr;
112112
113113 return &CP->second;
114114 }
7373 }
7474
7575 void MLxExpansion::clearStack() {
76 std::fill(LastMIs, LastMIs + 4, (MachineInstr*)0);
76 std::fill(LastMIs, LastMIs + 4, nullptr);
7777 MIIdx = 0;
7878 }
7979
8888 // real definition MI. This is important for _sfp instructions.
8989 unsigned Reg = MI->getOperand(1).getReg();
9090 if (TargetRegisterInfo::isPhysicalRegister(Reg))
91 return 0;
91 return nullptr;
9292
9393 MachineBasicBlock *MBB = MI->getParent();
9494 MachineInstr *DefMI = MRI->getVRegDef(Reg);
352352 if (Domain == ARMII::DomainGeneral) {
353353 if (++Skip == 2)
354354 // Assume dual issues of non-VFP / NEON instructions.
355 pushStack(0);
355 pushStack(nullptr);
356356 } else {
357357 Skip = 0;
358358
915915
916916 // Yes, CPSR could be livein.
917917 bool LiveCPSR = MBB.isLiveIn(ARM::CPSR);
918 MachineInstr *BundleMI = 0;
919
920 CPSRDef = 0;
918 MachineInstr *BundleMI = nullptr;
919
920 CPSRDef = nullptr;
921921 HighLatencyCPSR = false;
922922
923923 // Check predecessors for the latest CPSRDef.
983983 LiveCPSR = UpdateCPSRDef(*MI, LiveCPSR, DefCPSR);
984984 if (MI->isCall()) {
985985 // Calls don't really set CPSR.
986 CPSRDef = 0;
986 CPSRDef = nullptr;
987987 HighLatencyCPSR = false;
988988 IsSelfLoop = false;
989989 } else if (DefCPSR) {
7070 public:
7171 static char ID;
7272 ARM64AddressTypePromotion()
73 : FunctionPass(ID), Func(NULL), ConsideredSExtType(NULL) {
73 : FunctionPass(ID), Func(nullptr), ConsideredSExtType(nullptr) {
7474 initializeARM64AddressTypePromotionPass(*PassRegistry::getPassRegistry());
7575 }
7676
343343 SExtForOpnd->moveBefore(Inst);
344344 Inst->setOperand(OpIdx, SExtForOpnd);
345345 // If more sext are required, new instructions will have to be created.
346 SExtForOpnd = NULL;
346 SExtForOpnd = nullptr;
347347 }
348348 if (SExtForOpnd == SExt) {
349349 DEBUG(dbgs() << "Sign extension is useless now\n");
465465 if (insert || AlreadySeen != SeenChains.end()) {
466466 DEBUG(dbgs() << "Insert\n");
467467 SExtInsts.push_back(SExt);
468 if (AlreadySeen != SeenChains.end() && AlreadySeen->second != NULL) {
468 if (AlreadySeen != SeenChains.end() && AlreadySeen->second != nullptr) {
469469 DEBUG(dbgs() << "Insert chain member\n");
470470 SExtInsts.push_back(AlreadySeen->second);
471 SeenChains[Last] = NULL;
471 SeenChains[Last] = nullptr;
472472 }
473473 } else {
474474 DEBUG(dbgs() << "Record its chain membership\n");
5252 public:
5353 ARM64AsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
5454 : AsmPrinter(TM, Streamer), Subtarget(&TM.getSubtarget()),
55 MCInstLowering(OutContext, *Mang, *this), SM(*this), ARM64FI(NULL),
55 MCInstLowering(OutContext, *Mang, *this), SM(*this), ARM64FI(nullptr),
5656 LOHLabelCounter(0) {}
5757
5858 virtual const char *getPassName() const { return "ARM64 Assembly Printer"; }
261261 InstrToInstrs::const_iterator Res = sets[reg].find(&MI);
262262 if (Res != sets[reg].end())
263263 return &(Res->second);
264 return NULL;
264 return nullptr;
265265 }
266266
267267 /// Initialize the reaching definition algorithm:
334334 // Do not register clobbered definition for no ADRP.
335335 // This definition is not used anyway (otherwise register
336336 // allocation is wrong).
337 BBGen[Reg] = ADRPMode ? &MI : NULL;
337 BBGen[Reg] = ADRPMode ? &MI : nullptr;
338338 BBKillSet.set(Reg);
339339 }
340340 }
450450 static void reachingDef(MachineFunction &MF,
451451 InstrToInstrs *ColorOpToReachedUses,
452452 const MapRegToId &RegToId, bool ADRPMode = false,
453 const MachineInstr *DummyOp = NULL) {
453 const MachineInstr *DummyOp = nullptr) {
454454 // structures:
455455 // For each basic block.
456456 // Out: a set per color of definitions that reach the
783783 const InstrToInstrs *DefsPerColorToUses,
784784 ARM64FunctionInfo &ARM64FI, const MapRegToId &RegToId,
785785 const MachineDominatorTree *MDT) {
786 SetOfMachineInstr *InvolvedInLOHs = NULL;
786 SetOfMachineInstr *InvolvedInLOHs = nullptr;
787787 #ifdef DEBUG
788788 SetOfMachineInstr InvolvedInLOHsStorage;
789789 InvolvedInLOHs = &InvolvedInLOHsStorage;
836836 const MachineInstr *Def = *UseToDefs.find(Candidate)->second.begin();
837837 // Record the elements of the chain.
838838 const MachineInstr *L1 = Def;
839 const MachineInstr *L2 = NULL;
839 const MachineInstr *L2 = nullptr;
840840 unsigned ImmediateDefOpc = Def->getOpcode();
841841 if (Def->getOpcode() != ARM64::ADRP) {
842842 // Check the number of users of this node.
906906 SmallVector Args;
907907 MCLOHType Kind;
908908 if (isCandidateLoad(Candidate)) {
909 if (L2 == NULL) {
909 if (!L2) {
910910 // At this point, the candidate LOH indicates that the ldr instruction
911911 // may use a direct access to the symbol. There is not such encoding
912912 // for loads of byte and half.
10561056 if (RegToId.empty())
10571057 return false;
10581058
1059 MachineInstr *DummyOp = NULL;
1059 MachineInstr *DummyOp = nullptr;
10601060 if (BasicBlockScopeOnly) {
10611061 const ARM64InstrInfo *TII =
10621062 static_cast(TM.getInstrInfo());
297297 MachineInstr *SSACCmpConv::findConvertibleCompare(MachineBasicBlock *MBB) {
298298 MachineBasicBlock::iterator I = MBB->getFirstTerminator();
299299 if (I == MBB->end())
300 return 0;
300 return nullptr;
301301 // The terminator must be controlled by the flags.
302302 if (!I->readsRegister(ARM64::CPSR)) {
303303 switch (I->getOpcode()) {
310310 }
311311 ++NumCmpTermRejs;
312312 DEBUG(dbgs() << "Flags not used by terminator: " << *I);
313 return 0;
313 return nullptr;
314314 }
315315
316316 // Now find the instruction controlling the terminator.
329329 if (I->getOperand(3).getImm() || !isUInt<5>(I->getOperand(2).getImm())) {
330330 DEBUG(dbgs() << "Immediate out of range for ccmp: " << *I);
331331 ++NumImmRangeRejs;
332 return 0;
332 return nullptr;
333333 }
334334 // Fall through.
335335 case ARM64::SUBSWrr:
340340 return I;
341341 DEBUG(dbgs() << "Can't convert compare with live destination: " << *I);
342342 ++NumLiveDstRejs;
343 return 0;
343 return nullptr;
344344 case ARM64::FCMPSrr:
345345 case ARM64::FCMPDrr:
346346 case ARM64::FCMPESrr:
358358 // besides the terminators.
359359 DEBUG(dbgs() << "Can't create ccmp with multiple uses: " << *I);
360360 ++NumMultCPSRUses;
361 return 0;
361 return nullptr;
362362 }
363363
364364 if (PRI.Clobbers) {
365365 DEBUG(dbgs() << "Not convertible compare: " << *I);
366366 ++NumUnknCPSRDefs;
367 return 0;
367 return nullptr;
368368 }
369369 }
370370 DEBUG(dbgs() << "Flags not defined in BB#" << MBB->getNumber() << '\n');
371 return 0;
371 return nullptr;
372372 }
373373
374374 /// Determine if all the instructions in MBB can safely
415415
416416 // We never speculate stores, so an AA pointer isn't necessary.
417417 bool DontMoveAcrossStore = true;
418 if (!I.isSafeToMove(TII, 0, DontMoveAcrossStore)) {
418 if (!I.isSafeToMove(TII, nullptr, DontMoveAcrossStore)) {
419419 DEBUG(dbgs() << "Can't speculate: " << I);
420420 return false;
421421 }
434434 ///
435435 bool SSACCmpConv::canConvert(MachineBasicBlock *MBB) {
436436 Head = MBB;
437 Tail = CmpBB = 0;
437 Tail = CmpBB = nullptr;
438438
439439 if (Head->succ_size() != 2)
440440 return false;
494494
495495 // The branch we're looking to eliminate must be analyzable.
496496 HeadCond.clear();
497 MachineBasicBlock *TBB = 0, *FBB = 0;
497 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
498498 if (TII->AnalyzeBranch(*Head, TBB, FBB, HeadCond)) {
499499 DEBUG(dbgs() << "Head branch not analyzable.\n");
500500 ++NumHeadBranchRejs;
522522 }
523523
524524 CmpBBCond.clear();
525 TBB = FBB = 0;
525 TBB = FBB = nullptr;
526526 if (TII->AnalyzeBranch(*CmpBB, TBB, FBB, CmpBBCond)) {
527527 DEBUG(dbgs() << "CmpBB branch not analyzable.\n");
528528 ++NumCmpBranchRejs;
896896 DomTree = &getAnalysis();
897897 Loops = getAnalysisIfAvailable();
898898 Traces = &getAnalysis();
899 MinInstr = 0;
899 MinInstr = nullptr;
900900 MinSize = MF.getFunction()->getAttributes().hasAttribute(
901901 AttributeSet::FunctionIndex, Attribute::MinSize);
902902
302302
303303 // Computes the address to get to an object.
304304 bool ARM64FastISel::ComputeAddress(const Value *Obj, Address &Addr) {
305 const User *U = NULL;
305 const User *U = nullptr;
306306 unsigned Opcode = Instruction::UserOp1;
307307 if (const Instruction *I = dyn_cast(Obj)) {
308308 // Don't walk into other basic blocks unless the object is an alloca from
12801280 }
12811281
12821282 bool ARM64FastISel::SelectCall(const Instruction *I,
1283 const char *IntrMemName = 0) {
1283 const char *IntrMemName = nullptr) {
12841284 const CallInst *CI = cast(I);
12851285 const Value *Callee = CI->getCalledValue();
12861286
453453 if (Op1.getOpcode() != ISD::MUL ||
454454 !checkV64LaneV128(Op1.getOperand(0), Op1.getOperand(1), MLAOp1, MLAOp2,
455455 LaneIdx))
456 return 0;
456 return nullptr;
457457 }
458458
459459 SDValue LaneIdxVal = CurDAG->getTargetConstant(LaneIdx, MVT::i64);
489489
490490 if (!checkV64LaneV128(N->getOperand(1), N->getOperand(2), SMULLOp0, SMULLOp1,
491491 LaneIdx))
492 return 0;
492 return nullptr;
493493
494494 SDValue LaneIdxVal = CurDAG->getTargetConstant(LaneIdx, MVT::i64);
495495
851851 SDNode *ARM64DAGToDAGISel::SelectIndexedLoad(SDNode *N, bool &Done) {
852852 LoadSDNode *LD = cast(N);
853853 if (LD->isUnindexed())
854 return NULL;
854 return nullptr;
855855 EVT VT = LD->getMemoryVT();
856856 EVT DstVT = N->getValueType(0);
857857 ISD::MemIndexedMode AM = LD->getAddressingMode();
909909 } else if (VT == MVT::f64) {
910910 Opcode = IsPre ? ARM64::LDRDpre_isel : ARM64::LDRDpost_isel;
911911 } else
912 return NULL;
912 return nullptr;
913913 SDValue Chain = LD->getChain();
914914 SDValue Base = LD->getBasePtr();
915915 ConstantSDNode *OffsetOp = cast(LD->getOffset());
928928 ReplaceUses(SDValue(N, 0), SDValue(Sub, 0));
929929 ReplaceUses(SDValue(N, 1), SDValue(Res, 1));
930930 ReplaceUses(SDValue(N, 2), SDValue(Res, 2));
931 return 0;
931 return nullptr;
932932 }
933933 return Res;
934934 }
976976
977977 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));
978978
979 return 0;
979 return nullptr;
980980 }
981981
982982 SDNode *ARM64DAGToDAGISel::SelectStore(SDNode *N, unsigned NumVecs,
13701370 unsigned Opc, LSB, MSB;
13711371 SDValue Opd0;
13721372 if (!isBitfieldExtractOp(CurDAG, N, Opc, Opd0, LSB, MSB))
1373 return NULL;
1373 return nullptr;
13741374
13751375 EVT VT = N->getValueType(0);
13761376
17661766
17671767 SDNode *ARM64DAGToDAGISel::SelectBitfieldInsertOp(SDNode *N) {
17681768 if (N->getOpcode() != ISD::OR)
1769 return NULL;
1769 return nullptr;
17701770
17711771 unsigned Opc;
17721772 unsigned LSB, MSB;
17731773 SDValue Opd0, Opd1;
17741774
17751775 if (!isBitfieldInsertOpFromOr(N, Opc, Opd0, Opd1, LSB, MSB, CurDAG))
1776 return NULL;
1776 return nullptr;
17771777
17781778 EVT VT = N->getValueType(0);
17791779 SDValue Ops[] = { Opd0,
17941794 } else if (VT == MVT::f64) {
17951795 Variant = 1;
17961796 } else
1797 return 0; // Unrecognized argument type. Fall back on default codegen.
1797 return nullptr; // Unrecognized argument type. Fall back on default codegen.
17981798
17991799 // Pick the FRINTX variant needed to set the flags.
18001800 unsigned FRINTXOpc = FRINTXOpcs[Variant];
18011801
18021802 switch (N->getOpcode()) {
18031803 default:
1804 return 0; // Unrecognized libm ISD node. Fall back on default codegen.
1804 return nullptr; // Unrecognized libm ISD node. Fall back on default codegen.
18051805 case ISD::FCEIL: {
18061806 unsigned FRINTPOpcs[] = { ARM64::FRINTPSr, ARM64::FRINTPDr };
18071807 Opc = FRINTPOpcs[Variant];
18911891 if (Node->isMachineOpcode()) {
18921892 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
18931893 Node->setNodeId(-1);
1894 return NULL;
1894 return nullptr;
18951895 }
18961896
18971897 // Few custom selection stuff.
1898 SDNode *ResNode = 0;
1898 SDNode *ResNode = nullptr;
18991899 EVT VT = Node->getValueType(0);
19001900
19011901 switch (Node->getOpcode()) {
24542454 ResNode = SelectCode(Node);
24552455
24562456 DEBUG(errs() << "=> ");
2457 if (ResNode == NULL || ResNode == Node)
2457 if (ResNode == nullptr || ResNode == Node)
24582458 DEBUG(Node->dump(CurDAG));
24592459 else
24602460 DEBUG(ResNode->dump(CurDAG));
618618 const char *ARM64TargetLowering::getTargetNodeName(unsigned Opcode) const {
619619 switch (Opcode) {
620620 default:
621 return 0;
621 return nullptr;
622622 case ARM64ISD::CALL: return "ARM64ISD::CALL";
623623 case ARM64ISD::ADRP: return "ARM64ISD::ADRP";
624624 case ARM64ISD::ADDlow: return "ARM64ISD::ADDlow";
25642564
25652565 // If softenSetCCOperands returned a scalar, we need to compare the result
25662566 // against zero to select between true and false values.
2567 if (RHS.getNode() == 0) {
2567 if (!RHS.getNode()) {
25682568 RHS = DAG.getConstant(0, LHS.getValueType());
25692569 CC = ISD::SETNE;
25702570 }
28142814 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
28152815
28162816 // If softenSetCCOperands returned a scalar, use it.
2817 if (RHS.getNode() == 0) {
2817 if (!RHS.getNode()) {
28182818 assert(LHS.getValueType() == Op.getValueType() &&
28192819 "Unexpected setcc expansion!");
28202820 return LHS;
29382938
29392939 // If softenSetCCOperands returned a scalar, we need to compare the result
29402940 // against zero to select between true and false values.
2941 if (RHS.getNode() == 0) {
2941 if (!RHS.getNode()) {
29422942 RHS = DAG.getConstant(0, LHS.getValueType());
29432943 CC = ISD::SETNE;
29442944 }
35623562 Value *CallOperandVal = info.CallOperandVal;
35633563 // If we don't have a value, we can't do a match,
35643564 // but allow it at the lowest weight.
3565 if (CallOperandVal == NULL)
3565 if (!CallOperandVal)
35663566 return CW_Default;
35673567 Type *type = CallOperandVal->getType();
35683568 // Look at the constraint type.
36163616 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
36173617
36183618 // Not found as a standard register?
3619 if (Res.second == 0) {
3619 if (!Res.second) {
36203620 unsigned Size = Constraint.size();
36213621 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
36223622 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
36413641 void ARM64TargetLowering::LowerAsmOperandForConstraint(
36423642 SDValue Op, std::string &Constraint, std::vector &Ops,
36433643 SelectionDAG &DAG) const {
3644 SDValue Result(0, 0);
3644 SDValue Result;
36453645
36463646 // Currently only support length 1 constraints.
36473647 if (Constraint.length() != 1)
259259 // Shouldn't be a fall through.
260260 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
261261
262 if (FBB == 0) {
262 if (!FBB) {
263263 if (Cond.empty()) // Unconditional branch?
264264 BuildMI(&MBB, DL, get(ARM64::B)).addMBB(TBB);
265265 else
288288 // csel instruction. If so, return the folded opcode, and the replacement
289289 // register.
290290 static unsigned canFoldIntoCSel(const MachineRegisterInfo &MRI, unsigned VReg,
291 unsigned *NewVReg = 0) {
291 unsigned *NewVReg = nullptr) {
292292 VReg = removeCopies(MRI, VReg);
293293 if (!TargetRegisterInfo::isVirtualRegister(VReg))
294294 return 0;
468468 }
469469
470470 unsigned Opc = 0;
471 const TargetRegisterClass *RC = 0;
471 const TargetRegisterClass *RC = nullptr;
472472 bool TryFold = false;
473473 if (MRI.constrainRegClass(DstReg, &ARM64::GPR64RegClass)) {
474474 RC = &ARM64::GPR64RegClass;
16661666 unsigned SrcReg = MI->getOperand(1).getReg();
16671667 if (SrcReg == ARM64::SP && TargetRegisterInfo::isVirtualRegister(DstReg)) {
16681668 MF.getRegInfo().constrainRegClass(DstReg, &ARM64::GPR64RegClass);
1669 return 0;
1669 return nullptr;
16701670 }
16711671 if (DstReg == ARM64::SP && TargetRegisterInfo::isVirtualRegister(SrcReg)) {
16721672 MF.getRegInfo().constrainRegClass(SrcReg, &ARM64::GPR64RegClass);
1673 return 0;
1673 return nullptr;
16741674 }
16751675 }
16761676
16771677 // Cannot fold.
1678 return 0;
1678 return nullptr;
16791679 }
16801680
16811681 int llvm::isARM64FrameOffsetLegal(const MachineInstr &MI, int &Offset,
488488 ModuleToMergedGV.find(M);
489489 if (MapIt == ModuleToMergedGV.end()) {
490490 PromotedGV = new GlobalVariable(
491 *M, Cst->getType(), true, GlobalValue::InternalLinkage, 0,
492 "_PromotedConst", 0, GlobalVariable::NotThreadLocal);
491 *M, Cst->getType(), true, GlobalValue::InternalLinkage, nullptr,
492 "_PromotedConst", nullptr, GlobalVariable::NotThreadLocal);
493493 PromotedGV->setInitializer(Cst);
494494 ModuleToMergedGV[M] = PromotedGV;
495495 DEBUG(dbgs() << "Global replacement: ");
135135 const TargetRegisterClass *
136136 ARM64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
137137 if (RC == &ARM64::CCRRegClass)
138 return NULL; // Can't copy CPSR.
138 return nullptr; // Can't copy CPSR.
139139 return RC;
140140 }
141141
2929 ConstantSDNode *V = dyn_cast(Src);
3030 ConstantSDNode *SizeValue = dyn_cast(Size);
3131 const char *bzeroEntry =
32 (V && V->isNullValue()) ? Subtarget->getBZeroEntry() : 0;
32 (V && V->isNullValue()) ? Subtarget->getBZeroEntry() : nullptr;
3333 // For small size (< 256), it is not beneficial to use bzero
3434 // instead of memset.
3535 if (bzeroEntry && (!SizeValue || SizeValue->getZExtValue() > 256)) {
125125 SchedModel.init(*ST.getSchedModel(), &ST, TII);
126126
127127 Traces = &getAnalysis();
128 MinInstr = 0;
128 MinInstr = nullptr;
129129
130130 DEBUG(dbgs() << "*** " << getPassName() << ": " << MF->getName() << '\n');
131131
4444 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
4545
4646 public:
47 ARM64TTI() : ImmutablePass(ID), TM(0), ST(0), TLI(0) {
47 ARM64TTI() : ImmutablePass(ID), TM(nullptr), ST(nullptr), TLI(nullptr) {
4848 llvm_unreachable("This pass cannot be directly constructed");
4949 }
5050
963963 return false;
964964 if (Mem.Mode != ImmediateOffset)
965965 return false;
966 return Mem.OffsetImm == 0;
966 return Mem.OffsetImm == nullptr;
967967 }
968968 bool isMemoryIndexedSImm9() const {
969969 if (!isMem() || Mem.Mode != ImmediateOffset)
10401040
10411041 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
10421042 // Add as immediates when possible. Null MCExpr = 0.
1043 if (Expr == 0)
1043 if (!Expr)
10441044 Inst.addOperand(MCOperand::CreateImm(0));
10451045 else if (const MCConstantExpr *CE = dyn_cast(Expr))
10461046 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
16871687 ARM64Operand *Op = new ARM64Operand(k_Memory, Ctx);
16881688 Op->Mem.BaseRegNum = BaseReg;
16891689 Op->Mem.OffsetRegNum = OffsetReg;
1690 Op->Mem.OffsetImm = 0;
1690 Op->Mem.OffsetImm = nullptr;
16911691 Op->Mem.ExtType = ExtType;
16921692 Op->Mem.ShiftVal = ShiftVal;
16931693 Op->Mem.ExplicitShift = ExplicitShift;
23782378 StringRef Op = Tok.getString();
23792379 SMLoc S = Tok.getLoc();
23802380
2381 const MCExpr *Expr = 0;
2381 const MCExpr *Expr = nullptr;
23822382
23832383 #define SYS_ALIAS(op1, Cn, Cm, op2) \
23842384 do { \
27982798
27992799 Parser.Lex(); // Eat right bracket token.
28002800
2801 Operands.push_back(ARM64Operand::CreateMem(Reg, 0, S, E, E, getContext()));
2801 Operands.push_back(ARM64Operand::CreateMem(Reg, nullptr, S, E, E, getContext()));
28022802 return MatchOperand_Success;
28032803 }
28042804
28172817 return Error(BaseRegTok.getLoc(), "register expected");
28182818
28192819 // If there is an offset expression, parse it.
2820 const MCExpr *OffsetExpr = 0;
2820 const MCExpr *OffsetExpr = nullptr;
28212821 SMLoc OffsetLoc;
28222822 if (Parser.getTok().is(AsmToken::Comma)) {
28232823 Parser.Lex(); // Eat the comma.
38473847 const char *Repl = StringSwitch(Tok)
38483848 .Case("cmp", "subs")
38493849 .Case("cmn", "adds")
3850 .Default(0);
3850 .Default(nullptr);
38513851 assert(Repl && "Unknown compare instruction");
38523852 delete Operands[0];
38533853 Operands[0] = ARM64Operand::CreateToken(Repl, false, IDLoc, getContext());
166166 }
167167 }
168168
169 const MCExpr *Add = NULL;
169 const MCExpr *Add = nullptr;
170170 if (SymbolicOp.AddSymbol.Present) {
171171 if (SymbolicOp.AddSymbol.Name) {
172172 StringRef Name(SymbolicOp.AddSymbol.Name);
181181 }
182182 }
183183
184 const MCExpr *Sub = NULL;
184 const MCExpr *Sub = nullptr;
185185 if (SymbolicOp.SubtractSymbol.Present) {
186186 if (SymbolicOp.SubtractSymbol.Name) {
187187 StringRef Name(SymbolicOp.SubtractSymbol.Name);
192192 }
193193 }
194194
195 const MCExpr *Off = NULL;
195 const MCExpr *Off = nullptr;
196196 if (SymbolicOp.Value != 0)
197197 Off = MCConstantExpr::Create(SymbolicOp.Value, Ctx);
198198
203203 LHS = MCBinaryExpr::CreateSub(Add, Sub, Ctx);
204204 else
205205 LHS = MCUnaryExpr::CreateMinus(Sub, Ctx);
206 if (Off != 0)
206 if (Off)
207207 Expr = MCBinaryExpr::CreateAdd(LHS, Off, Ctx);
208208 else
209209 Expr = LHS;
210210 } else if (Add) {
211 if (Off != 0)
211 if (Off)
212212 Expr = MCBinaryExpr::CreateAdd(Add, Off, Ctx);
213213 else
214214 Expr = Add;
215215 } else {
216 if (Off != 0)
216 if (Off)
217217 Expr = Off;
218218 else
219219 Expr = MCConstantExpr::Create(0, Ctx);
8484
8585 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
8686 bool IsSigned = (Opcode == ARM64::SBFMXri || Opcode == ARM64::SBFMWri);
87 const char *AsmMnemonic = 0;
87 const char *AsmMnemonic = nullptr;
8888
8989 switch (Op3.getImm()) {
9090 default:
114114 // instruction. In all cases the immediate shift amount shift must be in
115115 // the range 0 to (reg.size -1).
116116 if (Op2.isImm() && Op3.isImm()) {
117 const char *AsmMnemonic = 0;
117 const char *AsmMnemonic = nullptr;
118118 int shift = 0;
119119 int64_t immr = Op2.getImm();
120120 int64_t imms = Op3.getImm();
692692 if (LdStNInstInfo[Idx].Opcode == Opcode)
693693 return &LdStNInstInfo[Idx];
694694
695 return 0;
695 return nullptr;
696696 }
697697
698698 void ARM64AppleInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
753753 assert(Opcode == ARM64::SYSxt && "Invalid opcode for SYS alias!");
754754 #endif
755755
756 const char *Asm = 0;
756 const char *Asm = nullptr;
757757 const MCOperand &Op1 = MI->getOperand(0);
758758 const MCOperand &Cn = MI->getOperand(1);
759759 const MCOperand &Cm = MI->getOperand(2);
967967 O << ", " << getRegisterName(Reg);
968968 }
969969
970 return Asm != 0;
970 return Asm != nullptr;
971971 }
972972
973973 void ARM64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
7070
7171 // Initial state of the frame pointer is SP.
7272 unsigned Reg = MRI.getDwarfRegNum(ARM64::SP, true);
73 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(0, Reg, 0);
73 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
7474 MAI->addInitialFrameState(Inst);
7575
7676 return MAI;
118118 if (SyntaxVariant == 1)
119119 return new ARM64AppleInstPrinter(MAI, MII, MRI, STI);
120120
121 return 0;
121 return nullptr;
122122 }
123123
124124 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
240240 Asm.getContext().FatalError(Fixup.getLoc(),
241241 "unsupported relocation with identical base");
242242
243 Value += (A_SD.getFragment() == NULL ? 0 : Writer->getSymbolAddress(
244 &A_SD, Layout)) -
245 (A_Base == NULL || A_Base->getFragment() == NULL
243 Value += (!A_SD.getFragment() ? 0
244 : Writer->getSymbolAddress(&A_SD, Layout)) -
245 (!A_Base || !A_Base->getFragment()
246246 ? 0
247247 : Writer->getSymbolAddress(A_Base, Layout));
248 Value -= (B_SD.getFragment() == NULL ? 0 : Writer->getSymbolAddress(
249 &B_SD, Layout)) -
250 (B_Base == NULL || B_Base->getFragment() == NULL
248 Value -= (!B_SD.getFragment() ? 0
249 : Writer->getSymbolAddress(&B_SD, Layout)) -
250 (!B_Base || !B_Base->getFragment()
251251 ? 0
252252 : Writer->getSymbolAddress(B_Base, Layout));
253253
301301 // have already been fixed up.
302302 if (Symbol->isInSection()) {
303303 if (Section.hasAttribute(MachO::S_ATTR_DEBUG))
304 Base = 0;
304 Base = nullptr;
305305 }
306306
307307 // ARM64 uses external relocations as much as possible. For debug sections,
395395 return I->second;
396396
397397 // Okay, let's build a new name for this type. Start with a prefix
398 const char* prefix = 0;
398 const char* prefix = nullptr;
399399 switch (Ty->getTypeID()) {
400400 case Type::FunctionTyID: prefix = "FuncTy_"; break;
401401 case Type::StructTyID: prefix = "StructTy_"; break;
224224 if (SyntaxVariant == 0)
225225 return(new HexagonInstPrinter(MAI, MII, MRI));
226226 else
227 return NULL;
227 return nullptr;
228228 }
229229
230230 extern "C" void LLVMInitializeHexagonAsmPrinter() {
146146 MachineBasicBlock::succ_iterator SI = MBB->succ_begin();
147147 MachineBasicBlock* FirstSucc = *SI;
148148 MachineBasicBlock* SecondSucc = *(++SI);
149 MachineBasicBlock* LayoutSucc = NULL;
150 MachineBasicBlock* JumpAroundTarget = NULL;
149 MachineBasicBlock* LayoutSucc = nullptr;
150 MachineBasicBlock* JumpAroundTarget = nullptr;
151151
152152 if (MBB->isLayoutSuccessor(FirstSucc)) {
153153 LayoutSucc = FirstSucc;
161161
162162 // The target of the unconditional branch must be JumpAroundTarget.
163163 // TODO: If not, we should not invert the unconditional branch.
164 MachineBasicBlock* CondBranchTarget = NULL;
164 MachineBasicBlock* CondBranchTarget = nullptr;
165165 if ((MI->getOpcode() == Hexagon::JMP_t) ||
166166 (MI->getOpcode() == Hexagon::JMP_f)) {
167167 CondBranchTarget = MI->getOperand(1).getMBB();
239239
240240 static void initializePassOnce(PassRegistry &Registry) {
241241 PassInfo *PI = new PassInfo("Hexagon CFG Optimizer", "hexagon-cfg",
242 &HexagonCFGOptimizer::ID, 0, false, false);
242 &HexagonCFGOptimizer::ID, nullptr, false, false);
243243 Registry.registerPass(*PI, true);
244244 }
245245
261261 unsigned KilledOperand = 0;
262262 if (I2->killsRegister(I2UseReg))
263263 KilledOperand = I2UseReg;
264 MachineInstr *KillingInstr = 0;
264 MachineInstr *KillingInstr = nullptr;
265265
266266 for (; I != End; ++I) {
267267 // If the intervening instruction I:
305305 // Track killed operands. If we move across an instruction that kills our
306306 // operand, we need to update the kill information on the moved I1. It kills
307307 // the operand now.
308 MachineInstr *KillingInstr = 0;
308 MachineInstr *KillingInstr = nullptr;
309309 unsigned KilledOperand = 0;
310310
311311 while(++I != End) {
505505 // Not safe. Stop searching.
506506 break;
507507 }
508 return 0;
508 return nullptr;
509509 }
510510
511511 void HexagonCopyToCombine::combine(MachineInstr *I1, MachineInstr *I2,
186186 const char *Name = "Hexagon Expand Predicate Spill Code";
187187 PassInfo *PI = new PassInfo(Name, "hexagon-spill-pred",
188188 &HexagonExpandPredSpillCode::ID,
189 0, false, false);
189 nullptr, false, false);
190190 Registry.registerPass(*PI, true);
191191 }
192192
245245 //
246246 unsigned SuperReg = uniqueSuperReg(Reg, TRI);
247247 bool CanUseDblStore = false;
248 const TargetRegisterClass* SuperRegClass = 0;
248 const TargetRegisterClass* SuperRegClass = nullptr;
249249
250250 if (ContiguousRegs && (i < CSI.size()-1)) {
251251 unsigned SuperRegNext = uniqueSuperReg(CSI[i+1].getReg(), TRI);
299299 // Check if we can use a double-word load.
300300 //
301301 unsigned SuperReg = uniqueSuperReg(Reg, TRI);
302 const TargetRegisterClass* SuperRegClass = 0;
302 const TargetRegisterClass* SuperRegClass = nullptr;
303303 bool CanUseDblLoad = false;
304304 if (ContiguousRegs && (i < CSI.size()-1)) {
305305 unsigned SuperRegNext = uniqueSuperReg(CSI[i+1].getReg(), TRI);
264264 return Contents.ImmVal;
265265 }
266266
267 void print(raw_ostream &OS, const TargetMachine *TM = 0) const {
268 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
267 void print(raw_ostream &OS, const TargetMachine *TM = nullptr) const {
268 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : nullptr;
269269 if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); }
270270 if (isImm()) { OS << Contents.ImmVal; }
271271 }
369369 } // for (instr)
370370
371371 SmallVector Cond;
372 MachineBasicBlock *TB = 0, *FB = 0;
372 MachineBasicBlock *TB = nullptr, *FB = nullptr;
373373 bool NotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Cond, false);
374374 if (NotAnalyzed)
375375 return false;
434434 "Loop must have more than one incoming edge!");
435435 MachineBasicBlock *Backedge = *PI++;
436436 if (PI == TopMBB->pred_end()) // dead loop?
437 return 0;
437 return nullptr;
438438 MachineBasicBlock *Incoming = *PI++;
439439 if (PI != TopMBB->pred_end()) // multiple backedges?
440 return 0;
440 return nullptr;
441441
442442 // Make sure there is one incoming and one backedge and determine which
443443 // is which.
444444 if (L->contains(Incoming)) {
445445 if (L->contains(Backedge))
446 return 0;
446 return nullptr;
447447 std::swap(Incoming, Backedge);
448448 } else if (!L->contains(Backedge))
449 return 0;
449 return nullptr;
450450
451451 // Look for the cmp instruction to determine if we can get a useful trip
452452 // count. The trip count can be either a register or an immediate. The
453453 // location of the value depends upon the type (reg or imm).
454454 MachineBasicBlock *Latch = L->getLoopLatch();
455455 if (!Latch)
456 return 0;
456 return nullptr;
457457
458458 unsigned IVReg = 0;
459459 int64_t IVBump = 0;
460460 MachineInstr *IVOp;
461461 bool FoundIV = findInductionRegister(L, IVReg, IVBump, IVOp);
462462 if (!FoundIV)
463 return 0;
463 return nullptr;
464464
465465 MachineBasicBlock *Preheader = L->getLoopPreheader();
466466
467 MachineOperand *InitialValue = 0;
467 MachineOperand *InitialValue = nullptr;
468468 MachineInstr *IV_Phi = MRI->getVRegDef(IVReg);
469469 for (unsigned i = 1, n = IV_Phi->getNumOperands(); i < n; i += 2) {
470470 MachineBasicBlock *MBB = IV_Phi->getOperand(i+1).getMBB();
474474 IVReg = IV_Phi->getOperand(i).getReg(); // Want IV reg after bump.
475475 }
476476 if (!InitialValue)
477 return 0;
477 return nullptr;
478478
479479 SmallVector Cond;
480 MachineBasicBlock *TB = 0, *FB = 0;
480 MachineBasicBlock *TB = nullptr, *FB = nullptr;
481481 bool NotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Cond, false);
482482 if (NotAnalyzed)
483 return 0;
483 return nullptr;
484484
485485 MachineBasicBlock *Header = L->getHeader();
486486 // TB must be non-null. If FB is also non-null, one of them must be
489489 assert (TB && "Latch block without a branch?");
490490 assert ((!FB || TB == Header || FB == Header) && "Branches not to header?");
491491 if (!TB || (FB && TB != Header && FB != Header))
492 return 0;
492 return nullptr;
493493
494494 // Branches of form "if (!P) ..." cause HexagonInstrInfo::AnalyzeBranch
495495 // to put imm(0), followed by P in the vector Cond.
505505 bool AnalyzedCmp = TII->analyzeCompare(CondI, CmpReg1, CmpReg2,
506506 Mask, ImmValue);
507507 if (!AnalyzedCmp)
508 return 0;
508 return nullptr;
509509
510510 // The comparison operator type determines how we compute the loop
511511 // trip count.
521521 bool isSwapped = false;
522522 const MachineOperand &Op1 = CondI->getOperand(1);
523523 const MachineOperand &Op2 = CondI->getOperand(2);
524 const MachineOperand *EndValue = 0;
524 const MachineOperand *EndValue = nullptr;
525525
526526 if (Op1.isReg()) {
527527 if (Op2.isImm() || Op1.getReg() == IVReg)
533533 }
534534
535535 if (!EndValue)
536 return 0;
536 return nullptr;
537537
538538 switch (CondOpc) {
539539 case Hexagon::CMPEQri:
552552 case Hexagon::CMPbEQri_V4:
553553 case Hexagon::CMPhEQri_V4: {
554554 if (IVBump != 1)
555 return 0;
555 return nullptr;
556556
557557 int64_t InitV, EndV;
558558 // Since the comparisons are "ri", the EndValue should be an
562562 // Allow InitialValue to be a register defined with an immediate.
563563 if (InitialValue->isReg()) {
564564 if (!defWithImmediate(InitialValue->getReg()))
565 return 0;
565 return nullptr;
566566 InitV = getImmediate(*InitialValue);
567567 } else {
568568 assert(InitialValue->isImm());
569569 InitV = InitialValue->getImm();
570570 }
571571 if (InitV >= EndV)
572 return 0;
572 return nullptr;
573573 if (CondOpc == Hexagon::CMPbEQri_V4) {
574574 if (!isInt<8>(InitV) || !isInt<8>(EndV))
575 return 0;
575 return nullptr;
576576 } else { // Hexagon::CMPhEQri_V4
577577 if (!isInt<16>(InitV) || !isInt<16>(EndV))
578 return 0;
578 return nullptr;
579579 }
580580 Cmp = !Negated ? Comparison::EQ : Comparison::NE;
581581 break;
582582 }
583583 default:
584 return 0;
584 return nullptr;
585585 }
586586
587587 if (isSwapped)
591591 unsigned R = InitialValue->getReg();
592592 MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent();
593593 if (!MDT->properlyDominates(DefBB, Header))
594 return 0;
594 return nullptr;
595595 OldInsts.push_back(MRI->getVRegDef(R));
596596 }
597597 if (EndValue->isReg()) {
598598 unsigned R = EndValue->getReg();
599599 MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent();
600600 if (!MDT->properlyDominates(DefBB, Header))
601 return 0;
601 return nullptr;
602602 }
603603
604604 return computeCount(L, InitialValue, EndValue, IVReg, IVBump, Cmp);
616616 Comparison::Kind Cmp) const {
617617 // Cannot handle comparison EQ, i.e. while (A == B).
618618 if (Cmp == Comparison::EQ)
619 return 0;
619 return nullptr;
620620
621621 // Check if either the start or end values are an assignment of an immediate.
622622 // If so, use the immediate value rather than the register.
642642 // If loop executes while iv is "less" with the iv value going down, then
643643 // the iv must wrap.
644644 if (CmpLess && IVBump < 0)
645 return 0;
645 return nullptr;
646646 // If loop executes while iv is "greater" with the iv value going up, then
647647 // the iv must wrap.
648648 if (CmpGreater && IVBump > 0)
649 return 0;
649 return nullptr;
650650
651651 if (Start->isImm() && End->isImm()) {
652652 // Both, start and end are immediates.
654654 int64_t EndV = End->getImm();
655655 int64_t Dist = EndV - StartV;
656656 if (Dist == 0)
657 return 0;
657 return nullptr;
658658
659659 bool Exact = (Dist % IVBump) == 0;
660660
661661 if (Cmp == Comparison::NE) {
662662 if (!Exact)
663 return 0;
663 return nullptr;
664664 if ((Dist < 0) ^ (IVBump < 0))
665 return 0;
665 return nullptr;
666666 }
667667
668668 // For comparisons that include the final value (i.e. include equality
683683 uint64_t Count = Dist1;
684684
685685 if (Count > 0xFFFFFFFFULL)
686 return 0;
686 return nullptr;
687687
688688 return new CountValue(CountValue::CV_Immediate, Count);
689689 }
695695 // If the induction variable bump is not a power of 2, quit.
696696 // Othwerise we'd need a general integer division.
697697 if (!isPowerOf2_64(abs64(IVBump)))
698 return 0;
698 return nullptr;
699699
700700 MachineBasicBlock *PH = Loop->getLoopPreheader();
701701 assert (PH && "Should have a preheader by now");
766766 // Hardware loops cannot handle 64-bit registers. If it's a double
767767 // register, it has to have a subregister.
768768 if (!SR && RC == &Hexagon::DoubleRegsRegClass)
769 return 0;
769 return nullptr;
770770 const TargetRegisterClass *IntRC = &Hexagon::IntRegsRegClass;
771771
772772 // Compute DistR (register with the distance between Start and End).
10131013
10141014 MachineBasicBlock *LastMBB = L->getExitingBlock();
10151015 // Don't generate hw loop if the loop has more than one exit.
1016 if (LastMBB == 0)
1016 if (!LastMBB)
10171017 return false;
10181018
10191019 MachineBasicBlock::iterator LastI = LastMBB->getFirstTerminator();
10351035 SmallVector OldInsts;
10361036 // Are we able to determine the trip count for the loop?
10371037 CountValue *TripCount = getLoopTripCount(L, OldInsts);
1038 if (TripCount == 0)
1038 if (!TripCount)
10391039 return false;
10401040
10411041 // Is the trip count available in the preheader?
11271127 if (LastI != LastMBB->end())
11281128 LastI = LastMBB->erase(LastI);
11291129 SmallVector Cond;
1130 TII->InsertBranch(*LastMBB, BranchTarget, 0, Cond, LastIDL);
1130 TII->InsertBranch(*LastMBB, BranchTarget, nullptr, Cond, LastIDL);
11311131 }
11321132 } else {
11331133 // Conditional branch to loop start; just delete it.
11961196 case Hexagon::CONST64_Int_Real:
11971197 return DI;
11981198 }
1199 return 0;
1199 return nullptr;
12001200 }
12011201
12021202
12911291 if (IndRegs.empty())
12921292 return false;
12931293
1294 MachineBasicBlock *TB = 0, *FB = 0;
1294 MachineBasicBlock *TB = nullptr, *FB = nullptr;
12951295 SmallVector Cond;
12961296 // AnalyzeBranch returns true if it fails to analyze branch.
12971297 bool NotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Cond, false);
13221322 return false;
13231323
13241324 SmallSet CmpRegs;
1325 MachineOperand *CmpImmOp = 0;
1325 MachineOperand *CmpImmOp = nullptr;
13261326
13271327 // Go over all operands to the compare and look for immediate and register
13281328 // operands. Assume that if the compare has a single register use and a
14201420 DebugLoc DL;
14211421
14221422 if (!Latch || Header->hasAddressTaken())
1423 return 0;
1423 return nullptr;
14241424
14251425 typedef MachineBasicBlock::instr_iterator instr_iterator;
14261426
14291429 typedef std::vector MBBVector;
14301430 MBBVector Preds(Header->pred_begin(), Header->pred_end());
14311431 SmallVector Tmp1;
1432 MachineBasicBlock *TB = 0, *FB = 0;
1432 MachineBasicBlock *TB = nullptr, *FB = nullptr;
14331433
14341434 if (TII->AnalyzeBranch(*Latch, TB, FB, Tmp1, false))
1435 return 0;
1435 return nullptr;
14361436
14371437 for (MBBVector::iterator I = Preds.begin(), E = Preds.end(); I != E; ++I) {
14381438 MachineBasicBlock *PB = *I;
14391439 if (PB != Latch) {
14401440 bool NotAnalyzed = TII->AnalyzeBranch(*PB, TB, FB, Tmp1, false);
14411441 if (NotAnalyzed)
1442 return 0;
1442 return nullptr;
14431443 }
14441444 }
14451445
15151515 SmallVector Tmp2;
15161516 SmallVector EmptyCond;
15171517
1518 TB = FB = 0;
1518 TB = FB = nullptr;
15191519
15201520 for (MBBVector::iterator I = Preds.begin(), E = Preds.end(); I != E; ++I) {
15211521 MachineBasicBlock *PB = *I;
15251525 (void)NotAnalyzed; // suppress compiler warning
15261526 assert (!NotAnalyzed && "Should be analyzable!");
15271527 if (TB != Header && (Tmp2.empty() || FB != Header))
1528 TII->InsertBranch(*PB, NewPH, 0, EmptyCond, DL);
1528 TII->InsertBranch(*PB, NewPH, nullptr, EmptyCond, DL);
15291529 PB->ReplaceUsesOfBlockWith(Header, NewPH);
15301530 }
15311531 }
15321532
15331533 // It can happen that the latch block will fall through into the header.
15341534 // Insert an unconditional branch to the header.
1535 TB = FB = 0;
1535 TB = FB = nullptr;
15361536 bool LatchNotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Tmp2, false);
15371537 (void)LatchNotAnalyzed; // suppress compiler warning
15381538 assert (!LatchNotAnalyzed && "Should be analyzable!");
15391539 if (!TB && !FB)
1540 TII->InsertBranch(*Latch, Header, 0, EmptyCond, DL);
1540 TII->InsertBranch(*Latch, Header, nullptr, EmptyCond, DL);
15411541
15421542 // Finally, the branch from the preheader to the header.
1543 TII->InsertBranch(*NewPH, Header, 0, EmptyCond, DL);
1543 TII->InsertBranch(*NewPH, Header, nullptr, EmptyCond, DL);
15441544 NewPH->addSuccessor(Header);
15451545
15461546 return NewPH;
186186 static void initializePassOnce(PassRegistry &Registry) {
187187 const char *Name = "Hexagon DAG->DAG Pattern Instruction Selection";
188188 PassInfo *PI = new PassInfo(Name, "hexagon-isel",
189 &SelectionDAGISel::ID, 0, false, false);
189 &SelectionDAGISel::ID, nullptr, false, false);
190190 Registry.registerPass(*PI, true);
191191 }
192192
12381238 SDNode *PdRs = CurDAG->getMachineNode(Hexagon::TFR_PdRs, dl, MVT::i1,
12391239 SDValue(Arg, 0));
12401240 Ops.push_back(SDValue(PdRs,0));
1241 } else if (RC == NULL && (dyn_cast(Arg) != NULL)) {
1241 } else if (!RC && (dyn_cast(Arg) != nullptr)) {
12421242 // This is immediate operand. Lower it here making sure that we DO have
12431243 // const SDNode for immediate value.
12441244 int32_t Val = cast(Arg)->getSExtValue();
13461346 SDNode *HexagonDAGToDAGISel::Select(SDNode *N) {
13471347 if (N->isMachineOpcode()) {
13481348 N->setNodeId(-1);
1349 return NULL; // Already selected.
1349 return nullptr; // Already selected.
13501350 }
13511351
13521352
411411 int NumNamedVarArgParams = -1;
412412 if (GlobalAddressSDNode *GA = dyn_cast(Callee))
413413 {
414 const Function* CalleeFn = NULL;
414 const Function* CalleeFn = nullptr;
415415 Callee = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, MVT::i32);
416416 if ((CalleeFn = dyn_cast(GA->getGlobal())))
417417 {
14811481 const char*
14821482 HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
14831483 switch (Opcode) {
1484 default: return 0;
1484 default: return nullptr;
14851485 case HexagonISD::CONST32: return "HexagonISD::CONST32";
14861486 case HexagonISD::CONST32_GP: return "HexagonISD::CONST32_GP";
14871487 case HexagonISD::CONST32_Int_Real: return "HexagonISD::CONST32_Int_Real";
137137 regPos = 1;
138138 }
139139
140 if (FBB == 0) {
140 if (!FBB) {
141141 if (Cond.empty()) {
142142 // Due to a bug in TailMerging/CFG Optimization, we need to add a
143143 // special case handling of a predicated jump followed by an
153153 if (NewTBB == NextBB) {
154154 ReverseBranchCondition(Cond);
155155 RemoveBranch(MBB);
156 return InsertBranch(MBB, TBB, 0, Cond, DL);
156 return InsertBranch(MBB, TBB, nullptr, Cond, DL);
157157 }
158158 }
159159 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
176176 MachineBasicBlock *&FBB,
177177 SmallVectorImpl &Cond,
178178 bool AllowModify) const {
179 TBB = NULL;
180 FBB = NULL;
179 TBB = nullptr;
180 FBB = nullptr;
181181
182182 // If the block has no terminators, it just falls into the block after it.
183183 MachineBasicBlock::instr_iterator I = MBB.instr_end();
226226
227227 // Get the last instruction in the block.
228228 MachineInstr *LastInst = I;
229 MachineInstr *SecondLastInst = NULL;
229 MachineInstr *SecondLastInst = nullptr;
230230 // Find one more terminator if present.
231231 do {
232232 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(I)) {
559559 const SmallVectorImpl &Ops,
560560 int FI) const {
561561 // Hexagon_TODO: Implement.
562 return(0);
562 return nullptr;
563563 }
564564
565565 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
2121
2222 /// Platform specific modifications to DAG.
2323 void VLIWMachineScheduler::postprocessDAG() {
24 SUnit* LastSequentialCall = NULL;
24 SUnit* LastSequentialCall = nullptr;
2525 // Currently we only catch the situation when compare gets scheduled
2626 // before preceding call.
2727 for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
397397 for (unsigned i = 0; Available.empty(); ++i) {
398398 assert(i <= (HazardRec->getMaxLookAhead() + MaxMinLatency) &&
399399 "permanent hazard"); (void)i;
400 ResourceModel->reserveResources(0);
400 ResourceModel->reserveResources(nullptr);
401401 bumpCycle();
402402 releasePending();
403403 }
404404 if (Available.size() == 1)
405405 return *Available.begin();
406 return NULL;
406 return nullptr;
407407 }
408408
409409 #ifndef NDEBUG
423423 /// getSingleUnscheduledPred - If there is exactly one unscheduled predecessor
424424 /// of SU, return it, otherwise return null.
425425 static SUnit *getSingleUnscheduledPred(SUnit *SU) {
426 SUnit *OnlyAvailablePred = 0;
426 SUnit *OnlyAvailablePred = nullptr;
427427 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
428428 I != E; ++I) {
429429 SUnit &Pred = *I->getSUnit();
431431 // We found an available, but not scheduled, predecessor. If it's the
432432 // only one we have found, keep track of it... otherwise give up.
433433 if (OnlyAvailablePred && OnlyAvailablePred != &Pred)
434 return 0;
434 return nullptr;
435435 OnlyAvailablePred = &Pred;
436436 }
437437 }
441441 /// getSingleUnscheduledSucc - If there is exactly one unscheduled successor
442442 /// of SU, return it, otherwise return null.
443443 static SUnit *getSingleUnscheduledSucc(SUnit *SU) {
444 SUnit *OnlyAvailableSucc = 0;
444 SUnit *OnlyAvailableSucc = nullptr;
445445 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
446446 I != E; ++I) {
447447 SUnit &Succ = *I->getSUnit();
449449 // We found an available, but not scheduled, successor. If it's the
450450 // only one we have found, keep track of it... otherwise give up.
451451 if (OnlyAvailableSucc && OnlyAvailableSucc != &Succ)
452 return 0;
452 return nullptr;
453453 OnlyAvailableSucc = &Succ;
454454 }
455455 }
638638 if (DAG->top() == DAG->bottom()) {
639639 assert(Top.Available.empty() && Top.Pending.empty() &&
640640 Bot.Available.empty() && Bot.Pending.empty() && "ReadyQ garbage");
641 return NULL;
641 return nullptr;
642642 }
643643 SUnit *SU;
644644 if (llvm::ForceTopDown) {
393393 bool MO2IsKill = false;
394394 MachineBasicBlock::iterator jmpPos;
395395 MachineBasicBlock::iterator cmpPos;
396 MachineInstr *cmpInstr = NULL, *jmpInstr = NULL;
397 MachineBasicBlock *jmpTarget = NULL;
396 MachineInstr *cmpInstr = nullptr, *jmpInstr = nullptr;
397 MachineBasicBlock *jmpTarget = nullptr;
398398 bool afterRA = false;
399399 bool isSecondOpReg = false;
400400 bool isSecondOpNewified = false;
221221 static void initializePassOnce(PassRegistry &Registry) {
222222 const char *Name = "Hexagon Split TFRCondSets";
223223 PassInfo *PI = new PassInfo(Name, "hexagon-split-tfr",
224 &HexagonSplitTFRCondSets::ID, 0, false, false);
224 &HexagonSplitTFRCondSets::ID, nullptr, false,
225 false);
225226 Registry.registerPass(*PI, true);
226227 }
227228
603603 // evaluate identically
604604 unsigned predRegNumSrc = 0;
605605 unsigned predRegNumDst = 0;
606 const TargetRegisterClass* predRegClass = NULL;
606 const TargetRegisterClass* predRegClass = nullptr;
607607
608608 // Get predicate register used in the source instruction
609609 for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
11721172 // of that (IsCallDependent) function. Bug 6216 is opened for this.
11731173 //
11741174 unsigned DepReg = 0;
1175 const TargetRegisterClass* RC = NULL;
1175 const TargetRegisterClass* RC = nullptr;
11761176 if (DepType == SDep::Data) {
11771177 DepReg = SUJ->Succs[i].getReg();
11781178 RC = QRI->getMinimalPhysRegClass(DepReg);
2020 HexagonMCAsmInfo::HexagonMCAsmInfo(StringRef TT) {
2121 Data16bitsDirective = "\t.half\t";
2222 Data32bitsDirective = "\t.word\t";
23 Data64bitsDirective = 0; // .xword is only supported by V9.
23 Data64bitsDirective = nullptr; // .xword is only supported by V9.
2424 ZeroDirective = "\t.skip\t";
2525 CommentString = "//";
2626 HasLEB128 = true;
5959
6060 // VirtualFP = (R30 + #0).
6161 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(
62 0, Hexagon::R30, 0);
62 nullptr, Hexagon::R30, 0);
6363 MAI->addInitialFrameState(Inst);
6464
6565 return MAI;
6565 const MCSubtargetInfo &STI) {
6666 if (SyntaxVariant == 0)
6767 return new MSP430InstPrinter(MAI, MII, MRI);
68 return 0;
68 return nullptr;
6969 }
7070
7171 extern "C" void LLVMInitializeMSP430TargetMC() {
4646 }
4747
4848 void printOperand(const MachineInstr *MI, int OpNum,
49 raw_ostream &O, const char* Modifier = 0);
49 raw_ostream &O, const char* Modifier = nullptr);
5050 void printSrcMemOperand(const MachineInstr *MI, int OpNum,
5151 raw_ostream &O);
5252 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
241241 // alignment boundary.
242242 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
243243
244 MachineInstr *New = 0;
244 MachineInstr *New = nullptr;
245245 if (Old->getOpcode() == TII.getCallFrameSetupOpcode()) {
246246 New = BuildMI(MF, Old->getDebugLoc(),
247247 TII.get(MSP430::SUB16ri), MSP430::SPW)
5353 unsigned Align; // CP alignment.
5454
5555 MSP430ISelAddressMode()
56 : BaseType(RegBase), Disp(0), GV(0), CP(0), BlockAddr(0),
57 ES(0), JT(-1), Align(0) {
56 : BaseType(RegBase), Disp(0), GV(nullptr), CP(nullptr),
57 BlockAddr(nullptr), ES(nullptr), JT(-1), Align(0) {
5858 }
5959
6060 bool hasSymbolicDisplacement() const {
61 return GV != 0 || CP != 0 || ES != 0 || JT != -1;
61 return GV != nullptr || CP != nullptr || ES != nullptr || JT != -1;
6262 }
6363
6464 void dump() {
6565 errs() << "MSP430ISelAddressMode " << this << '\n';
66 if (BaseType == RegBase && Base.Reg.getNode() != 0) {
66 if (BaseType == RegBase && Base.Reg.getNode() != nullptr) {
6767 errs() << "Base.Reg ";
6868 Base.Reg.getNode()->dump();
6969 } else if (BaseType == FrameIndexBase) {
200200
201201 case ISD::FrameIndex:
202202 if (AM.BaseType == MSP430ISelAddressMode::RegBase
203 && AM.Base.Reg.getNode() == 0) {
203 && AM.Base.Reg.getNode() == nullptr) {
204204 AM.BaseType = MSP430ISelAddressMode::FrameIndexBase;
205205 AM.Base.FrameIndex = cast(N)->getIndex();
206206 return false;
229229 // Start with the LHS as an addr mode.
230230 if (!MatchAddress(N.getOperand(0), AM) &&
231231 // Address could not have picked a GV address for the displacement.
232 AM.GV == NULL &&
232 AM.GV == nullptr &&
233233 // Check to see if the LHS & C is zero.
234234 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
235235 AM.Disp += Offset;
331331 SDNode *MSP430DAGToDAGISel::SelectIndexedLoad(SDNode *N) {
332332 LoadSDNode *LD = cast(N);
333333 if (!isValidIndexedLoad(LD))
334 return NULL;
334 return nullptr;
335335
336336 MVT VT = LD->getMemoryVT().getSimpleVT();
337337
344344 Opcode = MSP430::MOV16rm_POST;
345345 break;
346346 default:
347 return NULL;
347 return nullptr;
348348 }
349349
350350 return CurDAG->getMachineNode(Opcode, SDLoc(N),
360360 IsLegalToFold(N1, Op, Op, OptLevel)) {
361361 LoadSDNode *LD = cast(N1);
362362 if (!isValidIndexedLoad(LD))
363 return NULL;
363 return nullptr;
364364
365365 MVT VT = LD->getMemoryVT().getSimpleVT();
366366 unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8);
379379 return ResNode;
380380 }
381381
382 return NULL;
382 return nullptr;
383383 }
384384
385385
397397 Node->dump(CurDAG);
398398 errs() << "\n");
399399 Node->setNodeId(-1);
400 return NULL;
400 return nullptr;
401401 }
402402
403403 // Few custom selection stuff.
485485 SDNode *ResNode = SelectCode(Node);
486486
487487 DEBUG(errs() << "=> ");
488 if (ResNode == NULL || ResNode == Node)
488 if (ResNode == nullptr || ResNode == Node)
489489 DEBUG(Node->dump(CurDAG));
490490 else
491491 DEBUG(ResNode->dump(CurDAG));
628628 } else {
629629 assert(VA.isMemLoc());
630630
631 if (StackPtr.getNode() == 0)
631 if (!StackPtr.getNode())
632632 StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
633633
634634 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11471147
11481148 const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
11491149 switch (Opcode) {
1150 default: return NULL;
1150 default: return nullptr;
11511151 case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG";
11521152 case MSP430ISD::RETI_FLAG: return "MSP430ISD::RETI_FLAG";
11531153 case MSP430ISD::RRA: return "MSP430ISD::RRA";
207207 while (std::next(I) != MBB.end())
208208 std::next(I)->eraseFromParent();
209209 Cond.clear();
210 FBB = 0;
210 FBB = nullptr;
211211
212212 // Delete the JMP if it's equivalent to a fall-through.
213213 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
214 TBB = 0;
214 TBB = nullptr;
215215 I->eraseFromParent();
216216 I = MBB.end();
217217 continue;
468468 public:
469469 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
470470 // Add as immediate when possible. Null MCExpr = 0.
471 if (Expr == 0)
471 if (!Expr)
472472 Inst.addOperand(MCOperand::CreateImm(0));
473473 else if (const MCConstantExpr *CE = dyn_cast(Expr))
474474 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
16151615 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMemOperand(
16161616 SmallVectorImpl &Operands) {
16171617 DEBUG(dbgs() << "parseMemOperand\n");
1618 const MCExpr *IdVal = 0;
1618 const MCExpr *IdVal = nullptr;
16191619 SMLoc S;
16201620 bool isParenExpr = false;
16211621 MipsAsmParser::OperandMatchResultTy Res = MatchOperand_NoMatch;
16711671
16721672 Parser.Lex(); // Eat the ')' token.
16731673
1674 if (IdVal == 0)
1674 if (!IdVal)
16751675 IdVal = MCConstantExpr::Create(0, getContext());
16761676
16771677 // Replace the register operand with the memory operand.
3030
3131 // Prepare value for the target space for it
3232 static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
33 MCContext *Ctx = NULL) {
33 MCContext *Ctx = nullptr) {
3434
3535 unsigned Kind = Fixup.getKind();
3636
7878 MCAsmInfo *MAI = new MipsMCAsmInfo(TT);
7979
8080 unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
81 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(0, SP, 0);
81 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0);
8282 MAI->addInitialFrameState(Inst);
8383
8484 return MAI;
406406 CallInst::Create(F, Params, "", &Inst );
407407 } else if (const CallInst *CI = dyn_cast(I)) {
408408 const Value* V = CI->getCalledValue();
409 const Type* T = 0;
409 const Type* T = nullptr;
410410 if (V) T = V->getType();
411 const PointerType *PFT=0;
411 const PointerType *PFT=nullptr;
412412 if (T) PFT = dyn_cast(T);
413 const FunctionType *FT=0;
413 const FunctionType *FT=nullptr;
414414 if (PFT) FT = dyn_cast(PFT->getElementType());
415415 Function *F_ = CI->getCalledFunction();
416416 if (FT && needsFPReturnHelper(*FT) &&
2929 { "__fixunssfsi", { FSig, NoFPRet } },
3030 { "__fixunssfdi", { FSig, NoFPRet } },
3131 { "__floatundisf", { NoSig, FRet } },
32 { 0, { NoSig, NoFPRet } }
32 { nullptr, { NoSig, NoFPRet } }
3333 };
3434
3535 // just do a search for now. there are very few of these special cases.
4343 return &PredefinedFuncs[i].Signature;
4444 i++;
4545 }
46 return 0;
46 return nullptr;
4747 }
4848 }
4949 }
4444 std::pair
4545 Mips16DAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, SDLoc DL, EVT Ty,
4646 bool HasLo, bool HasHi) {
47 SDNode *Lo = 0, *Hi = 0;
47 SDNode *Lo = nullptr, *Hi = nullptr;
4848 SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0),
4949 N->getOperand(1));
5050 SDValue InFlag = SDValue(Mul, 0);
297297 if (!SDValue(Node, 1).use_empty())
298298 ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0));
299299
300 return std::make_pair(true, (SDNode*)NULL);
300 return std::make_pair(true, nullptr);
301301 }
302302
303303 case ISD::MULHS:
308308 }
309309 }
310310
311 return std::make_pair(false, (SDNode*)NULL);
311 return std::make_pair(false, nullptr);
312312 }
313313
314314 FunctionPass *llvm::createMips16ISelDag(MipsTargetMachine &TM) {
353353 #define T P "0" , T1
354354 #define P P_
355355 static char const * vMips16Helper[MAX_STUB_NUMBER+1] =
356 {0, T1 };
356 {nullptr, T1 };
357357 #undef P
358358 #define P P_ "sf_"
359359 static char const * sfMips16Helper[MAX_STUB_NUMBER+1] =
430430 SelectionDAG &DAG = CLI.DAG;
431431 MachineFunction &MF = DAG.getMachineFunction();
432432 MipsFunctionInfo *FuncInfo = MF.getInfo();
433 const char* Mips16HelperFunction = 0;
433 const char* Mips16HelperFunction = nullptr;
434434 bool NeedMips16Helper = false;
435435
436436 if (Subtarget->inMips16HardFloat()) {
836836 const MCSectionELF *M = OutContext.getELFSection(
837837 ".mips16.call.fp." + std::string(Symbol), ELF::SHT_PROGBITS,
838838 ELF::SHF_ALLOC | ELF::SHF_EXECINSTR, SectionKind::getText());
839 OutStreamer.SwitchSection(M, 0);
839 OutStreamer.SwitchSection(M, nullptr);
840840 //
841841 // .align 2
842842 //
6565
6666 public:
6767 MipsCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68 : MachineFunctionPass(ID), JTI(0), II(0), TD(0),
69 TM(tm), MCE(mce), MCPEs(0), MJTEs(0),
68 : MachineFunctionPass(ID), JTI(nullptr), II(nullptr), TD(nullptr),
69 TM(tm), MCE(mce), MCPEs(nullptr), MJTEs(nullptr),
7070 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
7171
7272 bool runOnMachineFunction(MachineFunction &MF);
138138 TD = Target.getDataLayout();
139139 Subtarget = &TM.getSubtarget ();
140140 MCPEs = &MF.getConstantPool()->getConstants();
141 MJTEs = 0;
141 MJTEs = nullptr;
142142 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
143143 JTI->Initialize(MF, IsPIC, Subtarget->isLittle());
144144 MCE.setModuleInfo(&getAnalysis ());
367367 : MachineFunctionPass(ID), TM(tm),
368368 IsPIC(TM.getRelocationModel() == Reloc::PIC_),
369369 ABI(TM.getSubtarget().getTargetABI()),
370 STI(&TM.getSubtarget()), MF(0), MCP(0),
370 STI(&TM.getSubtarget()), MF(nullptr), MCP(nullptr),
371371 PrescannedForConstants(false){}
372372
373373 virtual const char *getPassName() const {
627627 if (CPEs[i].CPEMI == CPEMI)
628628 return &CPEs[i];
629629 }
630 return NULL;
630 return nullptr;
631631 }
632632
633633 /// getCPELogAlign - Returns the required alignment of the constant pool entry
10641064 assert(CPE && "Unexpected!");
10651065 if (--CPE->RefCount == 0) {
10661066 removeDeadCPEMI(CPEMI);
1067 CPE->CPEMI = NULL;
1067 CPE->CPEMI = nullptr;
10681068 --NumCPEs;
10691069 return true;
10701070 }
10971097 if (CPEs[i].CPEMI == CPEMI)
10981098 continue;
10991099 // Removing CPEs can leave empty entries, skip
1100 if (CPEs[i].CPEMI == NULL)
1100 if (CPEs[i].CPEMI == nullptr)
11011101 continue;
11021102 if (isCPEntryInRange(UserMI, UserOffset, CPEs[i].CPEMI, U.getMaxDisp(),
11031103 U.NegOk)) {
11531153 if (CPEs[i].CPEMI == CPEMI)
11541154 continue;
11551155 // Removing CPEs can leave empty entries, skip
1156 if (CPEs[i].CPEMI == NULL)
1156 if (CPEs[i].CPEMI == nullptr)
11571157 continue;
11581158 if (isCPEntryInRange(UserMI, UserOffset, CPEs[i].CPEMI,
11591159 U.getLongFormMaxDisp(), U.NegOk)) {
14851485 for (unsigned j = 0, ee = CPEs.size(); j != ee; ++j) {
14861486 if (CPEs[j].RefCount == 0 && CPEs[j].CPEMI) {
14871487 removeDeadCPEMI(CPEs[j].CPEMI);
1488 CPEs[j].CPEMI = NULL;
1488 CPEs[j].CPEMI = nullptr;
14891489 MadeChange = true;
14901490 }
14911491 }
407407 (*MI.memoperands_begin())->getPseudoValue()) {
408408 if (isa(PSV))
409409 return false;
410 return !PSV->isConstant(0) && PSV != PseudoSourceValue::getStack();
410 return !PSV->isConstant(nullptr) && PSV != PseudoSourceValue::getStack();
411411 }
412412
413413 return true;
643643
644644 MachineBasicBlock *Filler::selectSuccBB(MachineBasicBlock &B) const {
645645 if (B.succ_empty())
646 return NULL;
646 return nullptr;
647647
648648 // Select the successor with the larget edge weight.
649649 auto &Prob = getAnalysis();
652652 const MachineBasicBlock *Dst1) {
653653 return Prob.getEdgeWeight(&B, Dst0) < Prob.getEdgeWeight(&B, Dst1);
654654 });
655 return S->isLandingPad() ? NULL : S;
655 return S->isLandingPad() ? nullptr : S;
656656 }
657657
658658 std::pair
659659 Filler::getBranch(MachineBasicBlock &MBB, const MachineBasicBlock &Dst) const {
660660 const MipsInstrInfo *TII =
661661 static_cast(TM.getInstrInfo());
662 MachineBasicBlock *TrueBB = 0, *FalseBB = 0;
662 MachineBasicBlock *TrueBB = nullptr, *FalseBB = nullptr;
663663 SmallVector BranchInstrs;
664664 SmallVector Cond;
665665
667667 TII->AnalyzeBranch(MBB, TrueBB, FalseBB, Cond, false, BranchInstrs);
668668
669669 if ((R == MipsInstrInfo::BT_None) || (R == MipsInstrInfo::BT_NoBranch))
670 return std::make_pair(R, (MachineInstr*)NULL);
670 return std::make_pair(R, nullptr);
671671
672672 if (R != MipsInstrInfo::BT_CondUncond) {
673673 if (!hasUnoccupiedSlot(BranchInstrs[0]))
674 return std::make_pair(MipsInstrInfo::BT_None, (MachineInstr*)NULL);
674 return std::make_pair(MipsInstrInfo::BT_None, nullptr);
675675
676676 assert(((R != MipsInstrInfo::BT_Uncond) || (TrueBB == &Dst)));
677677
688688 if (hasUnoccupiedSlot(BranchInstrs[1]) && (FalseBB == &Dst))
689689 return std::make_pair(MipsInstrInfo::BT_Uncond, BranchInstrs[1]);
690690
691 return std::make_pair(MipsInstrInfo::BT_None, (MachineInstr*)NULL);
691 return std::make_pair(MipsInstrInfo::BT_None, nullptr);
692692 }
693693
694694 bool Filler::examinePred(MachineBasicBlock &Pred, const MachineBasicBlock &Succ,
182182 if (Node->isMachineOpcode()) {
183183 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
184