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[ARM] Handle +t2dsp feature as an ArchExtKind in ARMTargetParser.def Currently, the availability of DSP instructions (ACLE 6.4.7) is handled in a hand-rolled tricky condition block in tools/clang/lib/Basic/Targets.cpp, with a FIXME: attached. This patch changes the handling of +t2dsp to be in line with other architecture extensions. Following a revert of r248152 and new review comments, this patch also includes renaming FeatureDSPThumb2 -> FeatureDSP, hasThumb2DSP() -> hasDSP(), etc. The spelling of "t2dsp" is preserved, pending a further investigation of its possible external usage. Differential Revision: http://reviews.llvm.org/D12937 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248519 91177308-0d34-0410-b5e6-96231b3b80d8 Artyom Skrobov 4 years ago
15 changed file(s) with 113 addition(s) and 116 deletion(s). Raw diff Collapse all Expand all
6060 ARM_ARCH("armv5t", AK_ARMV5T, "5T", "v5", ARMBuildAttrs::CPUArch::v5T,
6161 AEK_NONE)
6262 ARM_ARCH("armv5te", AK_ARMV5TE, "5TE", "v5e", ARMBuildAttrs::CPUArch::v5TE,
63 AEK_NONE)
63 AEK_DSP)
6464 ARM_ARCH("armv5tej", AK_ARMV5TEJ, "5TEJ", "v5e", ARMBuildAttrs::CPUArch::v5TEJ,
65 AEK_NONE)
65 AEK_DSP)
6666 ARM_ARCH("armv6", AK_ARMV6, "6", "v6", ARMBuildAttrs::CPUArch::v6,
67 AEK_NONE)
67 AEK_DSP)
6868 ARM_ARCH("armv6k", AK_ARMV6K, "6K", "v6k", ARMBuildAttrs::CPUArch::v6K,
69 AEK_NONE)
69 AEK_DSP)
7070 ARM_ARCH("armv6t2", AK_ARMV6T2, "6T2", "v6t2", ARMBuildAttrs::CPUArch::v6T2,
71 AEK_NONE)
71 AEK_DSP)
7272 ARM_ARCH("armv6z", AK_ARMV6Z, "6Z", "v6z", ARMBuildAttrs::CPUArch::v6KZ,
73 AEK_SEC)
73 AEK_DSP)
7474 ARM_ARCH("armv6zk", AK_ARMV6ZK, "6ZK", "v6zk", ARMBuildAttrs::CPUArch::v6KZ,
75 AEK_SEC)
75 AEK_DSP)
7676 ARM_ARCH("armv6-m", AK_ARMV6M, "6-M", "v6m", ARMBuildAttrs::CPUArch::v6_M,
7777 AEK_NONE)
7878 ARM_ARCH("armv6s-m", AK_ARMV6SM, "6S-M", "v6sm", ARMBuildAttrs::CPUArch::v6S_M,
7979 AEK_NONE)
8080 ARM_ARCH("armv7-a", AK_ARMV7A, "7-A", "v7", ARMBuildAttrs::CPUArch::v7,
81 AEK_NONE)
81 AEK_DSP)
8282 ARM_ARCH("armv7-r", AK_ARMV7R, "7-R", "v7r", ARMBuildAttrs::CPUArch::v7,
83 AEK_HWDIV)
83 (AEK_HWDIV | AEK_DSP))
8484 ARM_ARCH("armv7-m", AK_ARMV7M, "7-M", "v7m", ARMBuildAttrs::CPUArch::v7,
8585 AEK_HWDIV)
8686 ARM_ARCH("armv7e-m", AK_ARMV7EM, "7E-M", "v7em", ARMBuildAttrs::CPUArch::v7E_M,
87 AEK_HWDIV)
87 (AEK_HWDIV | AEK_DSP))
8888 ARM_ARCH("armv8-a", AK_ARMV8A, "8-A", "v8", ARMBuildAttrs::CPUArch::v8,
89 (AEK_SEC | AEK_MP | AEK_VIRT | AEK_HWDIVARM | AEK_HWDIV))
89 (AEK_SEC | AEK_MP | AEK_VIRT | AEK_HWDIVARM | AEK_HWDIV | AEK_DSP))
9090 ARM_ARCH("armv8.1-a", AK_ARMV8_1A, "8.1-A", "v8.1a", ARMBuildAttrs::CPUArch::v8,
91 (AEK_SEC | AEK_MP | AEK_VIRT | AEK_HWDIVARM | AEK_HWDIV))
91 (AEK_SEC | AEK_MP | AEK_VIRT | AEK_HWDIVARM | AEK_HWDIV | AEK_DSP))
9292 // Non-standard Arch names.
9393 ARM_ARCH("iwmmxt", AK_IWMMXT, "iwmmxt", "", ARMBuildAttrs::CPUArch::v5TE,
9494 AEK_NONE)
9999 ARM_ARCH("armv5", AK_ARMV5, "5T", "v5", ARMBuildAttrs::CPUArch::v5T,
100100 AEK_NONE)
101101 ARM_ARCH("armv5e", AK_ARMV5E, "5TE", "v5e", ARMBuildAttrs::CPUArch::v5TE,
102 AEK_NONE)
102 AEK_DSP)
103103 ARM_ARCH("armv6j", AK_ARMV6J, "6J", "v6", ARMBuildAttrs::CPUArch::v6,
104 AEK_NONE)
104 AEK_DSP)
105105 ARM_ARCH("armv6hl", AK_ARMV6HL, "6-M", "v6hl", ARMBuildAttrs::CPUArch::v6_M,
106106 AEK_NONE)
107107 ARM_ARCH("armv7", AK_ARMV7, "7", "v7", ARMBuildAttrs::CPUArch::v7,
108108 AEK_NONE)
109109 ARM_ARCH("armv7l", AK_ARMV7L, "7-L", "v7l", ARMBuildAttrs::CPUArch::v7,
110 AEK_NONE)
110 AEK_DSP)
111111 ARM_ARCH("armv7hl", AK_ARMV7HL, "7-L", "v7hl", ARMBuildAttrs::CPUArch::v7,
112 AEK_NONE)
112 AEK_DSP)
113113 ARM_ARCH("armv7s", AK_ARMV7S, "7-S", "v7s", ARMBuildAttrs::CPUArch::v7,
114 AEK_NONE)
114 AEK_DSP)
115115 ARM_ARCH("armv7k", AK_ARMV7K, "7-K", "v7k", ARMBuildAttrs::CPUArch::v7,
116 AEK_NONE)
116 AEK_DSP)
117117 #undef ARM_ARCH
118118
119119 #ifndef ARM_ARCH_EXT_NAME
8080 AEK_SIMD = 0x80,
8181 AEK_SEC = 0x100,
8282 AEK_VIRT = 0x200,
83 AEK_DSP = 0x400,
8384 // Unsupported extensions.
8485 AEK_OS = 0x8000000,
8586 AEK_IWMMXT = 0x10000000,
187187 Features.push_back("+crc");
188188 else
189189 Features.push_back("-crc");
190
191 if (Extensions & ARM::AEK_DSP)
192 Features.push_back("+t2dsp");
193 else
194 Features.push_back("-t2dsp");
190195
191196 return getHWDivFeatures(Extensions, Features);
192197 }
118118 def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
119119 "Has return address stack">;
120120
121 /// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
122 def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
123 "Supports v7 DSP instructions in Thumb2">;
121 /// DSP extension (called "t2dsp" for backwards compatibility only).
122 def FeatureDSP : SubtargetFeature<"t2dsp", "HasDSP", "true",
123 "Supports DSP instructions in ARM and/or Thumb2">;
124124
125125 // Multiprocessing extension.
126126 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
278278 "Cortex-R4 ARM processors",
279279 [FeatureHWDiv,
280280 FeatureAvoidPartialCPSR,
281 FeatureDSPThumb2, FeatureT2XtPk,
282 HasV7Ops, FeatureDB, FeatureHasRAS,
283 FeatureRClass]>;
281 FeatureDSP, FeatureT2XtPk, HasV7Ops,
282 FeatureDB, FeatureHasRAS, FeatureRClass]>;
284283
285284 def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
286285 "Cortex-R5 ARM processors",
368367 FeatureHasSlowFPVMLx]>;
369368
370369 // V6T2 Processors.
371 def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops,
372 FeatureDSPThumb2]>;
370 def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops, FeatureDSP]>;
373371 def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
374372 FeatureHasSlowFPVMLx,
375 FeatureDSPThumb2]>;
373 FeatureDSP]>;
376374
377375 // V7a Processors.
378376 // FIXME: A5 has currently the same Schedule model as A8
379377 def : ProcessorModel<"cortex-a5", CortexA8Model,
380378 [ProcA5, HasV7Ops, FeatureNEON, FeatureDB,
381 FeatureVFP4, FeatureDSPThumb2,
379 FeatureVFP4, FeatureDSP,
382380 FeatureHasRAS, FeatureAClass]>;
383381 def : ProcessorModel<"cortex-a7", CortexA8Model,
384382 [ProcA7, HasV7Ops, FeatureNEON, FeatureDB,
385 FeatureDSPThumb2, FeatureHasRAS,
386 FeatureAClass]>;
383 FeatureDSP, FeatureHasRAS, FeatureAClass]>;
387384 def : ProcessorModel<"cortex-a8", CortexA8Model,
388385 [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
389 FeatureDSPThumb2, FeatureHasRAS,
390 FeatureAClass]>;
386 FeatureDSP, FeatureHasRAS, FeatureAClass]>;
391387 def : ProcessorModel<"cortex-a9", CortexA9Model,
392388 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
393 FeatureDSPThumb2, FeatureHasRAS, FeatureMP,
389 FeatureDSP, FeatureHasRAS, FeatureMP,
394390 FeatureAClass]>;
395391
396392 // FIXME: A12 has currently the same Schedule model as A9
397393 def : ProcessorModel<"cortex-a12", CortexA9Model,
398394 [ProcA12, HasV7Ops, FeatureNEON, FeatureDB,
399 FeatureDSPThumb2, FeatureMP,
395 FeatureDSP, FeatureMP,
400396 FeatureHasRAS, FeatureAClass]>;
401397
402398 // FIXME: A15 has currently the same ProcessorModel as A9.
403399 def : ProcessorModel<"cortex-a15", CortexA9Model,
404400 [ProcA15, HasV7Ops, FeatureNEON, FeatureDB,
405 FeatureDSPThumb2, FeatureHasRAS,
406 FeatureAClass]>;
401 FeatureDSP, FeatureHasRAS, FeatureAClass]>;
407402
408403 // FIXME: A17 has currently the same Schedule model as A9
409404 def : ProcessorModel<"cortex-a17", CortexA9Model,
410405 [ProcA17, HasV7Ops, FeatureNEON, FeatureDB,
411 FeatureDSPThumb2, FeatureMP,
406 FeatureDSP, FeatureMP,
412407 FeatureHasRAS, FeatureAClass]>;
413408
414409 // FIXME: krait has currently the same Schedule model as A9
415410 def : ProcessorModel<"krait", CortexA9Model,
416411 [ProcKrait, HasV7Ops,
417412 FeatureNEON, FeatureDB,
418 FeatureDSPThumb2, FeatureHasRAS,
419 FeatureAClass]>;
413 FeatureDSP, FeatureHasRAS, FeatureAClass]>;
420414
421415 // FIXME: R4 has currently the same ProcessorModel as A8.
422416 def : ProcessorModel<"cortex-r4", CortexA8Model,
431425 // FIXME: R5 has currently the same ProcessorModel as A8.
432426 def : ProcessorModel<"cortex-r5", CortexA8Model,
433427 [ProcR5, HasV7Ops, FeatureDB,
434 FeatureVFP3, FeatureDSPThumb2,
435 FeatureHasRAS,
428 FeatureVFP3, FeatureDSP, FeatureHasRAS,
436429 FeatureD16, FeatureRClass]>;
437430
438431 // FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.
439432 def : ProcessorModel<"cortex-r7", CortexA8Model,
440433 [ProcR5, HasV7Ops, FeatureDB,
441 FeatureVFP3, FeatureDSPThumb2,
434 FeatureVFP3, FeatureDSP,
442435 FeatureHasRAS, FeatureVFPOnlySP,
443436 FeatureD16, FeatureMP, FeatureRClass]>;
444437
453446 // V7EM Processors.
454447 def : ProcNoItin<"cortex-m4", [HasV7Ops,
455448 FeatureThumb2, FeatureNoARM, FeatureDB,
456 FeatureHWDiv, FeatureDSPThumb2,
457 FeatureT2XtPk, FeatureVFP4,
458 FeatureVFPOnlySP, FeatureD16,
449 FeatureHWDiv, FeatureDSP, FeatureT2XtPk,
450 FeatureVFP4, FeatureVFPOnlySP, FeatureD16,
459451 FeatureMClass]>;
460452 def : ProcNoItin<"cortex-m7", [HasV7Ops,
461453 FeatureThumb2, FeatureNoARM, FeatureDB,
462 FeatureHWDiv, FeatureDSPThumb2,
454 FeatureHWDiv, FeatureDSP,
463455 FeatureT2XtPk, FeatureFPARMv8,
464456 FeatureD16, FeatureMClass]>;
465457
467459 // Swift uArch Processors.
468460 def : ProcessorModel<"swift", SwiftModel,
469461 [ProcSwift, HasV7Ops, FeatureNEON,
470 FeatureDB, FeatureDSPThumb2,
462 FeatureDB, FeatureDSP,
471463 FeatureHasRAS, FeatureAClass]>;
472464
473465 // V8 Processors
474466 def : ProcNoItin<"cortex-a53", [ProcA53, HasV8Ops, FeatureAClass,
475467 FeatureDB, FeatureFPARMv8,
476 FeatureNEON, FeatureDSPThumb2]>;
468 FeatureNEON, FeatureDSP]>;
477469 def : ProcNoItin<"cortex-a57", [ProcA57, HasV8Ops, FeatureAClass,
478470 FeatureDB, FeatureFPARMv8,
479 FeatureNEON, FeatureDSPThumb2]>;
471 FeatureNEON, FeatureDSP]>;
480472 // FIXME: Cortex-A72 is currently modelled as an Cortex-A57.
481473 def : ProcNoItin<"cortex-a72", [ProcA57, HasV8Ops, FeatureAClass,
482474 FeatureDB, FeatureFPARMv8,
483 FeatureNEON, FeatureDSPThumb2]>;
475 FeatureNEON, FeatureDSP]>;
484476
485477 // Cyclone is very similar to swift
486478 def : ProcessorModel<"cyclone", SwiftModel,
487479 [ProcSwift, HasV8Ops, HasV7Ops,
488480 FeatureCrypto, FeatureFPARMv8,
489 FeatureDB,FeatureDSPThumb2,
481 FeatureDB, FeatureDSP,
490482 FeatureHasRAS, FeatureZCZeroing]>;
491483
492484 //===----------------------------------------------------------------------===//
522522 if (Subtarget->hasV8Ops())
523523 return ARMBuildAttrs::v8;
524524 else if (Subtarget->hasV7Ops()) {
525 if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
525 if (Subtarget->isMClass() && Subtarget->hasDSP())
526526 return ARMBuildAttrs::v7E_M;
527527 return ARMBuildAttrs::v7;
528528 } else if (Subtarget->hasV6T2Ops())
34413441 // The flags here are common to those allowed for apsr in the A class cores and
34423442 // those allowed for the special registers in the M class cores. Returns a
34433443 // value representing which flags were present, -1 if invalid.
3444 static inline int getMClassFlagsMask(StringRef Flags, bool hasThumb2DSP) {
3444 static inline int getMClassFlagsMask(StringRef Flags, bool hasDSP) {
34453445 if (Flags.empty())
3446 return 0x2 | (int)hasThumb2DSP;
3446 return 0x2 | (int)hasDSP;
34473447
34483448 return StringSwitch(Flags)
34493449 .Case("g", 0x1)
34723472 }
34733473
34743474 // We know we are now handling a write so need to get the mask for the flags.
3475 int Mask = getMClassFlagsMask(Flags, Subtarget->hasThumb2DSP());
3475 int Mask = getMClassFlagsMask(Flags, Subtarget->hasDSP());
34763476
34773477 // Only apsr, iapsr, eapsr, xpsr can have flags. The other register values
34783478 // shouldn't have flags present.
34813481
34823482 // The _g and _nzcvqg versions are only valid if the DSP extension is
34833483 // available.
3484 if (!Subtarget->hasThumb2DSP() && (Mask & 0x1))
3484 if (!Subtarget->hasDSP() && (Mask & 0x1))
34853485 return -1;
34863486
34873487 // The register was valid so need to put the mask in the correct place
696696 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
697697 }
698698 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
699 || (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP()))
699 || (Subtarget->isThumb2() && !Subtarget->hasDSP()))
700700 setOperationAction(ISD::MULHS, MVT::i32, Expand);
701701
702702 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
233233 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
234234 AssemblerPredicate<"FeatureT2XtPk",
235235 "pack/extract">;
236 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
237 AssemblerPredicate<"FeatureDSPThumb2",
238 "thumb2-dsp">;
236 def HasDSP : Predicate<"Subtarget->hasDSP()">,
237 AssemblerPredicate<"FeatureDSP", "dsp">;
239238 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
240239 AssemblerPredicate<"FeatureDB",
241240 "data-barriers">;
20992099
21002100 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
21012101 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
2102 Requires<[IsThumb2, HasThumb2DSP]> {
2102 Requires<[IsThumb2, HasDSP]> {
21032103 let Inst{31-27} = 0b11111;
21042104 let Inst{26-24} = 0b010;
21052105 let Inst{23} = 0b1;
21162116 dag iops = (ins rGPR:$Rn, rGPR:$Rm),
21172117 string asm = "\t$Rd, $Rn, $Rm">
21182118 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
2119 Requires<[IsThumb2, HasThumb2DSP]> {
2119 Requires<[IsThumb2, HasDSP]> {
21202120 let Inst{31-27} = 0b11111;
21212121 let Inst{26-23} = 0b0101;
21222122 let Inst{22-20} = op22_20;
22142214 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
22152215 (ins rGPR:$Rn, rGPR:$Rm),
22162216 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
2217 Requires<[IsThumb2, HasThumb2DSP]> {
2217 Requires<[IsThumb2, HasDSP]> {
22182218 let Inst{15-12} = 0b1111;
22192219 }
22202220 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
22212221 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
22222222 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
2223 Requires<[IsThumb2, HasThumb2DSP]>;
2223 Requires<[IsThumb2, HasDSP]>;
22242224
22252225 // Signed/Unsigned saturate.
22262226 class T2SatI
22532253 def t2SSAT16: T2SatI<
22542254 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
22552255 "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
2256 Requires<[IsThumb2, HasThumb2DSP]> {
2256 Requires<[IsThumb2, HasDSP]> {
22572257 let Inst{31-27} = 0b11110;
22582258 let Inst{25-22} = 0b1100;
22592259 let Inst{20} = 0;
22772277 def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins imm0_15:$sat_imm, rGPR:$Rn),
22782278 NoItinerary,
22792279 "usat16", "\t$Rd, $sat_imm, $Rn", []>,
2280 Requires<[IsThumb2, HasThumb2DSP]> {
2280 Requires<[IsThumb2, HasDSP]> {
22812281 let Inst{31-22} = 0b1111001110;
22822282 let Inst{20} = 0;
22832283 let Inst{15} = 0;
26042604 (outs rGPR:$RdLo, rGPR:$RdHi),
26052605 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
26062606 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2607 Requires<[IsThumb2, HasThumb2DSP]>;
2607 Requires<[IsThumb2, HasDSP]>;
26082608 } // hasSideEffects
26092609
26102610 // Rounding variants of the below included for disassembly only
26132613 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
26142614 "smmul", "\t$Rd, $Rn, $Rm",
26152615 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
2616 Requires<[IsThumb2, HasThumb2DSP]> {
2616 Requires<[IsThumb2, HasDSP]> {
26172617 let Inst{31-27} = 0b11111;
26182618 let Inst{26-23} = 0b0110;
26192619 let Inst{22-20} = 0b101;
26232623
26242624 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
26252625 "smmulr", "\t$Rd, $Rn, $Rm", []>,
2626 Requires<[IsThumb2, HasThumb2DSP]> {
2626 Requires<[IsThumb2, HasDSP]> {
26272627 let Inst{31-27} = 0b11111;
26282628 let Inst{26-23} = 0b0110;
26292629 let Inst{22-20} = 0b101;
26352635 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
26362636 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
26372637 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
2638 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2638 Requires<[IsThumb2, HasDSP, UseMulOps]> {
26392639 let Inst{31-27} = 0b11111;
26402640 let Inst{26-23} = 0b0110;
26412641 let Inst{22-20} = 0b101;
26452645 def t2SMMLAR: T2FourReg<
26462646 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
26472647 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
2648 Requires<[IsThumb2, HasThumb2DSP]> {
2648 Requires<[IsThumb2, HasDSP]> {
26492649 let Inst{31-27} = 0b11111;
26502650 let Inst{26-23} = 0b0110;
26512651 let Inst{22-20} = 0b101;
26562656 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
26572657 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
26582658 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
2659 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2659 Requires<[IsThumb2, HasDSP, UseMulOps]> {
26602660 let Inst{31-27} = 0b11111;
26612661 let Inst{26-23} = 0b0110;
26622662 let Inst{22-20} = 0b110;
26662666 def t2SMMLSR:T2FourReg<
26672667 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
26682668 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
2669 Requires<[IsThumb2, HasThumb2DSP]> {
2669 Requires<[IsThumb2, HasDSP]> {
26702670 let Inst{31-27} = 0b11111;
26712671 let Inst{26-23} = 0b0110;
26722672 let Inst{22-20} = 0b110;
26782678 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
26792679 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
26802680 (sext_inreg rGPR:$Rm, i16)))]>,
2681 Requires<[IsThumb2, HasThumb2DSP]> {
2681 Requires<[IsThumb2, HasDSP]> {
26822682 let Inst{31-27} = 0b11111;
26832683 let Inst{26-23} = 0b0110;
26842684 let Inst{22-20} = 0b001;
26912691 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
26922692 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
26932693 (sra rGPR:$Rm, (i32 16))))]>,
2694 Requires<[IsThumb2, HasThumb2DSP]> {
2694 Requires<[IsThumb2, HasDSP]> {
26952695 let Inst{31-27} = 0b11111;
26962696 let Inst{26-23} = 0b0110;
26972697 let Inst{22-20} = 0b001;
27042704 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
27052705 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
27062706 (sext_inreg rGPR:$Rm, i16)))]>,
2707 Requires<[IsThumb2, HasThumb2DSP]> {
2707 Requires<[IsThumb2, HasDSP]> {
27082708 let Inst{31-27} = 0b11111;
27092709 let Inst{26-23} = 0b0110;
27102710 let Inst{22-20} = 0b001;
27172717 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
27182718 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
27192719 (sra rGPR:$Rm, (i32 16))))]>,
2720 Requires<[IsThumb2, HasThumb2DSP]> {
2720 Requires<[IsThumb2, HasDSP]> {
27212721 let Inst{31-27} = 0b11111;
27222722 let Inst{26-23} = 0b0110;
27232723 let Inst{22-20} = 0b001;
27292729 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
27302730 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
27312731 []>,
2732 Requires<[IsThumb2, HasThumb2DSP]> {
2732 Requires<[IsThumb2, HasDSP]> {
27332733 let Inst{31-27} = 0b11111;
27342734 let Inst{26-23} = 0b0110;
27352735 let Inst{22-20} = 0b011;
27412741 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
27422742 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
27432743 []>,
2744 Requires<[IsThumb2, HasThumb2DSP]> {
2744 Requires<[IsThumb2, HasDSP]> {
27452745 let Inst{31-27} = 0b11111;
27462746 let Inst{26-23} = 0b0110;
27472747 let Inst{22-20} = 0b011;
27592759 [(set rGPR:$Rd, (add rGPR:$Ra,
27602760 (opnode (sext_inreg rGPR:$Rn, i16),
27612761 (sext_inreg rGPR:$Rm, i16))))]>,
2762 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2762 Requires<[IsThumb2, HasDSP, UseMulOps]> {
27632763 let Inst{31-27} = 0b11111;
27642764 let Inst{26-23} = 0b0110;
27652765 let Inst{22-20} = 0b001;
27722772 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
27732773 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
27742774 (sra rGPR:$Rm, (i32 16)))))]>,
2775 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2775 Requires<[IsThumb2, HasDSP, UseMulOps]> {
27762776 let Inst{31-27} = 0b11111;
27772777 let Inst{26-23} = 0b0110;
27782778 let Inst{22-20} = 0b001;
27852785 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
27862786 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
27872787 (sext_inreg rGPR:$Rm, i16))))]>,
2788 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2788 Requires<[IsThumb2, HasDSP, UseMulOps]> {
27892789 let Inst{31-27} = 0b11111;
27902790 let Inst{26-23} = 0b0110;
27912791 let Inst{22-20} = 0b001;
27982798 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
27992799 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
28002800 (sra rGPR:$Rm, (i32 16)))))]>,
2801 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2801 Requires<[IsThumb2, HasDSP, UseMulOps]> {
28022802 let Inst{31-27} = 0b11111;
28032803 let Inst{26-23} = 0b0110;
28042804 let Inst{22-20} = 0b001;
28102810 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
28112811 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
28122812 []>,
2813 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2813 Requires<[IsThumb2, HasDSP, UseMulOps]> {
28142814 let Inst{31-27} = 0b11111;
28152815 let Inst{26-23} = 0b0110;
28162816 let Inst{22-20} = 0b011;
28222822 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
28232823 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
28242824 []>,
2825 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2825 Requires<[IsThumb2, HasDSP, UseMulOps]> {
28262826 let Inst{31-27} = 0b11111;
28272827 let Inst{26-23} = 0b0110;
28282828 let Inst{22-20} = 0b011;
28382838 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
28392839 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
28402840 [/* For disassembly only; pattern left blank */]>,
2841 Requires<[IsThumb2, HasThumb2DSP]>;
2841 Requires<[IsThumb2, HasDSP]>;
28422842 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
28432843 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
28442844 [/* For disassembly only; pattern left blank */]>,
2845 Requires<[IsThumb2, HasThumb2DSP]>;
2845 Requires<[IsThumb2, HasDSP]>;
28462846 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
28472847 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
28482848 [/* For disassembly only; pattern left blank */]>,
2849 Requires<[IsThumb2, HasThumb2DSP]>;
2849 Requires<[IsThumb2, HasDSP]>;
28502850 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
28512851 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
28522852 [/* For disassembly only; pattern left blank */]>,
2853 Requires<[IsThumb2, HasThumb2DSP]>;
2853 Requires<[IsThumb2, HasDSP]>;
28542854
28552855 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
28562856 def t2SMUAD: T2ThreeReg_mac<
28572857 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
28582858 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
2859 Requires<[IsThumb2, HasThumb2DSP]> {
2859 Requires<[IsThumb2, HasDSP]> {
28602860 let Inst{15-12} = 0b1111;
28612861 }
28622862 def t2SMUADX:T2ThreeReg_mac<
28632863 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
28642864 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
2865 Requires<[IsThumb2, HasThumb2DSP]> {
2865 Requires<[IsThumb2, HasDSP]> {
28662866 let Inst{15-12} = 0b1111;
28672867 }
28682868 def t2SMUSD: T2ThreeReg_mac<
28692869 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
28702870 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
2871 Requires<[IsThumb2, HasThumb2DSP]> {
2871 Requires<[IsThumb2, HasDSP]> {
28722872 let Inst{15-12} = 0b1111;
28732873 }
28742874 def t2SMUSDX:T2ThreeReg_mac<
28752875 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
28762876 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
2877 Requires<[IsThumb2, HasThumb2DSP]> {
2877 Requires<[IsThumb2, HasDSP]> {
28782878 let Inst{15-12} = 0b1111;
28792879 }
28802880 def t2SMLAD : T2FourReg_mac<
28812881 0, 0b010, 0b0000, (outs rGPR:$Rd),
28822882 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
28832883 "\t$Rd, $Rn, $Rm, $Ra", []>,
2884 Requires<[IsThumb2, HasThumb2DSP]>;
2884 Requires<[IsThumb2, HasDSP]>;
28852885 def t2SMLADX : T2FourReg_mac<
28862886 0, 0b010, 0b0001, (outs rGPR:$Rd),
28872887 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
28882888 "\t$Rd, $Rn, $Rm, $Ra", []>,
2889 Requires<[IsThumb2, HasThumb2DSP]>;
2889 Requires<[IsThumb2, HasDSP]>;
28902890 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
28912891 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
28922892 "\t$Rd, $Rn, $Rm, $Ra", []>,
2893 Requires<[IsThumb2, HasThumb2DSP]>;
2893 Requires<[IsThumb2, HasDSP]>;
28942894 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
28952895 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
28962896 "\t$Rd, $Rn, $Rm, $Ra", []>,
2897 Requires<[IsThumb2, HasThumb2DSP]>;
2897 Requires<[IsThumb2, HasDSP]>;
28982898 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
28992899 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald",
29002900 "\t$Ra, $Rd, $Rn, $Rm", []>,
2901 Requires<[IsThumb2, HasThumb2DSP]>;
2901 Requires<[IsThumb2, HasDSP]>;
29022902 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
29032903 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaldx",
29042904 "\t$Ra, $Rd, $Rn, $Rm", []>,
2905 Requires<[IsThumb2, HasThumb2DSP]>;
2905 Requires<[IsThumb2, HasDSP]>;
29062906 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
29072907 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlsld",
29082908 "\t$Ra, $Rd, $Rn, $Rm", []>,
2909 Requires<[IsThumb2, HasThumb2DSP]>;
2909 Requires<[IsThumb2, HasDSP]>;
29102910 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
29112911 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
29122912 "\t$Ra, $Rd, $Rn, $Rm", []>,
2913 Requires<[IsThumb2, HasThumb2DSP]>;
2913 Requires<[IsThumb2, HasDSP]>;
29142914
29152915 //===----------------------------------------------------------------------===//
29162916 // Division Instructions.
146146 HasCRC = false;
147147 HasZeroCycleZeroing = false;
148148 StrictAlign = false;
149 Thumb2DSP = false;
149 HasDSP = false;
150150 UseNaClTrap = false;
151151 GenLongCalls = false;
152152 UnsafeFPMath = false;
198198 /// blocks to conform to ARMv8 rule.
199199 bool RestrictIT;
200200
201 /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
202 /// and such) instructions in Thumb2 code.
203 bool Thumb2DSP;
201 /// HasDSP - If true, the subtarget supports the DSP (saturating arith
202 /// and such) instructions.
203 bool HasDSP;
204204
205205 /// NaCl TRAP instruction is generated instead of the regular TRAP.
206206 bool UseNaClTrap;
342342 bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
343343 bool hasRAS() const { return HasRAS; }
344344 bool hasMPExtension() const { return HasMPExtension; }
345 bool hasThumb2DSP() const { return Thumb2DSP; }
345 bool hasDSP() const { return HasDSP; }
346346 bool useNaClTrap() const { return UseNaClTrap; }
347347 bool genLongCalls() const { return GenLongCalls; }
348348
271271 bool hasARM() const {
272272 return !STI.getFeatureBits()[ARM::FeatureNoARM];
273273 }
274 bool hasThumb2DSP() const {
275 return STI.getFeatureBits()[ARM::FeatureDSPThumb2];
274 bool hasDSP() const {
275 return STI.getFeatureBits()[ARM::FeatureDSP];
276276 }
277277 bool hasD16() const {
278278 return STI.getFeatureBits()[ARM::FeatureD16];
39713971 if (FlagsVal == ~0U)
39723972 return MatchOperand_NoMatch;
39733973
3974 if (!hasThumb2DSP() && (FlagsVal & 0x400))
3974 if (!hasDSP() && (FlagsVal & 0x400))
39753975 // The _g and _nzcvqg versions are only valid if the DSP extension is
39763976 // available.
39773977 return MatchOperand_NoMatch;
41104110 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
41114111 // only if the processor includes the DSP extension.
41124112 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4113 (!(FeatureBits[ARM::FeatureDSPThumb2]) && (Mask & 1)))
4113 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
41144114 S = MCDisassembler::SoftFail;
41154115 }
41164116 }
803803 unsigned Opcode = MI->getOpcode();
804804
805805 // For writes, handle extended mask bits if the DSP extension is present.
806 if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSPThumb2]) {
806 if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSP]) {
807807 switch (SYSm) {
808808 case 0x400:
809809 O << "apsr_g";
140140 llvm_unreachable("invalid sub-architecture for ARM");
141141 case Triple::ARMSubArch_v8:
142142 if (NoCPU)
143 // v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
143 // v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSP,
144144 // FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
145145 // FeatureT2XtPk, FeatureCrypto, FeatureCRC
146146 ARMArchFeature = "+v8,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,"
151151 break;
152152 case Triple::ARMSubArch_v8_1a:
153153 if (NoCPU)
154 // v8.1a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
154 // v8.1a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSP,
155155 // FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
156156 // FeatureT2XtPk, FeatureCrypto, FeatureCRC, FeatureV8_1a
157157 ARMArchFeature = "+v8.1a,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,"
171171 break;
172172 case Triple::ARMSubArch_v7em:
173173 if (NoCPU)
174 // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
174 // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSP,
175175 // FeatureT2XtPk, FeatureMClass
176176 ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,+t2xtpk,+mclass";
177177 else
180180 break;
181181 case Triple::ARMSubArch_v7s:
182182 if (NoCPU)
183 // v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureHasRAS
183 // v7s: FeatureNEON, FeatureDB, FeatureDSP, FeatureHasRAS
184184 // Swift
185185 ARMArchFeature = "+v7,+swift,+neon,+db,+t2dsp,+ras";
186186 else
193193 // the "minimum" feature set and use CPU string to figure out the exact
194194 // features.
195195 if (NoCPU)
196 // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
196 // v7a: FeatureNEON, FeatureDB, FeatureDSP, FeatureT2XtPk
197197 ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
198198 else
199199 // Use CPU to figure out the exact features.