llvm.org GIT mirror llvm / c8478d8
Change the 'isStore' inferrer to look for 'SDNPMayStore' instead of "ISD::STORE". This allows us to mark target-specific dag nodes as storing (such as ppc byteswap stores). This allows us to remove more explicit isStore flags from the .td files. Finally, add a warning for when a .td file contains an explicit isStore and tblgen is able to infer it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45654 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 11 years ago
10 changed file(s) with 248 addition(s) and 228 deletion(s). Raw diff Collapse all Expand all
3737
3838
3939 //3.3.1
40 class MForm opcode, bit store, bit load, string asmstr, list pattern, InstrItinClass itin>
40 class MForm opcode, bit load, string asmstr, list pattern, InstrItinClass itin>
4141 : InstAlpha {
4242 let Pattern = pattern;
43 let isStore = store;
4443 let isLoad = load;
4544 let Defs = [R28]; //We may use this for frame index calculations, so reserve it here
4645
411411
412412
413413 let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in {
414 def LDQ : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)",
414 def LDQ : MForm<0x29, 1, "ldq $RA,$DISP($RB)",
415415 [(set GPRC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))], s_ild>;
416 def LDQr : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)\t\t!gprellow",
416 def LDQr : MForm<0x29, 1, "ldq $RA,$DISP($RB)\t\t!gprellow",
417417 [(set GPRC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_ild>;
418 def LDL : MForm<0x28, 0, 1, "ldl $RA,$DISP($RB)",
418 def LDL : MForm<0x28, 1, "ldl $RA,$DISP($RB)",
419419 [(set GPRC:$RA, (sextloadi32 (add GPRC:$RB, immSExt16:$DISP)))], s_ild>;
420 def LDLr : MForm<0x28, 0, 1, "ldl $RA,$DISP($RB)\t\t!gprellow",
420 def LDLr : MForm<0x28, 1, "ldl $RA,$DISP($RB)\t\t!gprellow",
421421 [(set GPRC:$RA, (sextloadi32 (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_ild>;
422 def LDBU : MForm<0x0A, 0, 1, "ldbu $RA,$DISP($RB)",
422 def LDBU : MForm<0x0A, 1, "ldbu $RA,$DISP($RB)",
423423 [(set GPRC:$RA, (zextloadi8 (add GPRC:$RB, immSExt16:$DISP)))], s_ild>;
424 def LDBUr : MForm<0x0A, 0, 1, "ldbu $RA,$DISP($RB)\t\t!gprellow",
424 def LDBUr : MForm<0x0A, 1, "ldbu $RA,$DISP($RB)\t\t!gprellow",
425425 [(set GPRC:$RA, (zextloadi8 (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_ild>;
426 def LDWU : MForm<0x0C, 0, 1, "ldwu $RA,$DISP($RB)",
426 def LDWU : MForm<0x0C, 1, "ldwu $RA,$DISP($RB)",
427427 [(set GPRC:$RA, (zextloadi16 (add GPRC:$RB, immSExt16:$DISP)))], s_ild>;
428 def LDWUr : MForm<0x0C, 0, 1, "ldwu $RA,$DISP($RB)\t\t!gprellow",
428 def LDWUr : MForm<0x0C, 1, "ldwu $RA,$DISP($RB)\t\t!gprellow",
429429 [(set GPRC:$RA, (zextloadi16 (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_ild>;
430430 }
431431
432432
433433 let OutOperandList = (ops), InOperandList = (ops GPRC:$RA, s64imm:$DISP, GPRC:$RB) in {
434 def STB : MForm<0x0E, 1, 0, "stb $RA,$DISP($RB)",
434 def STB : MForm<0x0E, 0, "stb $RA,$DISP($RB)",
435435 [(truncstorei8 GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>;
436 def STBr : MForm<0x0E, 1, 0, "stb $RA,$DISP($RB)\t\t!gprellow",
436 def STBr : MForm<0x0E, 0, "stb $RA,$DISP($RB)\t\t!gprellow",
437437 [(truncstorei8 GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>;
438 def STW : MForm<0x0D, 1, 0, "stw $RA,$DISP($RB)",
438 def STW : MForm<0x0D, 0, "stw $RA,$DISP($RB)",
439439 [(truncstorei16 GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>;
440 def STWr : MForm<0x0D, 1, 0, "stw $RA,$DISP($RB)\t\t!gprellow",
440 def STWr : MForm<0x0D, 0, "stw $RA,$DISP($RB)\t\t!gprellow",
441441 [(truncstorei16 GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>;
442 def STL : MForm<0x2C, 1, 0, "stl $RA,$DISP($RB)",
442 def STL : MForm<0x2C, 0, "stl $RA,$DISP($RB)",
443443 [(truncstorei32 GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>;
444 def STLr : MForm<0x2C, 1, 0, "stl $RA,$DISP($RB)\t\t!gprellow",
444 def STLr : MForm<0x2C, 0, "stl $RA,$DISP($RB)\t\t!gprellow",
445445 [(truncstorei32 GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>;
446 def STQ : MForm<0x2D, 1, 0, "stq $RA,$DISP($RB)",
446 def STQ : MForm<0x2D, 0, "stq $RA,$DISP($RB)",
447447 [(store GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>;
448 def STQr : MForm<0x2D, 1, 0, "stq $RA,$DISP($RB)\t\t!gprellow",
448 def STQr : MForm<0x2D, 0, "stq $RA,$DISP($RB)\t\t!gprellow",
449449 [(store GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>;
450450 }
451451
452452 //Load address
453453 let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in {
454 def LDA : MForm<0x08, 0, 0, "lda $RA,$DISP($RB)",
454 def LDA : MForm<0x08, 0, "lda $RA,$DISP($RB)",
455455 [(set GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_lda>;
456 def LDAr : MForm<0x08, 0, 0, "lda $RA,$DISP($RB)\t\t!gprellow",
456 def LDAr : MForm<0x08, 0, "lda $RA,$DISP($RB)\t\t!gprellow",
457457 [(set GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_lda>; //Load address
458 def LDAH : MForm<0x09, 0, 0, "ldah $RA,$DISP($RB)",
458 def LDAH : MForm<0x09, 0, "ldah $RA,$DISP($RB)",
459459 [], s_lda>; //Load address high
460 def LDAHr : MForm<0x09, 0, 0, "ldah $RA,$DISP($RB)\t\t!gprelhigh",
460 def LDAHr : MForm<0x09, 0, "ldah $RA,$DISP($RB)\t\t!gprelhigh",
461461 [(set GPRC:$RA, (Alpha_gprelhi tglobaladdr:$DISP, GPRC:$RB))], s_lda>; //Load address high
462462 }
463463
464464 let OutOperandList = (ops), InOperandList = (ops F4RC:$RA, s64imm:$DISP, GPRC:$RB) in {
465 def STS : MForm<0x26, 1, 0, "sts $RA,$DISP($RB)",
465 def STS : MForm<0x26, 0, "sts $RA,$DISP($RB)",
466466 [(store F4RC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_fst>;
467 def STSr : MForm<0x26, 1, 0, "sts $RA,$DISP($RB)\t\t!gprellow",
467 def STSr : MForm<0x26, 0, "sts $RA,$DISP($RB)\t\t!gprellow",
468468 [(store F4RC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_fst>;
469469 }
470470 let OutOperandList = (ops F4RC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in {
471 def LDS : MForm<0x22, 0, 1, "lds $RA,$DISP($RB)",
471 def LDS : MForm<0x22, 1, "lds $RA,$DISP($RB)",
472472 [(set F4RC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))], s_fld>;
473 def LDSr : MForm<0x22, 0, 1, "lds $RA,$DISP($RB)\t\t!gprellow",
473 def LDSr : MForm<0x22, 1, "lds $RA,$DISP($RB)\t\t!gprellow",
474474 [(set F4RC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_fld>;
475475 }
476476 let OutOperandList = (ops), InOperandList = (ops F8RC:$RA, s64imm:$DISP, GPRC:$RB) in {
477 def STT : MForm<0x27, 1, 0, "stt $RA,$DISP($RB)",
477 def STT : MForm<0x27, 0, "stt $RA,$DISP($RB)",
478478 [(store F8RC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_fst>;
479 def STTr : MForm<0x27, 1, 0, "stt $RA,$DISP($RB)\t\t!gprellow",
479 def STTr : MForm<0x27, 0, "stt $RA,$DISP($RB)\t\t!gprellow",
480480 [(store F8RC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_fst>;
481481 }
482482 let OutOperandList = (ops F8RC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in {
483 def LDT : MForm<0x23, 0, 1, "ldt $RA,$DISP($RB)",
483 def LDT : MForm<0x23, 1, "ldt $RA,$DISP($RB)",
484484 [(set F8RC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))], s_fld>;
485 def LDTr : MForm<0x23, 0, 1, "ldt $RA,$DISP($RB)\t\t!gprellow",
485 def LDTr : MForm<0x23, 1, "ldt $RA,$DISP($RB)\t\t!gprellow",
486486 [(set F8RC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_fld>;
487487 }
488488
556556
557557 //load address, rellocated gpdist form
558558 let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s16imm:$DISP, GPRC:$RB, s16imm:$NUM) in {
559 def LDAg : MForm<0x08, 0, 1, "lda $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>; //Load address
560 def LDAHg : MForm<0x09, 0, 1, "ldah $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>; //Load address
559 def LDAg : MForm<0x08, 1, "lda $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>; //Load address
560 def LDAHg : MForm<0x09, 1, "ldah $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>; //Load address
561561 }
562562
563563 //Load quad, rellocated literal form
564564 let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in
565 def LDQl : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)\t\t!literal",
565 def LDQl : MForm<0x29, 1, "ldq $RA,$DISP($RB)\t\t!literal",
566566 [(set GPRC:$RA, (Alpha_rellit tglobaladdr:$DISP, GPRC:$RB))], s_ild>;
567567 def : Pat<(Alpha_rellit texternalsym:$ext, GPRC:$RB),
568568 (LDQl texternalsym:$ext, GPRC:$RB)>;
256256 // Stores:
257257 //===----------------------------------------------------------------------===//
258258
259 let isStore = 1 in {
260 def STQDv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
261 "stqd\t$rT, $src", LoadStore,
262 [(store (v16i8 VECREG:$rT), dform_addr:$src)]>;
263
264 def STQDv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
265 "stqd\t$rT, $src", LoadStore,
266 [(store (v8i16 VECREG:$rT), dform_addr:$src)]>;
267
268 def STQDv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
269 "stqd\t$rT, $src", LoadStore,
270 [(store (v4i32 VECREG:$rT), dform_addr:$src)]>;
271
272 def STQDv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
273 "stqd\t$rT, $src", LoadStore,
274 [(store (v2i64 VECREG:$rT), dform_addr:$src)]>;
275
276 def STQDv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
277 "stqd\t$rT, $src", LoadStore,
278 [(store (v4f32 VECREG:$rT), dform_addr:$src)]>;
279
280 def STQDv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
281 "stqd\t$rT, $src", LoadStore,
282 [(store (v2f64 VECREG:$rT), dform_addr:$src)]>;
283
284 def STQDr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, memri10:$src),
285 "stqd\t$rT, $src", LoadStore,
286 [(store GPRC:$rT, dform_addr:$src)]>;
287
288 def STQDr64 : RI10Form<0b00100100, (outs), (ins R64C:$rT, memri10:$src),
289 "stqd\t$rT, $src", LoadStore,
290 [(store R64C:$rT, dform_addr:$src)]>;
291
292 def STQDr32 : RI10Form<0b00100100, (outs), (ins R32C:$rT, memri10:$src),
293 "stqd\t$rT, $src", LoadStore,
294 [(store R32C:$rT, dform_addr:$src)]>;
295
296 // Floating Point
297 def STQDf32 : RI10Form<0b00100100, (outs), (ins R32FP:$rT, memri10:$src),
298 "stqd\t$rT, $src", LoadStore,
299 [(store R32FP:$rT, dform_addr:$src)]>;
300
301 def STQDf64 : RI10Form<0b00100100, (outs), (ins R64FP:$rT, memri10:$src),
302 "stqd\t$rT, $src", LoadStore,
303 [(store R64FP:$rT, dform_addr:$src)]>;
304
305 def STQDr16 : RI10Form<0b00100100, (outs), (ins R16C:$rT, memri10:$src),
306 "stqd\t$rT, $src", LoadStore,
307 [(store R16C:$rT, dform_addr:$src)]>;
308
309 def STQDr8 : RI10Form<0b00100100, (outs), (ins R8C:$rT, memri10:$src),
310 "stqd\t$rT, $src", LoadStore,
311 [(store R8C:$rT, dform_addr:$src)]>;
312
313 def STQAv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
314 "stqa\t$rT, $src", LoadStore,
315 [(store (v16i8 VECREG:$rT), aform_addr:$src)]>;
316
317 def STQAv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
318 "stqa\t$rT, $src", LoadStore,
319 [(store (v8i16 VECREG:$rT), aform_addr:$src)]>;
320
321 def STQAv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
322 "stqa\t$rT, $src", LoadStore,
323 [(store (v4i32 VECREG:$rT), aform_addr:$src)]>;
324
325 def STQAv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
326 "stqa\t$rT, $src", LoadStore,
327 [(store (v2i64 VECREG:$rT), aform_addr:$src)]>;
328
329 def STQAv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
330 "stqa\t$rT, $src", LoadStore,
331 [(store (v4f32 VECREG:$rT), aform_addr:$src)]>;
332
333 def STQAv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
334 "stqa\t$rT, $src", LoadStore,
335 [(store (v2f64 VECREG:$rT), aform_addr:$src)]>;
336
337 def STQAr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, addr256k:$src),
338 "stqa\t$rT, $src", LoadStore,
339 [(store GPRC:$rT, aform_addr:$src)]>;
340
341 def STQAr64 : RI10Form<0b00100100, (outs), (ins R64C:$rT, addr256k:$src),
342 "stqa\t$rT, $src", LoadStore,
343 [(store R64C:$rT, aform_addr:$src)]>;
344
345 def STQAr32 : RI10Form<0b00100100, (outs), (ins R32C:$rT, addr256k:$src),
346 "stqa\t$rT, $src", LoadStore,
347 [(store R32C:$rT, aform_addr:$src)]>;
348
349 // Floating Point
350 def STQAf32 : RI10Form<0b00100100, (outs), (ins R32FP:$rT, addr256k:$src),
351 "stqa\t$rT, $src", LoadStore,
352 [(store R32FP:$rT, aform_addr:$src)]>;
353
354 def STQAf64 : RI10Form<0b00100100, (outs), (ins R64FP:$rT, addr256k:$src),
355 "stqa\t$rT, $src", LoadStore,
356 [(store R64FP:$rT, aform_addr:$src)]>;
357
358 def STQAr16 : RI10Form<0b00100100, (outs), (ins R16C:$rT, addr256k:$src),
359 "stqa\t$rT, $src", LoadStore,
360 [(store R16C:$rT, aform_addr:$src)]>;
361
362 def STQAr8 : RI10Form<0b00100100, (outs), (ins R8C:$rT, addr256k:$src),
363 "stqa\t$rT, $src", LoadStore,
364 [(store R8C:$rT, aform_addr:$src)]>;
365
366 def STQXv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
367 "stqx\t$rT, $src", LoadStore,
368 [(store (v16i8 VECREG:$rT), xform_addr:$src)]>;
369
370 def STQXv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
371 "stqx\t$rT, $src", LoadStore,
372 [(store (v8i16 VECREG:$rT), xform_addr:$src)]>;
373
374 def STQXv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
375 "stqx\t$rT, $src", LoadStore,
376 [(store (v4i32 VECREG:$rT), xform_addr:$src)]>;
377
378 def STQXv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
379 "stqx\t$rT, $src", LoadStore,
380 [(store (v2i64 VECREG:$rT), xform_addr:$src)]>;
381
382 def STQXv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
383 "stqx\t$rT, $src", LoadStore,
384 [(store (v4f32 VECREG:$rT), xform_addr:$src)]>;
385
386 def STQXv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
387 "stqx\t$rT, $src", LoadStore,
388 [(store (v2f64 VECREG:$rT), xform_addr:$src)]>;
389
390 def STQXr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, memrr:$src),
391 "stqx\t$rT, $src", LoadStore,
392 [(store GPRC:$rT, xform_addr:$src)]>;
393
394 def STQXr64:
395 RI10Form<0b00100100, (outs), (ins R64C:$rT, memrr:$src),
396 "stqx\t$rT, $src", LoadStore,
397 [(store R64C:$rT, xform_addr:$src)]>;
398
399 def STQXr32:
400 RI10Form<0b00100100, (outs), (ins R32C:$rT, memrr:$src),
401 "stqx\t$rT, $src", LoadStore,
402 [(store R32C:$rT, xform_addr:$src)]>;
403
404 // Floating Point
405 def STQXf32:
406 RI10Form<0b00100100, (outs), (ins R32FP:$rT, memrr:$src),
407 "stqx\t$rT, $src", LoadStore,
408 [(store R32FP:$rT, xform_addr:$src)]>;
409
410 def STQXf64:
411 RI10Form<0b00100100, (outs), (ins R64FP:$rT, memrr:$src),
412 "stqx\t$rT, $src", LoadStore,
413 [(store R64FP:$rT, xform_addr:$src)]>;
414
415 def STQXr16:
416 RI10Form<0b00100100, (outs), (ins R16C:$rT, memrr:$src),
417 "stqx\t$rT, $src", LoadStore,
418 [(store R16C:$rT, xform_addr:$src)]>;
419
420 def STQXr8:
421 RI10Form<0b00100100, (outs), (ins R8C:$rT, memrr:$src),
422 "stqx\t$rT, $src", LoadStore,
423 [(store R8C:$rT, xform_addr:$src)]>;
259 def STQDv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
260 "stqd\t$rT, $src", LoadStore,
261 [(store (v16i8 VECREG:$rT), dform_addr:$src)]>;
262
263 def STQDv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
264 "stqd\t$rT, $src", LoadStore,
265 [(store (v8i16 VECREG:$rT), dform_addr:$src)]>;
266
267 def STQDv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
268 "stqd\t$rT, $src", LoadStore,
269 [(store (v4i32 VECREG:$rT), dform_addr:$src)]>;
270
271 def STQDv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
272 "stqd\t$rT, $src", LoadStore,
273 [(store (v2i64 VECREG:$rT), dform_addr:$src)]>;
274
275 def STQDv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
276 "stqd\t$rT, $src", LoadStore,
277 [(store (v4f32 VECREG:$rT), dform_addr:$src)]>;
278
279 def STQDv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
280 "stqd\t$rT, $src", LoadStore,
281 [(store (v2f64 VECREG:$rT), dform_addr:$src)]>;
282
283 def STQDr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, memri10:$src),
284 "stqd\t$rT, $src", LoadStore,
285 [(store GPRC:$rT, dform_addr:$src)]>;
286
287 def STQDr64 : RI10Form<0b00100100, (outs), (ins R64C:$rT, memri10:$src),
288 "stqd\t$rT, $src", LoadStore,
289 [(store R64C:$rT, dform_addr:$src)]>;
290
291 def STQDr32 : RI10Form<0b00100100, (outs), (ins R32C:$rT, memri10:$src),
292 "stqd\t$rT, $src", LoadStore,
293 [(store R32C:$rT, dform_addr:$src)]>;
294
295 // Floating Point
296 def STQDf32 : RI10Form<0b00100100, (outs), (ins R32FP:$rT, memri10:$src),
297 "stqd\t$rT, $src", LoadStore,
298 [(store R32FP:$rT, dform_addr:$src)]>;
299
300 def STQDf64 : RI10Form<0b00100100, (outs), (ins R64FP:$rT, memri10:$src),
301 "stqd\t$rT, $src", LoadStore,
302 [(store R64FP:$rT, dform_addr:$src)]>;
303
304 def STQDr16 : RI10Form<0b00100100, (outs), (ins R16C:$rT, memri10:$src),
305 "stqd\t$rT, $src", LoadStore,
306 [(store R16C:$rT, dform_addr:$src)]>;
307
308 def STQDr8 : RI10Form<0b00100100, (outs), (ins R8C:$rT, memri10:$src),
309 "stqd\t$rT, $src", LoadStore,
310 [(store R8C:$rT, dform_addr:$src)]>;
311
312 def STQAv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
313 "stqa\t$rT, $src", LoadStore,
314 [(store (v16i8 VECREG:$rT), aform_addr:$src)]>;
315
316 def STQAv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
317 "stqa\t$rT, $src", LoadStore,
318 [(store (v8i16 VECREG:$rT), aform_addr:$src)]>;
319
320 def STQAv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
321 "stqa\t$rT, $src", LoadStore,
322 [(store (v4i32 VECREG:$rT), aform_addr:$src)]>;
323
324 def STQAv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
325 "stqa\t$rT, $src", LoadStore,
326 [(store (v2i64 VECREG:$rT), aform_addr:$src)]>;
327
328 def STQAv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
329 "stqa\t$rT, $src", LoadStore,
330 [(store (v4f32 VECREG:$rT), aform_addr:$src)]>;
331
332 def STQAv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
333 "stqa\t$rT, $src", LoadStore,
334 [(store (v2f64 VECREG:$rT), aform_addr:$src)]>;
335
336 def STQAr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, addr256k:$src),
337 "stqa\t$rT, $src", LoadStore,
338 [(store GPRC:$rT, aform_addr:$src)]>;
339
340 def STQAr64 : RI10Form<0b00100100, (outs), (ins R64C:$rT, addr256k:$src),
341 "stqa\t$rT, $src", LoadStore,
342 [(store R64C:$rT, aform_addr:$src)]>;
343
344 def STQAr32 : RI10Form<0b00100100, (outs), (ins R32C:$rT, addr256k:$src),
345 "stqa\t$rT, $src", LoadStore,
346 [(store R32C:$rT, aform_addr:$src)]>;
347
348 // Floating Point
349 def STQAf32 : RI10Form<0b00100100, (outs), (ins R32FP:$rT, addr256k:$src),
350 "stqa\t$rT, $src", LoadStore,
351 [(store R32FP:$rT, aform_addr:$src)]>;
352
353 def STQAf64 : RI10Form<0b00100100, (outs), (ins R64FP:$rT, addr256k:$src),
354 "stqa\t$rT, $src", LoadStore,
355 [(store R64FP:$rT, aform_addr:$src)]>;
356
357 def STQAr16 : RI10Form<0b00100100, (outs), (ins R16C:$rT, addr256k:$src),
358 "stqa\t$rT, $src", LoadStore,
359 [(store R16C:$rT, aform_addr:$src)]>;
360
361 def STQAr8 : RI10Form<0b00100100, (outs), (ins R8C:$rT, addr256k:$src),
362 "stqa\t$rT, $src", LoadStore,
363 [(store R8C:$rT, aform_addr:$src)]>;
364
365 def STQXv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
366 "stqx\t$rT, $src", LoadStore,
367 [(store (v16i8 VECREG:$rT), xform_addr:$src)]>;
368
369 def STQXv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
370 "stqx\t$rT, $src", LoadStore,
371 [(store (v8i16 VECREG:$rT), xform_addr:$src)]>;
372
373 def STQXv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
374 "stqx\t$rT, $src", LoadStore,
375 [(store (v4i32 VECREG:$rT), xform_addr:$src)]>;
376
377 def STQXv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
378 "stqx\t$rT, $src", LoadStore,
379 [(store (v2i64 VECREG:$rT), xform_addr:$src)]>;
380
381 def STQXv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
382 "stqx\t$rT, $src", LoadStore,
383 [(store (v4f32 VECREG:$rT), xform_addr:$src)]>;
384
385 def STQXv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
386 "stqx\t$rT, $src", LoadStore,
387 [(store (v2f64 VECREG:$rT), xform_addr:$src)]>;
388
389 def STQXr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, memrr:$src),
390 "stqx\t$rT, $src", LoadStore,
391 [(store GPRC:$rT, xform_addr:$src)]>;
392
393 def STQXr64:
394 RI10Form<0b00100100, (outs), (ins R64C:$rT, memrr:$src),
395 "stqx\t$rT, $src", LoadStore,
396 [(store R64C:$rT, xform_addr:$src)]>;
397
398 def STQXr32:
399 RI10Form<0b00100100, (outs), (ins R32C:$rT, memrr:$src),
400 "stqx\t$rT, $src", LoadStore,
401 [(store R32C:$rT, xform_addr:$src)]>;
402
403 // Floating Point
404 def STQXf32:
405 RI10Form<0b00100100, (outs), (ins R32FP:$rT, memrr:$src),
406 "stqx\t$rT, $src", LoadStore,
407 [(store R32FP:$rT, xform_addr:$src)]>;
408
409 def STQXf64:
410 RI10Form<0b00100100, (outs), (ins R64FP:$rT, memrr:$src),
411 "stqx\t$rT, $src", LoadStore,
412 [(store R64FP:$rT, xform_addr:$src)]>;
413
414 def STQXr16:
415 RI10Form<0b00100100, (outs), (ins R16C:$rT, memrr:$src),
416 "stqx\t$rT, $src", LoadStore,
417 [(store R16C:$rT, xform_addr:$src)]>;
418
419 def STQXr8:
420 RI10Form<0b00100100, (outs), (ins R8C:$rT, memrr:$src),
421 "stqx\t$rT, $src", LoadStore,
422 [(store R8C:$rT, xform_addr:$src)]>;
424423
425424 /* Store quadword, PC relative: Not much use at this point in time. Might
426 be useful for relocatable code.
427 def STQR : RI16Form<0b111000100, (outs), (ins VECREG:$rT, s16imm:$disp),
428 "stqr\t$rT, $disp", LoadStore,
429 [(store VECREG:$rT, iaddr:$disp)]>;
430 */
431 }
425 be useful for relocatable code.
426 def STQR : RI16Form<0b111000100, (outs), (ins VECREG:$rT, s16imm:$disp),
427 "stqr\t$rT, $disp", LoadStore,
428 [(store VECREG:$rT, iaddr:$disp)]>;
429 */
432430
433431 //===----------------------------------------------------------------------===//
434432 // Generate Controls for Insertion:
212212 !strconcat(instr_asm, " $dst, $addr"),
213213 [(set CPURegs:$dst, (OpNode addr:$addr))], IILoad>;
214214
215 let isStore = 1 in
216215 class StoreM op, string instr_asm, PatFrag OpNode>:
217216 FI< op,
218217 (outs),
512512 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">,
513513 isPPC64;
514514
515 }
516
517 let isStore = 1, PPC970_Unit = 2 in {
518
515 let isStore = 1 in
519516 def STDUX : XForm_8<31, 181, (outs), (ins G8RC:$rS, memrr:$dst),
520517 "stdux $rS, $dst", LdStSTD,
521518 []>, isPPC64;
522
523519
524520 // STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
525521 def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst),
5151 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
5252 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
5353 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
54 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, [SDNPHasChain]>;
54 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
55 [SDNPHasChain, SDNPMayStore]>;
5556
5657 // This sequence is used for long double->int conversions. It changes the
5758 // bits in the FPSCR which is not modelled.
8788 def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>;
8889
8990 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
90 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, [SDNPHasChain]>;
91 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,
92 [SDNPHasChain, SDNPMayStore]>;
9193
9294 // These are target-independent nodes, but have target-specific formats.
9395 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
118120 [SDNPHasChain, SDNPOptInFlag]>;
119121
120122 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, [SDNPHasChain]>;
121 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, [SDNPHasChain]>;
123 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
124 [SDNPHasChain, SDNPMayStore]>;
122125
123126 // Instructions to support dynamic alloca.
124127 def SDTDynOp : SDTypeProfile<1, 2, []>;
638641 def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB),
639642 "stwux $rS, $rA, $rB", LdStGeneral,
640643 []>;
644 }
641645 def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
642646 "sthbrx $rS, $dst", LdStGeneral,
643647 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i16)]>,
650654 def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
651655 "stfiwx $frS, $dst", LdStUX,
652656 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
653 }
657
654658 def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
655659 "stfsx $frS, $dst", LdStUX,
656660 [(store F4RC:$frS, xaddr:$dst)]>;
188188 def SDNPOutFlag : SDNodeProperty; // Write a flag result
189189 def SDNPInFlag : SDNodeProperty; // Read a flag operand
190190 def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand
191 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'isStore'.
191192
192193 //===----------------------------------------------------------------------===//
193194 // Selection DAG Node definitions.
312313 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
313314 // and truncst (see below).
314315 def ld : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>;
315 def st : SDNode<"ISD::STORE" , SDTStore, [SDNPHasChain]>;
316 def ist : SDNode<"ISD::STORE" , SDTIStore, [SDNPHasChain]>;
316 def st : SDNode<"ISD::STORE" , SDTStore,
317 [SDNPHasChain, SDNPMayStore]>;
318 def ist : SDNode<"ISD::STORE" , SDTIStore,
319 [SDNPHasChain, SDNPMayStore]>;
317320
318321 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
319322 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, 0, []>, []>;
316316 Properties |= 1 << SDNPInFlag;
317317 } else if (PropList[i]->getName() == "SDNPOptInFlag") {
318318 Properties |= 1 << SDNPOptInFlag;
319 } else if (PropList[i]->getName() == "SDNPMayStore") {
320 Properties |= 1 << SDNPMayStore;
319321 } else {
320322 cerr << "Unknown SD Node property '" << PropList[i]->getName()
321323 << "' on node '" << R->getName() << "'!\n";
2929 class CodeGenTarget;
3030
3131 // SelectionDAG node properties.
32 enum SDNP { SDNPCommutative, SDNPAssociative, SDNPHasChain,
33 SDNPOutFlag, SDNPInFlag, SDNPOptInFlag };
32 enum SDNP {
33 SDNPCommutative,
34 SDNPAssociative,
35 SDNPHasChain,
36 SDNPOutFlag,
37 SDNPInFlag,
38 SDNPOptInFlag,
39 SDNPMayStore
40 };
3441
3542 /// getValueType - Return the MVT::ValueType that the specified TableGen record
3643 /// corresponds to.
156156 if (Pattern == 0) return; // No pattern.
157157
158158 // Assume there is no side-effect unless we see one.
159 // FIXME: Enable this.
160 //NeverHasSideEffects = true;
161
159 NeverHasSideEffects = true;
162160
163161 // FIXME: Assume only the first tree is the pattern. The others are clobber
164162 // nodes.
175173 // Get information about the SDNode for the operator.
176174 const SDNodeInfo &OpInfo = CDP.getSDNodeInfo(N->getOperator());
177175
178 // If this is a store node, it obviously stores to memory.
179 if (OpInfo.getEnumName() == "ISD::STORE") {
176 // If node writes to memory, it obviously stores to memory.
177 if (OpInfo.hasProperty(SDNPMayStore)) {
180178 isStore = true;
181
182179 } else if (const CodeGenIntrinsic *IntInfo = N->getIntrinsicInfo(CDP)) {
183180 // If this is an intrinsic, analyze it.
184181 if (IntInfo->ModRef >= CodeGenIntrinsic::WriteArgMem)
195192 void InstrInfoEmitter::InferFromPattern(const CodeGenInstruction &Inst,
196193 bool &isStore, bool &isLoad,
197194 bool &NeverHasSideEffects) {
198 isStore = Inst.isStore;
195 isStore = isLoad = NeverHasSideEffects = false;
196
197 InstAnalyzer(CDP, isStore, isLoad, NeverHasSideEffects).Analyze(Inst.TheDef);
198
199 // InstAnalyzer only correctly analyzes isStore so far.
200 if (Inst.isStore) { // If the .td file explicitly sets isStore, use it.
201 // If we decided that this is a store from the pattern, then the .td file
202 // entry is redundant.
203 if (isStore)
204 fprintf(stderr, "Warning: isStore flag explicitly set on instruction '%s'"
205 " but flag already inferred from pattern.\n",
206 Inst.getName().c_str());
207 isStore = true;
208 }
209
210 // These two override everything.
199211 isLoad = Inst.isLoad;
200212 NeverHasSideEffects = Inst.neverHasSideEffects;
201
202 InstAnalyzer(CDP, isStore, isLoad, NeverHasSideEffects).Analyze(Inst.TheDef);
203
213
214 #if 0
204215 // If the .td file explicitly says there is no side effect, believe it.
205216 if (Inst.neverHasSideEffects)
206217 NeverHasSideEffects = true;
218 #endif
207219 }
208220
209221