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use DebugLoc default ctor instead of DebugLoc::getUnknownLoc() git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100214 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 10 years ago
36 changed file(s) with 133 addition(s) and 159 deletion(s). Raw diff Collapse all Expand all
311311 MachineBasicBlock *FBB,
312312 const SmallVectorImpl &Cond) const {
313313 // FIXME this should probably have a DebugLoc argument
314 DebugLoc dl = DebugLoc::getUnknownLoc();
314 DebugLoc dl;
315315
316316 ARMFunctionInfo *AFI = MBB.getParent()->getInfo();
317317 int BOpc = !AFI->isThumbFunction()
652652 unsigned DestReg, unsigned SrcReg,
653653 const TargetRegisterClass *DestRC,
654654 const TargetRegisterClass *SrcRC) const {
655 DebugLoc DL = DebugLoc::getUnknownLoc();
655 DebugLoc DL;
656656 if (I != MBB.end()) DL = I->getDebugLoc();
657657
658658 // tGPR is used sometimes in ARM instructions that need to avoid using
714714 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
715715 unsigned SrcReg, bool isKill, int FI,
716716 const TargetRegisterClass *RC) const {
717 DebugLoc DL = DebugLoc::getUnknownLoc();
717 DebugLoc DL;
718718 if (I != MBB.end()) DL = I->getDebugLoc();
719719 MachineFunction &MF = *MBB.getParent();
720720 MachineFrameInfo &MFI = *MF.getFrameInfo();
768768 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
769769 unsigned DestReg, int FI,
770770 const TargetRegisterClass *RC) const {
771 DebugLoc DL = DebugLoc::getUnknownLoc();
771 DebugLoc DL;
772772 if (I != MBB.end()) DL = I->getDebugLoc();
773773 MachineFunction &MF = *MBB.getParent();
774774 MachineFrameInfo &MFI = *MF.getFrameInfo();
12761276 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
12771277 unsigned NumBytes = MFI->getStackSize();
12781278 const std::vector &CSI = MFI->getCalleeSavedInfo();
1279 DebugLoc dl = (MBBI != MBB.end() ?
1280 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
1279 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
12811280
12821281 // Determine the sizes of each callee-save spill areas and record which frame
12831282 // belongs to which callee-save spill areas.
398398 // aligned.
399399 assert((Size & 3) == 0 && "CP Entry not multiple of 4 bytes!");
400400 MachineInstr *CPEMI =
401 BuildMI(BB, DebugLoc::getUnknownLoc(), TII->get(ARM::CONSTPOOL_ENTRY))
402 .addImm(i).addConstantPoolIndex(i).addImm(Size);
401 BuildMI(BB, DebugLoc(), TII->get(ARM::CONSTPOOL_ENTRY))
402 .addImm(i).addConstantPoolIndex(i).addImm(Size);
403403 CPEMIs.push_back(CPEMI);
404404
405405 // Add a new CPEntry, but no corresponding CPUser yet.
720720 // There doesn't seem to be meaningful DebugInfo available; this doesn't
721721 // correspond to anything in the source.
722722 unsigned Opc = isThumb ? (isThumb2 ? ARM::t2B : ARM::tB) : ARM::B;
723 BuildMI(OrigBB, DebugLoc::getUnknownLoc(), TII->get(Opc)).addMBB(NewBB);
723 BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB);
724724 NumSplit++;
725725
726726 // Update the CFG. All succs of OrigBB are now succs of NewBB.
11021102 // targets will be exchanged, and the altered branch may be out of
11031103 // range, so the machinery has to know about it.
11041104 int UncondBr = isThumb ? ((isThumb2) ? ARM::t2B : ARM::tB) : ARM::B;
1105 BuildMI(UserMBB, DebugLoc::getUnknownLoc(),
1106 TII->get(UncondBr)).addMBB(NewMBB);
1105 BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB);
11071106 unsigned MaxDisp = getUnconditionalBrDisp(UncondBr);
11081107 ImmBranches.push_back(ImmBranch(&UserMBB->back(),
11091108 MaxDisp, false, UncondBr));
12431242 // Now that we have an island to add the CPE to, clone the original CPE and
12441243 // add it to the island.
12451244 U.HighWaterMark = NewIsland;
1246 U.CPEMI = BuildMI(NewIsland, DebugLoc::getUnknownLoc(),
1247 TII->get(ARM::CONSTPOOL_ENTRY))
1245 U.CPEMI = BuildMI(NewIsland, DebugLoc(), TII->get(ARM::CONSTPOOL_ENTRY))
12481246 .addImm(ID).addConstantPoolIndex(CPI).addImm(Size);
12491247 CPEntries[CPI].push_back(CPEntry(U.CPEMI, ID, 1));
12501248 NumCPEs++;
14451443
14461444 // Insert a new conditional branch and a new unconditional branch.
14471445 // Also update the ImmBranch as well as adding a new entry for the new branch.
1448 BuildMI(MBB, DebugLoc::getUnknownLoc(),
1449 TII->get(MI->getOpcode()))
1446 BuildMI(MBB, DebugLoc(), TII->get(MI->getOpcode()))
14501447 .addMBB(NextBB).addImm(CC).addReg(CCReg);
14511448 Br.MI = &MBB->back();
14521449 BBSizes[MBB->getNumber()] += TII->GetInstSizeInBytes(&MBB->back());
1453 BuildMI(MBB, DebugLoc::getUnknownLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
1450 BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
14541451 BBSizes[MBB->getNumber()] += TII->GetInstSizeInBytes(&MBB->back());
14551452 unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr);
14561453 ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr));
18081805 // There doesn't seem to be meaningful DebugInfo available; this doesn't
18091806 // correspond directly to anything in the source.
18101807 assert (isThumb2 && "Adjusting for TB[BH] but not in Thumb2?");
1811 BuildMI(NewBB, DebugLoc::getUnknownLoc(), TII->get(ARM::t2B)).addMBB(BB);
1808 BuildMI(NewBB, DebugLoc(), TII->get(ARM::t2B)).addMBB(BB);
18121809
18131810 // Update internal data structures to account for the newly inserted MBB.
18141811 MF.RenumberBlocks(NewBB);
3636 unsigned DestReg, unsigned SrcReg,
3737 const TargetRegisterClass *DestRC,
3838 const TargetRegisterClass *SrcRC) const {
39 DebugLoc DL = DebugLoc::getUnknownLoc();
39 DebugLoc DL;
4040 if (I != MBB.end()) DL = I->getDebugLoc();
4141
4242 if (DestRC == ARM::GPRRegisterClass) {
9797 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
9898 unsigned SrcReg, bool isKill, int FI,
9999 const TargetRegisterClass *RC) const {
100 DebugLoc DL = DebugLoc::getUnknownLoc();
100 DebugLoc DL;
101101 if (I != MBB.end()) DL = I->getDebugLoc();
102102
103103 assert((RC == ARM::tGPRRegisterClass ||
124124 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
125125 unsigned DestReg, int FI,
126126 const TargetRegisterClass *RC) const {
127 DebugLoc DL = DebugLoc::getUnknownLoc();
127 DebugLoc DL;
128128 if (I != MBB.end()) DL = I->getDebugLoc();
129129
130130 assert((RC == ARM::tGPRRegisterClass ||
153153 if (CSI.empty())
154154 return false;
155155
156 DebugLoc DL = DebugLoc::getUnknownLoc();
156 DebugLoc DL;
157157 if (MI != MBB.end()) DL = MI->getDebugLoc();
158158
159159 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
397397 // off the frame pointer (if, for example, there are alloca() calls in
398398 // the function, the offset will be negative. Use R12 instead since that's
399399 // a call clobbered register that we know won't be used in Thumb1 mode.
400 DebugLoc DL = DebugLoc::getUnknownLoc();
400 DebugLoc DL;
401401 BuildMI(MBB, I, DL, TII.get(ARM::tMOVtgpr2gpr)).
402402 addReg(ARM::R12, RegState::Define).addReg(Reg, RegState::Kill);
403403
684684 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
685685 unsigned NumBytes = MFI->getStackSize();
686686 const std::vector &CSI = MFI->getCalleeSavedInfo();
687 DebugLoc dl = (MBBI != MBB.end() ?
688 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
687 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
689688
690689 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
691690 NumBytes = (NumBytes + 3) & ~3;
4040 unsigned DestReg, unsigned SrcReg,
4141 const TargetRegisterClass *DestRC,
4242 const TargetRegisterClass *SrcRC) const {
43 DebugLoc DL = DebugLoc::getUnknownLoc();
43 DebugLoc DL;
4444 if (I != MBB.end()) DL = I->getDebugLoc();
4545
4646 if (DestRC == ARM::GPRRegisterClass &&
6565 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
6666 unsigned SrcReg, bool isKill, int FI,
6767 const TargetRegisterClass *RC) const {
68 DebugLoc DL = DebugLoc::getUnknownLoc();
68 DebugLoc DL;
6969 if (I != MBB.end()) DL = I->getDebugLoc();
7070
7171 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass) {
8989 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
9090 unsigned DestReg, int FI,
9191 const TargetRegisterClass *RC) const {
92 DebugLoc DL = DebugLoc::getUnknownLoc();
92 DebugLoc DL;
9393 if (I != MBB.end()) DL = I->getDebugLoc();
9494
9595 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass) {
470470
471471 SDValue Copy = DAG.getCopyToReg(Chain, dl, Alpha::R26,
472472 DAG.getNode(AlphaISD::GlobalRetAddr,
473 DebugLoc::getUnknownLoc(),
474 MVT::i64),
473 DebugLoc(), MVT::i64),
475474 SDValue());
476475 switch (Outs.size()) {
477476 default:
739738 SA2, NULL, 0, MVT::i32, false, false, 0);
740739 }
741740 case ISD::RETURNADDR:
742 return DAG.getNode(AlphaISD::GlobalRetAddr, DebugLoc::getUnknownLoc(),
743 MVT::i64);
741 return DAG.getNode(AlphaISD::GlobalRetAddr, DebugLoc(), MVT::i64);
744742 //FIXME: implement
745743 case ISD::FRAMEADDR: break;
746744 }
111111 MachineBasicBlock *FBB,
112112 const SmallVectorImpl &Cond) const {
113113 // FIXME this should probably have a DebugLoc argument
114 DebugLoc dl = DebugLoc::getUnknownLoc();
114 DebugLoc dl;
115115 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
116116 assert((Cond.size() == 2 || Cond.size() == 0) &&
117117 "Alpha branch conditions have two components!");
152152 return false;
153153 }
154154
155 DebugLoc DL = DebugLoc::getUnknownLoc();
155 DebugLoc DL;
156156 if (MI != MBB.end()) DL = MI->getDebugLoc();
157157
158158 if (DestRC == Alpha::GPRCRegisterClass) {
184184 // << FrameIdx << "\n";
185185 //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
186186
187 DebugLoc DL = DebugLoc::getUnknownLoc();
187 DebugLoc DL;
188188 if (MI != MBB.end()) DL = MI->getDebugLoc();
189189
190190 if (RC == Alpha::F4RCRegisterClass)
210210 const TargetRegisterClass *RC) const {
211211 //cerr << "Trying to load " << getPrettyName(DestReg) << " to "
212212 // << FrameIdx << "\n";
213 DebugLoc DL = DebugLoc::getUnknownLoc();
213 DebugLoc DL;
214214 if (MI != MBB.end()) DL = MI->getDebugLoc();
215215
216216 if (RC == Alpha::F4RCRegisterClass)
397397
398398 void AlphaInstrInfo::insertNoop(MachineBasicBlock &MBB,
399399 MachineBasicBlock::iterator MI) const {
400 DebugLoc DL = DebugLoc::getUnknownLoc();
400 DebugLoc DL;
401401 if (MI != MBB.end()) DL = MI->getDebugLoc();
402402 BuildMI(MBB, MI, DL, get(Alpha::BISr), Alpha::R31)
403403 .addReg(Alpha::R31)
4848 const TargetInstrInfo *TII = F.getTarget().getInstrInfo();
4949 bool Changed = false;
5050 MachineInstr* prev[3] = {0,0,0};
51 DebugLoc dl = DebugLoc::getUnknownLoc();
51 DebugLoc dl;
5252 unsigned count = 0;
5353 for (MachineFunction::iterator FI = F.begin(), FE = F.end();
5454 FI != FE; ++FI) {
206206 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
207207 MachineBasicBlock::iterator MBBI = MBB.begin();
208208 MachineFrameInfo *MFI = MF.getFrameInfo();
209 DebugLoc dl = (MBBI != MBB.end() ?
210 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
209 DebugLoc dl = (MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc());
211210 bool FP = hasFP(MF);
212211
213212 //handle GOP offset
105105 MachineBasicBlock *FBB,
106106 const SmallVectorImpl &Cond) const {
107107 // FIXME this should probably have a DebugLoc operand
108 DebugLoc dl = DebugLoc::getUnknownLoc();
108 DebugLoc DL;
109109
110110 // Shouldn't be a fall through.
111111 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
115115 if (Cond.empty()) {
116116 // Unconditional branch?
117117 assert(!FBB && "Unconditional branch with multiple successors!");
118 BuildMI(&MBB, dl, get(BF::JUMPa)).addMBB(TBB);
118 BuildMI(&MBB, DL, get(BF::JUMPa)).addMBB(TBB);
119119 return 1;
120120 }
121121
138138 unsigned SrcReg,
139139 const TargetRegisterClass *DestRC,
140140 const TargetRegisterClass *SrcRC) const {
141 DebugLoc dl = DebugLoc::getUnknownLoc();
141 DebugLoc DL;
142142
143143 if (inClass(BF::ALLRegClass, DestReg, DestRC) &&
144144 inClass(BF::ALLRegClass, SrcReg, SrcRC)) {
145 BuildMI(MBB, I, dl, get(BF::MOVE), DestReg).addReg(SrcReg);
145 BuildMI(MBB, I, DL, get(BF::MOVE), DestReg).addReg(SrcReg);
146146 return true;
147147 }
148148
149149 if (inClass(BF::D16RegClass, DestReg, DestRC) &&
150150 inClass(BF::D16RegClass, SrcReg, SrcRC)) {
151 BuildMI(MBB, I, dl, get(BF::SLL16i), DestReg).addReg(SrcReg).addImm(0);
151 BuildMI(MBB, I, DL, get(BF::SLL16i), DestReg).addReg(SrcReg).addImm(0);
152152 return true;
153153 }
154154
155155 if (inClass(BF::AnyCCRegClass, SrcReg, SrcRC) &&
156156 inClass(BF::DRegClass, DestReg, DestRC)) {
157157 if (inClass(BF::NotCCRegClass, SrcReg, SrcRC)) {
158 BuildMI(MBB, I, dl, get(BF::MOVENCC_z), DestReg).addReg(SrcReg);
159 BuildMI(MBB, I, dl, get(BF::BITTGL), DestReg).addReg(DestReg).addImm(0);
158 BuildMI(MBB, I, DL, get(BF::MOVENCC_z), DestReg).addReg(SrcReg);
159 BuildMI(MBB, I, DL, get(BF::BITTGL), DestReg).addReg(DestReg).addImm(0);
160160 } else {
161 BuildMI(MBB, I, dl, get(BF::MOVECC_zext), DestReg).addReg(SrcReg);
161 BuildMI(MBB, I, DL, get(BF::MOVECC_zext), DestReg).addReg(SrcReg);
162162 }
163163 return true;
164164 }
166166 if (inClass(BF::AnyCCRegClass, DestReg, DestRC) &&
167167 inClass(BF::DRegClass, SrcReg, SrcRC)) {
168168 if (inClass(BF::NotCCRegClass, DestReg, DestRC))
169 BuildMI(MBB, I, dl, get(BF::SETEQri_not), DestReg).addReg(SrcReg);
169 BuildMI(MBB, I, DL, get(BF::SETEQri_not), DestReg).addReg(SrcReg);
170170 else
171 BuildMI(MBB, I, dl, get(BF::MOVECC_nz), DestReg).addReg(SrcReg);
171 BuildMI(MBB, I, DL, get(BF::MOVECC_nz), DestReg).addReg(SrcReg);
172172 return true;
173173 }
174174
175175 if (inClass(BF::NotCCRegClass, DestReg, DestRC) &&
176176 inClass(BF::JustCCRegClass, SrcReg, SrcRC)) {
177 BuildMI(MBB, I, dl, get(BF::MOVE_ncccc), DestReg).addReg(SrcReg);
177 BuildMI(MBB, I, DL, get(BF::MOVE_ncccc), DestReg).addReg(SrcReg);
178178 return true;
179179 }
180180
181181 if (inClass(BF::JustCCRegClass, DestReg, DestRC) &&
182182 inClass(BF::NotCCRegClass, SrcReg, SrcRC)) {
183 BuildMI(MBB, I, dl, get(BF::MOVE_ccncc), DestReg).addReg(SrcReg);
183 BuildMI(MBB, I, DL, get(BF::MOVE_ccncc), DestReg).addReg(SrcReg);
184184 return true;
185185 }
186186
196196 bool isKill,
197197 int FI,
198198 const TargetRegisterClass *RC) const {
199 DebugLoc DL = I != MBB.end() ?
200 I->getDebugLoc() : DebugLoc::getUnknownLoc();
199 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
201200
202201 if (inClass(BF::DPRegClass, SrcReg, RC)) {
203202 BuildMI(MBB, I, DL, get(BF::STORE32fi))
243242 unsigned DestReg,
244243 int FI,
245244 const TargetRegisterClass *RC) const {
246 DebugLoc DL = I != MBB.end() ?
247 I->getDebugLoc() : DebugLoc::getUnknownLoc();
245 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
248246 if (inClass(BF::DPRegClass, DestReg, RC)) {
249247 BuildMI(MBB, I, DL, get(BF::LOAD32fi), DestReg)
250248 .addFrameIndex(FI)
383383 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
384384 MachineBasicBlock::iterator MBBI = MBB.begin();
385385 MachineFrameInfo *MFI = MF.getFrameInfo();
386 DebugLoc dl = (MBBI != MBB.end()
387 ? MBBI->getDebugLoc()
388 : DebugLoc::getUnknownLoc());
386 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
389387
390388 int FrameSize = MFI->getStackSize();
391389 if (FrameSize%4) {
261261 // we instruction select bitconvert i64 -> f64 as a noop for example, so our
262262 // types have no specific meaning.
263263
264 DebugLoc DL = DebugLoc::getUnknownLoc();
264 DebugLoc DL;
265265 if (MI != MBB.end()) DL = MI->getDebugLoc();
266266
267267 if (DestRC == SPU::R8CRegisterClass) {
316316 llvm_unreachable("Unknown regclass!");
317317 }
318318
319 DebugLoc DL = DebugLoc::getUnknownLoc();
319 DebugLoc DL;
320320 if (MI != MBB.end()) DL = MI->getDebugLoc();
321321 addFrameReference(BuildMI(MBB, MI, DL, get(opc))
322322 .addReg(SrcReg, getKillRegState(isKill)), FrameIdx);
350350 llvm_unreachable("Unknown regclass in loadRegFromStackSlot!");
351351 }
352352
353 DebugLoc DL = DebugLoc::getUnknownLoc();
353 DebugLoc DL;
354354 if (MI != MBB.end()) DL = MI->getDebugLoc();
355355 addFrameReference(BuildMI(MBB, MI, DL, get(opc), DestReg), FrameIdx);
356356 }
552552 MachineBasicBlock *FBB,
553553 const SmallVectorImpl &Cond) const {
554554 // FIXME this should probably have a DebugLoc argument
555 DebugLoc dl = DebugLoc::getUnknownLoc();
555 DebugLoc dl;
556556 // Shouldn't be a fall through.
557557 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
558558 assert((Cond.size() == 2 || Cond.size() == 0) &&
451451 MachineBasicBlock::iterator MBBI = MBB.begin();
452452 MachineFrameInfo *MFI = MF.getFrameInfo();
453453 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
454 DebugLoc dl = (MBBI != MBB.end() ?
455 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
454 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
456455
457456 // Prepare for debug frame info.
458457 bool hasDebugInfo = MMI && MMI->hasDebugInfo();
105105 /// instruction.
106106 void MBlazeInstrInfo::
107107 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const {
108 DebugLoc DL = DebugLoc::getUnknownLoc();
108 DebugLoc DL;
109109 if (MI != MBB.end()) DL = MI->getDebugLoc();
110110 BuildMI(MBB, MI, DL, get(MBlaze::NOP));
111111 }
115115 unsigned DestReg, unsigned SrcReg,
116116 const TargetRegisterClass *DestRC,
117117 const TargetRegisterClass *SrcRC) const {
118 DebugLoc dl = DebugLoc::getUnknownLoc();
119 llvm::BuildMI(MBB, I, dl, get(MBlaze::ADD), DestReg)
118 DebugLoc DL;
119 llvm::BuildMI(MBB, I, DL, get(MBlaze::ADD), DestReg)
120120 .addReg(SrcReg).addReg(MBlaze::R0);
121121 return true;
122122 }
125125 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
126126 unsigned SrcReg, bool isKill, int FI,
127127 const TargetRegisterClass *RC) const {
128 DebugLoc dl = DebugLoc::getUnknownLoc();
129 BuildMI(MBB, I, dl, get(MBlaze::SWI)).addReg(SrcReg,getKillRegState(isKill))
128 DebugLoc DL;
129 BuildMI(MBB, I, DL, get(MBlaze::SWI)).addReg(SrcReg,getKillRegState(isKill))
130130 .addImm(0).addFrameIndex(FI);
131131 }
132132
134134 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
135135 unsigned DestReg, int FI,
136136 const TargetRegisterClass *RC) const {
137 DebugLoc dl = DebugLoc::getUnknownLoc();
138 BuildMI(MBB, I, dl, get(MBlaze::LWI), DestReg)
137 DebugLoc DL;
138 BuildMI(MBB, I, DL, get(MBlaze::LWI), DestReg)
139139 .addImm(0).addFrameIndex(FI);
140140 }
141141
184184 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
185185 MachineBasicBlock *FBB,
186186 const SmallVectorImpl &Cond) const {
187 DebugLoc dl = DebugLoc::getUnknownLoc();
188
189187 // Can only insert uncond branches so far.
190188 assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
191 BuildMI(&MBB, dl, get(MBlaze::BRI)).addMBB(TBB);
189 BuildMI(&MBB, DebugLoc(), get(MBlaze::BRI)).addMBB(TBB);
192190 return 1;
193191 }
194192
301301 MachineFrameInfo *MFI = MF.getFrameInfo();
302302 MBlazeFunctionInfo *MBlazeFI = MF.getInfo();
303303 MachineBasicBlock::iterator MBBI = MBB.begin();
304 DebugLoc dl = (MBBI != MBB.end() ?
305 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
304 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
306305
307306 // Get the right frame order for MBlaze.
308307 adjustMBlazeStackFrame(MF);
318317 int RAOffset = MBlazeFI->getRAStackOffset();
319318
320319 // Adjust stack : addi R1, R1, -imm
321 BuildMI(MBB, MBBI, dl, TII.get(MBlaze::ADDI), MBlaze::R1)
320 BuildMI(MBB, MBBI, DL, TII.get(MBlaze::ADDI), MBlaze::R1)
322321 .addReg(MBlaze::R1).addImm(-StackSize);
323322
324323 // Save the return address only if the function isnt a leaf one.
325324 // swi R15, R1, stack_loc
326325 if (MFI->hasCalls()) {
327 BuildMI(MBB, MBBI, dl, TII.get(MBlaze::SWI))
326 BuildMI(MBB, MBBI, DL, TII.get(MBlaze::SWI))
328327 .addReg(MBlaze::R15).addImm(RAOffset).addReg(MBlaze::R1);
329328 }
330329
332331 // to point to the stack pointer
333332 if (hasFP(MF)) {
334333 // swi R19, R1, stack_loc
335 BuildMI(MBB, MBBI, dl, TII.get(MBlaze::SWI))
334 BuildMI(MBB, MBBI, DL, TII.get(MBlaze::SWI))
336335 .addReg(MBlaze::R19).addImm(FPOffset).addReg(MBlaze::R1);
337336
338337 // add R19, R1, R0
339 BuildMI(MBB, MBBI, dl, TII.get(MBlaze::ADD), MBlaze::R19)
338 BuildMI(MBB, MBBI, DL, TII.get(MBlaze::ADD), MBlaze::R19)
340339 .addReg(MBlaze::R1).addReg(MBlaze::R0);
341340 }
342341 }
3232 MachineBasicBlock::iterator MI,
3333 unsigned SrcReg, bool isKill, int FrameIdx,
3434 const TargetRegisterClass *RC) const {
35 DebugLoc DL = DebugLoc::getUnknownLoc();
35 DebugLoc DL;
3636 if (MI != MBB.end()) DL = MI->getDebugLoc();
3737 MachineFunction &MF = *MBB.getParent();
3838 MachineFrameInfo &MFI = *MF.getFrameInfo();
5959 MachineBasicBlock::iterator MI,
6060 unsigned DestReg, int FrameIdx,
6161 const TargetRegisterClass *RC) const{
62 DebugLoc DL = DebugLoc::getUnknownLoc();
62 DebugLoc DL;
6363 if (MI != MBB.end()) DL = MI->getDebugLoc();
6464 MachineFunction &MF = *MBB.getParent();
6565 MachineFrameInfo &MFI = *MF.getFrameInfo();
8585 unsigned DestReg, unsigned SrcReg,
8686 const TargetRegisterClass *DestRC,
8787 const TargetRegisterClass *SrcRC) const {
88 DebugLoc DL = DebugLoc::getUnknownLoc();
88 DebugLoc DL;
8989 if (I != MBB.end()) DL = I->getDebugLoc();
9090
9191 if (DestRC == SrcRC) {
133133 if (CSI.empty())
134134 return false;
135135
136 DebugLoc DL = DebugLoc::getUnknownLoc();
136 DebugLoc DL;
137137 if (MI != MBB.end()) DL = MI->getDebugLoc();
138138
139139 MachineFunction &MF = *MBB.getParent();
157157 if (CSI.empty())
158158 return false;
159159
160 DebugLoc DL = DebugLoc::getUnknownLoc();
160 DebugLoc DL;
161161 if (MI != MBB.end()) DL = MI->getDebugLoc();
162162
163163 for (unsigned i = 0, e = CSI.size(); i != e; ++i)
322322 MachineBasicBlock *FBB,
323323 const SmallVectorImpl &Cond) const {
324324 // FIXME this should probably have a DebugLoc operand
325 DebugLoc dl = DebugLoc::getUnknownLoc();
325 DebugLoc DL;
326326
327327 // Shouldn't be a fall through.
328328 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
332332 if (Cond.empty()) {
333333 // Unconditional branch?
334334 assert(!FBB && "Unconditional branch with multiple successors!");
335 BuildMI(&MBB, dl, get(MSP430::JMP)).addMBB(TBB);
335 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB);
336336 return 1;
337337 }
338338
339339 // Conditional branch.
340340 unsigned Count = 0;
341 BuildMI(&MBB, dl, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
341 BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
342342 ++Count;
343343
344344 if (FBB) {
345345 // Two-way Conditional branch. Insert the second branch.
346 BuildMI(&MBB, dl, get(MSP430::JMP)).addMBB(FBB);
346 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
347347 ++Count;
348348 }
349349 return Count;
282282 MachineFrameInfo *MFI = MF.getFrameInfo();
283283 MSP430MachineFunctionInfo *MSP430FI = MF.getInfo();
284284 MachineBasicBlock::iterator MBBI = MBB.begin();
285 DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() :
286 DebugLoc::getUnknownLoc());
285 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
287286
288287 // Get the number of bytes to allocate from the FrameInfo.
289288 uint64_t StackSize = MFI->getStackSize();
122122 void MipsInstrInfo::
123123 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
124124 {
125 DebugLoc DL = DebugLoc::getUnknownLoc();
125 DebugLoc DL;
126126 if (MI != MBB.end()) DL = MI->getDebugLoc();
127127 BuildMI(MBB, MI, DL, get(Mips::NOP));
128128 }
132132 unsigned DestReg, unsigned SrcReg,
133133 const TargetRegisterClass *DestRC,
134134 const TargetRegisterClass *SrcRC) const {
135 DebugLoc DL = DebugLoc::getUnknownLoc();
135 DebugLoc DL;
136136
137137 if (I != MBB.end()) DL = I->getDebugLoc();
138138
190190 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
191191 unsigned SrcReg, bool isKill, int FI,
192192 const TargetRegisterClass *RC) const {
193 DebugLoc DL = DebugLoc::getUnknownLoc();
193 DebugLoc DL;
194194 if (I != MBB.end()) DL = I->getDebugLoc();
195195
196196 if (RC == Mips::CPURegsRegisterClass)
224224 unsigned DestReg, int FI,
225225 const TargetRegisterClass *RC) const
226226 {
227 DebugLoc DL = DebugLoc::getUnknownLoc();
227 DebugLoc DL;
228228 if (I != MBB.end()) DL = I->getDebugLoc();
229229
230230 if (RC == Mips::CPURegsRegisterClass)
522522 MachineBasicBlock *FBB,
523523 const SmallVectorImpl &Cond) const {
524524 // FIXME this should probably have a DebugLoc argument
525 DebugLoc dl = DebugLoc::getUnknownLoc();
525 DebugLoc dl;
526526 // Shouldn't be a fall through.
527527 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
528528 assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) &&
396396 MachineFrameInfo *MFI = MF.getFrameInfo();
397397 MipsFunctionInfo *MipsFI = MF.getInfo();
398398 MachineBasicBlock::iterator MBBI = MBB.begin();
399 DebugLoc dl = (MBBI != MBB.end() ?
400 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
399 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
401400 bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_);
402401
403402 // Get the right frame order for Mips.
7171 unsigned SrcReg, bool isKill, int FI,
7272 const TargetRegisterClass *RC) const {
7373 PIC16TargetLowering *PTLI = TM.getTargetLowering();
74 DebugLoc DL = DebugLoc::getUnknownLoc();
74 DebugLoc DL;
7575 if (I != MBB.end()) DL = I->getDebugLoc();
7676
7777 const Function *Func = MBB.getParent()->getFunction();
113113 unsigned DestReg, int FI,
114114 const TargetRegisterClass *RC) const {
115115 PIC16TargetLowering *PTLI = TM.getTargetLowering();
116 DebugLoc DL = DebugLoc::getUnknownLoc();
116 DebugLoc DL;
117117 if (I != MBB.end()) DL = I->getDebugLoc();
118118
119119 const Function *Func = MBB.getParent()->getFunction();
153153 unsigned DestReg, unsigned SrcReg,
154154 const TargetRegisterClass *DestRC,
155155 const TargetRegisterClass *SrcRC) const {
156 DebugLoc DL = DebugLoc::getUnknownLoc();
156 DebugLoc DL;
157157 if (I != MBB.end()) DL = I->getDebugLoc();
158158
159159 if (DestRC == PIC16::FSR16RegisterClass) {
201201 if (FBB == 0) { // One way branch.
202202 if (Cond.empty()) {
203203 // Unconditional branch?
204 DebugLoc dl = DebugLoc::getUnknownLoc();
204 DebugLoc dl;
205205 BuildMI(&MBB, dl, get(PIC16::br_uncond)).addMBB(TBB);
206206 }
207207 return 1;
214214
215215 const TargetInstrInfo &TII = *TM.getInstrInfo();
216216 MachineBasicBlock &EntryBB = *Fn.begin();
217 DebugLoc dl = DebugLoc::getUnknownLoc();
217 DebugLoc dl;
218218 // Emit the following code into the entry block:
219219 // InVRSAVE = MFVRSAVE
220220 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
252252 // Insert the set of GlobalBaseReg into the first MBB of the function
253253 MachineBasicBlock &FirstMBB = MF->front();
254254 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
255 DebugLoc dl = DebugLoc::getUnknownLoc();
255 DebugLoc dl;
256256
257257 if (PPCLowering.getPointerTy() == MVT::i32) {
258258 GlobalBaseReg = RegInfo->createVirtualRegister(PPC::GPRCRegisterClass);
11211121 // With PIC, the first instruction is actually "GR+hi(&G)".
11221122 Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
11231123 DAG.getNode(PPCISD::GlobalBaseReg,
1124 DebugLoc::getUnknownLoc(), PtrVT), Hi);
1124 DebugLoc(), PtrVT), Hi);
11251125 }
11261126
11271127 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
11541154 // With PIC, the first instruction is actually "GR+hi(&G)".
11551155 Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
11561156 DAG.getNode(PPCISD::GlobalBaseReg,
1157 DebugLoc::getUnknownLoc(), PtrVT), Hi);
1157 DebugLoc(), PtrVT), Hi);
11581158 }
11591159
11601160 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
11911191 // With PIC, the first instruction is actually "GR+hi(&G)".
11921192 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
11931193 DAG.getNode(PPCISD::GlobalBaseReg,
1194 DebugLoc::getUnknownLoc(), PtrVT), Hi);
1194 DebugLoc(), PtrVT), Hi);
11951195 }
11961196
11971197 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
12321232 // With PIC, the first instruction is actually "GR+hi(&G)".
12331233 Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
12341234 DAG.getNode(PPCISD::GlobalBaseReg,
1235 DebugLoc::getUnknownLoc(), PtrVT), Hi);
1235 DebugLoc(), PtrVT), Hi);
12361236 }
12371237
12381238 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
198198
199199 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
200200 MachineBasicBlock::iterator MI) const {
201 DebugLoc DL = DebugLoc::getUnknownLoc();
201 DebugLoc DL;
202202 if (MI != MBB.end()) DL = MI->getDebugLoc();
203203
204204 BuildMI(MBB, MI, DL, get(PPC::NOP));
316316 MachineBasicBlock *FBB,
317317 const SmallVectorImpl &Cond) const {
318318 // FIXME this should probably have a DebugLoc argument
319 DebugLoc dl = DebugLoc::getUnknownLoc();
319 DebugLoc dl;
320320 // Shouldn't be a fall through.
321321 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
322322 assert((Cond.size() == 2 || Cond.size() == 0) &&
349349 return false;
350350 }
351351
352 DebugLoc DL = DebugLoc::getUnknownLoc();
352 DebugLoc DL;
353353 if (MI != MBB.end()) DL = MI->getDebugLoc();
354354
355355 if (DestRC == PPC::GPRCRegisterClass) {
379379 int FrameIdx,
380380 const TargetRegisterClass *RC,
381381 SmallVectorImpl &NewMIs) const{
382 DebugLoc DL = DebugLoc::getUnknownLoc();
382 DebugLoc DL;
383383 if (RC == PPC::GPRCRegisterClass) {
384384 if (SrcReg != PPC::LR) {
385385 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
634634 const TargetRegisterClass *RC) const {
635635 MachineFunction &MF = *MBB.getParent();
636636 SmallVector NewMIs;
637 DebugLoc DL = DebugLoc::getUnknownLoc();
637 DebugLoc DL;
638638 if (MI != MBB.end()) DL = MI->getDebugLoc();
639639 LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
640640 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
12801280 MachineBasicBlock::iterator MBBI = MBB.begin();
12811281 MachineFrameInfo *MFI = MF.getFrameInfo();
12821282 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
1283 DebugLoc dl = DebugLoc::getUnknownLoc();
1283 DebugLoc dl;
12841284 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
12851285 !MF.getFunction()->doesNotThrow() ||
12861286 UnwindTablesMandatory;
15201520 MachineBasicBlock &MBB) const {
15211521 MachineBasicBlock::iterator MBBI = prior(MBB.end());
15221522 unsigned RetOpcode = MBBI->getOpcode();
1523 DebugLoc dl = DebugLoc::getUnknownLoc();
1523 DebugLoc dl;
15241524
15251525 assert( (RetOpcode == PPC::BLR ||
15261526 RetOpcode == PPC::TCRETURNri ||
6767 if (I->getDesc().hasDelaySlot()) {
6868 MachineBasicBlock::iterator J = I;
6969 ++J;
70 BuildMI(MBB, J, DebugLoc::getUnknownLoc(), TII->get(SP::NOP));
70 BuildMI(MBB, J, DebugLoc(), TII->get(SP::NOP));
7171 ++FilledSlots;
7272 Changed = true;
7373 }
110110 MachineBasicBlock *FBB,
111111 const SmallVectorImpl &Cond)const{
112112 // FIXME this should probably take a DebugLoc argument
113 DebugLoc dl = DebugLoc::getUnknownLoc();
113 DebugLoc dl;
114114 // Can only insert uncond branches so far.
115115 assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
116116 BuildMI(&MBB, dl, get(SP::BA)).addMBB(TBB);
127127 return false;
128128 }
129129
130 DebugLoc DL = DebugLoc::getUnknownLoc();
130 DebugLoc DL;
131131 if (I != MBB.end()) DL = I->getDebugLoc();
132132
133133 if (DestRC == SP::IntRegsRegisterClass)
148148 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
149149 unsigned SrcReg, bool isKill, int FI,
150150 const TargetRegisterClass *RC) const {
151 DebugLoc DL = DebugLoc::getUnknownLoc();
151 DebugLoc DL;
152152 if (I != MBB.end()) DL = I->getDebugLoc();
153153
154154 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
169169 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
170170 unsigned DestReg, int FI,
171171 const TargetRegisterClass *RC) const {
172 DebugLoc DL = DebugLoc::getUnknownLoc();
172 DebugLoc DL;
173173 if (I != MBB.end()) DL = I->getDebugLoc();
174174
175175 if (RC == SP::IntRegsRegisterClass)
252252 GlobalBaseReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
253253
254254
255 DebugLoc dl = DebugLoc::getUnknownLoc();
255 DebugLoc dl;
256256
257257 BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg);
258258 SparcFI->setGlobalBaseReg(GlobalBaseReg);
124124 MachineBasicBlock &MBB = MF.front();
125125 MachineFrameInfo *MFI = MF.getFrameInfo();
126126 MachineBasicBlock::iterator MBBI = MBB.begin();
127 DebugLoc dl = (MBBI != MBB.end() ?
128 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
127 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
129128
130129 // Get the number of bytes to allocate from the FrameInfo
131130 int NumBytes = (int) MFI->getStackSize();
6161 MachineBasicBlock::iterator MI,
6262 unsigned SrcReg, bool isKill, int FrameIdx,
6363 const TargetRegisterClass *RC) const {
64 DebugLoc DL = DebugLoc::getUnknownLoc();
64 DebugLoc DL;
6565 if (MI != MBB.end()) DL = MI->getDebugLoc();
6666
6767 unsigned Opc = 0;
9090 MachineBasicBlock::iterator MI,
9191 unsigned DestReg, int FrameIdx,
9292 const TargetRegisterClass *RC) const{
93 DebugLoc DL = DebugLoc::getUnknownLoc();
93 DebugLoc DL;
9494 if (MI != MBB.end()) DL = MI->getDebugLoc();
9595
9696 unsigned Opc = 0;
119119 unsigned DestReg, unsigned SrcReg,
120120 const TargetRegisterClass *DestRC,
121121 const TargetRegisterClass *SrcRC) const {
122 DebugLoc DL = DebugLoc::getUnknownLoc();
122 DebugLoc DL;
123123 if (I != MBB.end()) DL = I->getDebugLoc();
124124
125125 // Determine if DstRC and SrcRC have a common superclass.
272272 if (CSI.empty())
273273 return false;
274274
275 DebugLoc DL = DebugLoc::getUnknownLoc();
275 DebugLoc DL;
276276 if (MI != MBB.end()) DL = MI->getDebugLoc();
277277
278278 MachineFunction &MF = *MBB.getParent();
346346 if (CSI.empty())
347347 return false;
348348
349 DebugLoc DL = DebugLoc::getUnknownLoc();
349 DebugLoc DL;
350350 if (MI != MBB.end()) DL = MI->getDebugLoc();
351351
352352 MachineFunction &MF = *MBB.getParent();
520520 MachineBasicBlock *FBB,
521521 const SmallVectorImpl &Cond) const {
522522 // FIXME: this should probably have a DebugLoc operand
523 DebugLoc dl = DebugLoc::getUnknownLoc();
523 DebugLoc DL;
524524 // Shouldn't be a fall through.
525525 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
526526 assert((Cond.size() == 1 || Cond.size() == 0) &&
529529 if (Cond.empty()) {
530530 // Unconditional branch?
531531 assert(!FBB && "Unconditional branch with multiple successors!");
532 BuildMI(&MBB, dl, get(SystemZ::JMP)).addMBB(TBB);
532 BuildMI(&MBB, DL, get(SystemZ::JMP)).addMBB(TBB);
533533 return 1;
534534 }
535535
536536 // Conditional branch.
537537 unsigned Count = 0;
538538 SystemZCC::CondCodes CC = (SystemZCC::CondCodes)Cond[0].getImm();
539 BuildMI(&MBB, dl, getBrCond(CC)).addMBB(TBB);
539 BuildMI(&MBB, DL, getBrCond(CC)).addMBB(TBB);
540540 ++Count;
541541
542542 if (FBB) {
543543 // Two-way Conditional branch. Insert the second branch.
544 BuildMI(&MBB, dl, get(SystemZ::JMP)).addMBB(FBB);
544 BuildMI(&MBB, DL, get(SystemZ::JMP)).addMBB(FBB);
545545 ++Count;
546546 }
547547 return Count;
193193 Chunk = (1LL << 15) - 1;
194194 }
195195
196 DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() :
197 DebugLoc::getUnknownLoc());
196 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
198197
199198 while (Offset) {
200199 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
214213 SystemZMachineFunctionInfo *SystemZMFI =
215214 MF.getInfo();
216215 MachineBasicBlock::iterator MBBI = MBB.begin();
217 DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() :
218 DebugLoc::getUnknownLoc());
216 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
219217
220218 // Get the number of bytes to allocate from the FrameInfo.
221219 // Note that area for callee-saved stuff is already allocated, thus we need to
128128 }
129129 // Finally, if we found any FP code, emit the FP_REG_KILL instruction.
130130 if (ContainsFPCode) {
131 BuildMI(*MBB, MBBI->getFirstTerminator(), DebugLoc::getUnknownLoc(),
131 BuildMI(*MBB, MBBI->getFirstTerminator(), DebugLoc(),
132132 MF.getTarget().getInstrInfo()->get(X86::FP_REG_KILL));
133133 ++NumFPKill;
134134 Changed = true;
541541 MachineFrameInfo *MFI) {
542542 const TargetInstrInfo *TII = TM.getInstrInfo();
543543 if (Subtarget->isTargetCygMing())
544 BuildMI(BB, DebugLoc::getUnknownLoc(),
544 BuildMI(BB, DebugLoc(),
545545 TII->get(X86::CALLpcrel32)).addExternalSymbol("__main");
546546 }
547547
11481148 if (!Subtarget->is64Bit())
11491149 // This doesn't have DebugLoc associated with it, but is not really the
11501150 // same as a Register.
1151 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(),
1152 getPointerTy());
1151 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
11531152 return Table;
11541153 }
11551154
19301929 if (!isTailCall) {
19311930 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
19321931 DAG.getNode(X86ISD::GlobalBaseReg,
1933 DebugLoc::getUnknownLoc(),
1934 getPointerTy()),
1932 DebugLoc(), getPointerTy()),
19351933 InFlag);
19361934 InFlag = Chain.getValue(1);
19371935 } else {
50605058 if (OpFlag) {
50615059 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
50625060 DAG.getNode(X86ISD::GlobalBaseReg,
5063 DebugLoc::getUnknownLoc(), getPointerTy()),
5061 DebugLoc(), getPointerTy()),
50645062 Result);
50655063 }
50665064
50935091 if (OpFlag) {
50945092 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
50955093 DAG.getNode(X86ISD::GlobalBaseReg,
5096 DebugLoc::getUnknownLoc(), getPointerTy()),
5094 DebugLoc(), getPointerTy()),
50975095 Result);
50985096 }
50995097
51295127 !Subtarget->is64Bit()) {
51305128 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
51315129 DAG.getNode(X86ISD::GlobalBaseReg,
5132 DebugLoc::getUnknownLoc(),
5133 getPointerTy()),
5130 DebugLoc(), getPointerTy()),
51345131 Result);
51355132 }
51365133
52525249 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
52535250 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
52545251 DAG.getNode(X86ISD::GlobalBaseReg,
5255 DebugLoc::getUnknownLoc(),
5256 PtrVT), InFlag);
5252 DebugLoc(), PtrVT), InFlag);
52575253 InFlag = Chain.getValue(1);
52585254
52595255 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
52755271 DebugLoc dl = GA->getDebugLoc();
52765272 // Get the Thread Pointer
52775273 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
5278 DebugLoc::getUnknownLoc(), PtrVT,
5274 DebugLoc(), PtrVT,
52795275 DAG.getRegister(is64Bit? X86::FS : X86::GS,
52805276 MVT::i32));
52815277
18021802 MachineBasicBlock *FBB,
18031803 const SmallVectorImpl &Cond) const {
18041804 // FIXME this should probably have a DebugLoc operand
1805 DebugLoc dl = DebugLoc::getUnknownLoc();
1805 DebugLoc dl;
18061806 // Shouldn't be a fall through.
18071807 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
18081808 assert((Cond.size() == 1 || Cond.size() == 0) &&
21062106 SmallVectorImpl &NewMIs) const {
21072107 bool isAligned = (*MMOBegin)->getAlignment() >= 16;
21082108 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2109 DebugLoc DL = DebugLoc::getUnknownLoc();
2109 DebugLoc DL;
21102110 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
21112111 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
21122112 MIB.addOperand(Addr[i]);
22012201 SmallVectorImpl &NewMIs) const {
22022202 bool isAligned = (*MMOBegin)->getAlignment() >= 16;
22032203 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2204 DebugLoc DL = DebugLoc::getUnknownLoc();
2204 DebugLoc DL;
22052205 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
22062206 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
22072207 MIB.addOperand(Addr[i]);
300300 MachineBasicBlock *FBB,
301301 const SmallVectorImpl &Cond)const{
302302 // FIXME there should probably be a DebugLoc argument here
303 DebugLoc dl = DebugLoc::getUnknownLoc();
303 DebugLoc dl;
304304 // Shouldn't be a fall through.
305305 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
306306 assert((Cond.size() == 2 || Cond.size() == 0) &&
361361 unsigned DestReg, unsigned SrcReg,
362362 const TargetRegisterClass *DestRC,
363363 const TargetRegisterClass *SrcRC) const {
364 DebugLoc DL = DebugLoc::getUnknownLoc();
364 DebugLoc DL;
365365 if (I != MBB.end()) DL = I->getDebugLoc();
366366
367367 if (DestRC == SrcRC) {
396396 int FrameIndex,
397397 const TargetRegisterClass *RC) const
398398 {
399 DebugLoc DL = DebugLoc::getUnknownLoc();
399 DebugLoc DL;
400400 if (I != MBB.end()) DL = I->getDebugLoc();
401401 BuildMI(MBB, I, DL, get(XCore::STWFI))
402402 .addReg(SrcReg, getKillRegState(isKill))
409409 unsigned DestReg, int FrameIndex,
410410 const TargetRegisterClass *RC) const
411411 {
412 DebugLoc DL = DebugLoc::getUnknownLoc();
412 DebugLoc DL;
413413 if (I != MBB.end()) DL = I->getDebugLoc();
414414 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg)
415415 .addFrameIndex(FrameIndex)
430430
431431 bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(*MF);
432432
433 DebugLoc DL = DebugLoc::getUnknownLoc();
433 DebugLoc DL;
434434 if (MI != MBB.end()) DL = MI->getDebugLoc();
435435
436436 for (std::vector::const_iterator it = CSI.begin();
413413 MachineFrameInfo *MFI = MF.getFrameInfo();
414414 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
415415 XCoreFunctionInfo *XFI = MF.getInfo();
416 DebugLoc dl = (MBBI != MBB.end() ?
417 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
416 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
418417
419418 bool FP = hasFP(MF);
420419