llvm.org GIT mirror llvm / c7acbe2
Add DAG argument to canMergeStoresTo NFC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307583 91177308-0d34-0410-b5e6-96231b3b80d8 Nirav Dave 3 years ago
7 changed file(s) with 21 addition(s) and 13 deletion(s). Raw diff Collapse all Expand all
414414 virtual bool mergeStoresAfterLegalization() const { return false; }
415415
416416 /// Returns if it's reasonable to merge stores to MemVT size.
417 virtual bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT) const {
417 virtual bool canMergeStoresTo(unsigned AS, EVT MemVT,
418 const SelectionDAG &DAG) const {
418419 return true;
419420 }
420421
1271112711 EVT StoreTy = EVT::getIntegerVT(Context, SizeInBits);
1271212712 bool IsFast = false;
1271312713 if (TLI.isTypeLegal(StoreTy) &&
12714 TLI.canMergeStoresTo(FirstStoreAS, StoreTy) &&
12714 TLI.canMergeStoresTo(FirstStoreAS, StoreTy, DAG) &&
1271512715 TLI.allowsMemoryAccess(Context, DL, StoreTy, FirstStoreAS,
1271612716 FirstStoreAlign, &IsFast) &&
1271712717 IsFast) {
1272312723 EVT LegalizedStoredValueTy =
1272412724 TLI.getTypeToTransformTo(Context, StoredVal.getValueType());
1272512725 if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy) &&
12726 TLI.canMergeStoresTo(FirstStoreAS, LegalizedStoredValueTy) &&
12726 TLI.canMergeStoresTo(FirstStoreAS, LegalizedStoredValueTy, DAG) &&
1272712727 TLI.allowsMemoryAccess(Context, DL, LegalizedStoredValueTy,
1272812728 FirstStoreAS, FirstStoreAlign, &IsFast) &&
1272912729 IsFast) {
1274012740 !NoVectors) {
1274112741 // Find a legal type for the vector store.
1274212742 EVT Ty = EVT::getVectorVT(Context, MemVT, i + 1);
12743 if (TLI.isTypeLegal(Ty) && TLI.canMergeStoresTo(FirstStoreAS, Ty) &&
12743 if (TLI.isTypeLegal(Ty) &&
12744 TLI.canMergeStoresTo(FirstStoreAS, Ty, DAG) &&
1274412745 TLI.allowsMemoryAccess(Context, DL, Ty, FirstStoreAS,
1274512746 FirstStoreAlign, &IsFast) &&
1274612747 IsFast)
1279812799 EVT Ty =
1279912800 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), Elts);
1280012801 bool IsFast;
12801 if (TLI.isTypeLegal(Ty) && TLI.canMergeStoresTo(FirstStoreAS, Ty) &&
12802 if (TLI.isTypeLegal(Ty) &&
12803 TLI.canMergeStoresTo(FirstStoreAS, Ty, DAG) &&
1280212804 TLI.allowsMemoryAccess(Context, DL, Ty, FirstStoreAS,
1280312805 FirstStoreAlign, &IsFast) &&
1280412806 IsFast)
1291512917 EVT StoreTy = EVT::getVectorVT(Context, MemVT, i + 1);
1291612918 bool IsFastSt, IsFastLd;
1291712919 if (TLI.isTypeLegal(StoreTy) &&
12918 TLI.canMergeStoresTo(FirstStoreAS, StoreTy) &&
12920 TLI.canMergeStoresTo(FirstStoreAS, StoreTy, DAG) &&
1291912921 TLI.allowsMemoryAccess(Context, DL, StoreTy, FirstStoreAS,
1292012922 FirstStoreAlign, &IsFastSt) &&
1292112923 IsFastSt &&
1292912931 unsigned SizeInBits = (i + 1) * ElementSizeBytes * 8;
1293012932 StoreTy = EVT::getIntegerVT(Context, SizeInBits);
1293112933 if (TLI.isTypeLegal(StoreTy) &&
12932 TLI.canMergeStoresTo(FirstStoreAS, StoreTy) &&
12934 TLI.canMergeStoresTo(FirstStoreAS, StoreTy, DAG) &&
1293312935 TLI.allowsMemoryAccess(Context, DL, StoreTy, FirstStoreAS,
1293412936 FirstStoreAlign, &IsFastSt) &&
1293512937 IsFastSt &&
1294312945 TargetLowering::TypePromoteInteger) {
1294412946 EVT LegalizedStoredValueTy = TLI.getTypeToTransformTo(Context, StoreTy);
1294512947 if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy) &&
12946 TLI.canMergeStoresTo(FirstStoreAS, LegalizedStoredValueTy) &&
12948 TLI.canMergeStoresTo(FirstStoreAS, LegalizedStoredValueTy, DAG) &&
1294712949 TLI.isLoadExtLegal(ISD::ZEXTLOAD, LegalizedStoredValueTy,
1294812950 StoreTy) &&
1294912951 TLI.isLoadExtLegal(ISD::SEXTLOAD, LegalizedStoredValueTy,
16171617 return VT.changeVectorElementTypeToInteger();
16181618 }
16191619
1620 bool R600TargetLowering::canMergeStoresTo(unsigned AS, EVT MemVT) const {
1620 bool R600TargetLowering::canMergeStoresTo(unsigned AS, EVT MemVT,
1621 const SelectionDAG &DAG) const {
16211622 // Local and Private addresses do not handle vectors. Limit to i32
16221623 if ((AS == AMDGPUASI.LOCAL_ADDRESS || AS == AMDGPUASI.PRIVATE_ADDRESS)) {
16231624 return (MemVT.getSizeInBits() <= 32);
4343 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &,
4444 EVT VT) const override;
4545
46 bool canMergeStoresTo(unsigned AS, EVT MemVT) const override;
46 bool canMergeStoresTo(unsigned AS, EVT MemVT,
47 const SelectionDAG &DAG) const override;
4748
4849 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
4950 unsigned Align,
712712 }
713713 }
714714
715 bool SITargetLowering::canMergeStoresTo(unsigned AS, EVT MemVT) const {
715 bool SITargetLowering::canMergeStoresTo(unsigned AS, EVT MemVT,
716 const SelectionDAG &DAG) const {
716717 if (AS == AMDGPUASI.GLOBAL_ADDRESS || AS == AMDGPUASI.FLAT_ADDRESS) {
717718 return (MemVT.getSizeInBits() <= 4 * 32);
718719 } else if (AS == AMDGPUASI.PRIVATE_ADDRESS) {
152152 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
153153 unsigned AS) const override;
154154
155 bool canMergeStoresTo(unsigned AS, EVT MemVT) const override;
155 bool canMergeStoresTo(unsigned AS, EVT MemVT,
156 const SelectionDAG &DAG) const override;
156157
157158 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
158159 unsigned Align,
509509 bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
510510 unsigned &Cost) const override;
511511
512 bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT) const override {
512 bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
513 const SelectionDAG &DAG) const override {
513514 // Do not merge to larger than i32.
514515 return (MemVT.getSizeInBits() <= 32);
515516 }