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AMDGPU: Fix allocating pseudo-registers There's no need for these to be part of a class since they are immediately replaced. New unreachable hit in existing tests.' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308903 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 2 years ago
2 changed file(s) with 6 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
296296 case AMDGPU::FLAT_SCR_HI:
297297 O << "flat_scratch_hi";
298298 return;
299 case AMDGPU::FP_REG:
300 case AMDGPU::SP_REG:
301 case AMDGPU::SCRATCH_WAVE_OFFSET_REG:
302 case AMDGPU::PRIVATE_RSRC_REG:
303 llvm_unreachable("pseudo-register should not ever be emitted");
299304 default:
300305 break;
301306 }
273273 def SReg_32_XM0_XEXEC : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
274274 (add SGPR_32, VCC_LO, VCC_HI, FLAT_SCR_LO, FLAT_SCR_HI,
275275 TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI, SRC_SHARED_BASE, SRC_SHARED_LIMIT,
276 SRC_PRIVATE_BASE, SRC_PRIVATE_LIMIT,
277 FP_REG, SP_REG, SCRATCH_WAVE_OFFSET_REG)> {
276 SRC_PRIVATE_BASE, SRC_PRIVATE_LIMIT)> {
278277 let AllocationPriority = 7;
279278 }
280279