llvm.org GIT mirror llvm / c75a44c
AVX512: combining setcc and zext is wrong on AVX512 because vector compare instruction puts result in mask register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199798 91177308-0d34-0410-b5e6-96231b3b80d8 Elena Demikhovsky 6 years ago
2 changed file(s) with 15 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
50815081 if (N0.getOpcode() == ISD::SETCC) {
50825082 if (!LegalOperations && VT.isVector() &&
50835083 N0.getValueType().getVectorElementType() == MVT::i1) {
5084 EVT N0VT = N0.getOperand(0).getValueType();
5085 if (getSetCCResultType(N0VT) == N0.getValueType())
5086 return SDValue();
5087
50845088 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
50855089 // Only do this before legalize for now.
5086 EVT N0VT = N0.getOperand(0).getValueType();
50875090 EVT EltVT = VT.getVectorElementType();
50885091 SmallVector OneOps(VT.getVectorNumElements(),
50895092 DAG.getConstant(1, EltVT));
121121 %res1 = bitcast <16 x i1> %res to i16
122122 ret i16 %res1
123123 }
124
125 ; CHECK-LABEL: test13
126 ; CHECK: vcmpeqps %zmm
127 ; CHECK: vpbroadcastd
128 ; CHECK: ret
129 define <16 x i32> @test13(<16 x float>%a, <16 x float>%b)
130 {
131 %cmpvector_i = fcmp oeq <16 x float> %a, %b
132 %conv = zext <16 x i1> %cmpvector_i to <16 x i32>
133 ret <16 x i32> %conv
134 }