llvm.org GIT mirror llvm / c72fe20
Move X86RegisterInfo away from using the TargetMachine and only using the subtarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210595 91177308-0d34-0410-b5e6-96231b3b80d8 Eric Christopher 6 years ago
5 changed file(s) with 30 addition(s) and 33 deletion(s). Raw diff Collapse all Expand all
196196 }
197197 }
198198
199 unsigned X86_MC::getDwarfRegFlavour(StringRef TT, bool isEH) {
200 Triple TheTriple(TT);
201 if (TheTriple.getArch() == Triple::x86_64)
199 unsigned X86_MC::getDwarfRegFlavour(Triple TT, bool isEH) {
200 if (TT.getArch() == Triple::x86_64)
202201 return DWARFFlavour::X86_64;
203202
204 if (TheTriple.isOSDarwin())
203 if (TT.isOSDarwin())
205204 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
206 if (TheTriple.isOSCygMing())
205 if (TT.isOSCygMing())
207206 // Unsupported by now, just quick fallback
208207 return DWARFFlavour::X86_32_Generic;
209208 return DWARFFlavour::X86_32_Generic;
250249
251250 MCRegisterInfo *X = new MCRegisterInfo();
252251 InitX86MCRegisterInfo(X, RA,
253 X86_MC::getDwarfRegFlavour(TT, false),
254 X86_MC::getDwarfRegFlavour(TT, true),
252 X86_MC::getDwarfRegFlavour(TheTriple, false),
253 X86_MC::getDwarfRegFlavour(TheTriple, true),
255254 RA);
256255 X86_MC::InitLLVM2SEHRegisterMapping(X);
257256 return X;
2727 class MCRelocationInfo;
2828 class MCStreamer;
2929 class Target;
30 class Triple;
3031 class StringRef;
3132 class raw_ostream;
3233
6364
6465 void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model);
6566
66 unsigned getDwarfRegFlavour(StringRef TT, bool isEH);
67 unsigned getDwarfRegFlavour(Triple TT, bool isEH);
6768
6869 void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI);
6970
104104 (tm.getSubtarget().is64Bit()
105105 ? X86::ADJCALLSTACKUP64
106106 : X86::ADJCALLSTACKUP32)),
107 TM(tm), RI(tm) {
107 TM(tm), RI(tm.getSubtarget()) {
108108
109109 static const X86OpTblEntry OpTbl2Addr[] = {
110110 { X86::ADC32ri, X86::ADC32mi, 0 },
5252 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
5353 cl::desc("Enable use of a base pointer for complex stack frames"));
5454
55 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm)
56 : X86GenRegisterInfo((tm.getSubtarget().is64Bit()
57 ? X86::RIP : X86::EIP),
58 X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), false),
59 X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), true),
60 (tm.getSubtarget().is64Bit()
61 ? X86::RIP : X86::EIP)),
62 TM(tm) {
55 X86RegisterInfo::X86RegisterInfo(const X86Subtarget &STI)
56 : X86GenRegisterInfo(
57 (STI.is64Bit() ? X86::RIP : X86::EIP),
58 X86_MC::getDwarfRegFlavour(STI.getTargetTriple(), false),
59 X86_MC::getDwarfRegFlavour(STI.getTargetTriple(), true),
60 (STI.is64Bit() ? X86::RIP : X86::EIP)),
61 Subtarget(STI) {
6362 X86_MC::InitLLVM2SEHRegisterMapping(this);
6463
6564 // Cache some information.
66 const X86Subtarget *Subtarget = &TM.getSubtarget();
67 Is64Bit = Subtarget->is64Bit();
68 IsWin64 = Subtarget->isTargetWin64();
65 Is64Bit = Subtarget.is64Bit();
66 IsWin64 = Subtarget.isTargetWin64();
6967
7068 if (Is64Bit) {
7169 SlotSize = 8;
172170 }
173171
174172 const TargetRegisterClass *
175 X86RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
176 const {
177 const X86Subtarget &Subtarget = TM.getSubtarget();
173 X86RegisterInfo::getPointerRegClass(const MachineFunction &MF,
174 unsigned Kind) const {
178175 switch (Kind) {
179176 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
180177 case 0: // Normal GPRs.
224221 case X86::GR64RegClassID:
225222 return 12 - FPDiff;
226223 case X86::VR128RegClassID:
227 return TM.getSubtarget().is64Bit() ? 10 : 4;
224 return Subtarget.is64Bit() ? 10 : 4;
228225 case X86::VR64RegClassID:
229226 return 4;
230227 }
232229
233230 const MCPhysReg *
234231 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
235 bool HasAVX = TM.getSubtarget().hasAVX();
236 bool HasAVX512 = TM.getSubtarget().hasAVX512();
232 bool HasAVX = Subtarget.hasAVX();
233 bool HasAVX512 = Subtarget.hasAVX512();
237234
238235 assert(MF && "MachineFunction required");
239236 switch (MF->getFunction()->getCallingConv()) {
286283
287284 const uint32_t*
288285 X86RegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
289 bool HasAVX = TM.getSubtarget().hasAVX();
290 bool HasAVX512 = TM.getSubtarget().hasAVX512();
286 bool HasAVX = Subtarget.hasAVX();
287 bool HasAVX512 = Subtarget.hasAVX512();
291288
292289 switch (CC) {
293290 case CallingConv::GHC:
405402 Reserved.set(*AI);
406403 }
407404 }
408 if (!Is64Bit || !TM.getSubtarget().hasAVX512()) {
405 if (!Is64Bit || !Subtarget.hasAVX512()) {
409406 for (unsigned n = 16; n != 32; ++n) {
410407 for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
411408 Reserved.set(*AI);
458455 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
459456 const MachineFrameInfo *MFI = MF.getFrameInfo();
460457 const Function *F = MF.getFunction();
461 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
458 unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
462459 bool requiresRealignment =
463460 ((MFI->getMaxAlignment() > StackAlign) ||
464461 F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
2121 namespace llvm {
2222 class Type;
2323 class TargetInstrInfo;
24 class X86TargetMachine;
24 class X86Subtarget;
2525
2626 class X86RegisterInfo final : public X86GenRegisterInfo {
2727 public:
28 X86TargetMachine &TM;
28 const X86Subtarget &Subtarget;
2929
3030 private:
3131 /// Is64Bit - Is the target 64-bits.
5454 unsigned BasePtr;
5555
5656 public:
57 X86RegisterInfo(X86TargetMachine &tm);
57 X86RegisterInfo(const X86Subtarget &STI);
5858
5959 // FIXME: This should be tablegen'd like getDwarfRegNum is
6060 int getSEHRegNum(unsigned i) const;