llvm.org GIT mirror llvm / c6676d8
[mips] Honour -mno-odd-spreg for vector splat (again) Previous the lowering of FILL_FW would use the MSA128W register class when performing a vector splat. Instead it should be honouring -mno-odd-spreg and only use the even registers when performing a splat from word to vector register. Logical follow-on from r230235. This fixes PR/31369. A previous commit was missing the test case and had another differential in it. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D28373 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291566 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Dardis 2 years ago
2 changed file(s) with 61 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
33763376 DebugLoc DL = MI.getDebugLoc();
33773377 unsigned Wd = MI.getOperand(0).getReg();
33783378 unsigned Fs = MI.getOperand(1).getReg();
3379 unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3380 unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3379 unsigned Wt1 = RegInfo.createVirtualRegister(
3380 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
3381 : &Mips::MSA128WEvensRegClass);
3382 unsigned Wt2 = RegInfo.createVirtualRegister(
3383 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
3384 : &Mips::MSA128WEvensRegClass);
33813385
33823386 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
33833387 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
0 ; RUN: llc -march=mips -mcpu=mips32r5 -mattr=+fp64,+msa,+nooddspreg < %s | FileCheck %s
1
2 ; Test that the register allocator honours +nooddspreg and does not pick an odd
3 ; single precision subregister of an MSA register.
4
5 @f1 = external global float
6
7 @f2 = external global float
8
9 @v3 = external global <4 x float>
10
11 @d1 = external global double
12
13 define void @test() {
14 ; CHECK-LABEL: test:
15 entry:
16 ; CHECK-NOT: lwc1 $f{{[13579]+}}
17 ; CHECK: lwc1 $f{{[02468]+}}
18 %0 = load float, float * @f1
19 %1 = insertelement <4 x float> undef, float %0, i32 0
20 %2 = insertelement <4 x float> %1, float %0, i32 1
21 %3 = insertelement <4 x float> %2, float %0, i32 2
22 %4 = insertelement <4 x float> %3, float %0, i32 3
23
24 ; CHECK-NOT: lwc1 $f{{[13579]+}}
25 ; CHECK: lwc1 $f{{[02468]+}}
26 %5 = load float, float * @f2
27 %6 = insertelement <4 x float> undef, float %5, i32 0
28 %7 = insertelement <4 x float> %6, float %5, i32 1
29 %8 = insertelement <4 x float> %7, float %5, i32 2
30 %9 = insertelement <4 x float> %8, float %5, i32 3
31
32 %10 = fadd <4 x float> %4, %9
33 store <4 x float> %10, <4 x float> * @v3
34 ret void
35 }
36
37 ; Test that the register allocator hnours +noodspreg and does not pick an odd
38 ; single precision register for a load to perform a conversion to a double.
39
40 define void @test2() {
41 ; CHECK-LABEL: test2:
42 entry:
43 ; CHECK-NOT: lwc1 $f{{[13579]+}}
44 ; CHECK: lwc1 $f{{[02468]+}}
45 %0 = load float, float * @f1
46 %1 = fpext float %0 to double
47 ; CHECK-NOT: lwc1 $f{{[13579]+}}
48 ; CHECK: lwc1 $f{{[02468]+}}
49 %2 = load float, float * @f2
50 %3 = fpext float %2 to double
51 %4 = fadd double %1, %3
52 store double%4, double * @d1
53 ret void
54 }