llvm.org GIT mirror llvm / c60f9b7
Next round of MC refactoring. This patch factor MC table instantiations, MC registeration and creation code into XXXMCDesc libraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 8 years ago
134 changed file(s) with 1286 addition(s) and 496 deletion(s). Raw diff Collapse all Expand all
1515 #define TARGET_ARM_H
1616
1717 #include "ARMBaseInfo.h"
18 #include "MCTargetDesc/ARMMCTargetDesc.h"
1819 #include "llvm/Support/DataTypes.h"
1920 #include "llvm/Support/ErrorHandling.h"
2021 #include "llvm/Target/TargetMachine.h"
5657 FunctionPass *createThumb2ITBlockPass();
5758 FunctionPass *createThumb2SizeReductionPass();
5859
59 extern Target TheARMTarget, TheThumbTarget;
60
6160 void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
6261 ARMAsmPrinter &AP);
6362
3535 #include "llvm/Support/ErrorHandling.h"
3636 #include "llvm/ADT/STLExtras.h"
3737
38 #define GET_INSTRINFO_MC_DESC
3938 #define GET_INSTRINFO_CTOR
4039 #include "ARMGenInstrInfo.inc"
4140
3939 #include "llvm/ADT/SmallVector.h"
4040 #include "llvm/Support/CommandLine.h"
4141
42 #define GET_REGINFO_MC_DESC
4342 #define GET_REGINFO_TARGET_DESC
4443 #include "ARMGenRegisterInfo.inc"
4544
2424 #include "llvm/MC/MCSubtargetInfo.h"
2525 #include "llvm/ADT/Statistic.h"
2626 #include "llvm/Support/raw_ostream.h"
27
28 #define GET_SUBTARGETINFO_ENUM
29 #include "ARMGenSubtargetInfo.inc"
3027
3128 using namespace llvm;
3229
1717 #include "llvm/Support/CommandLine.h"
1818 #include "llvm/ADT/SmallVector.h"
1919
20 #define GET_SUBTARGETINFO_ENUM
21 #define GET_SUBTARGETINFO_MC_DESC
2220 #define GET_SUBTARGETINFO_TARGET_DESC
2321 #define GET_SUBTARGETINFO_CTOR
2422 #include "ARMGenSubtargetInfo.inc"
2929 #include "llvm/ADT/StringExtras.h"
3030 #include "llvm/ADT/StringSwitch.h"
3131 #include "llvm/ADT/Twine.h"
32
33 #define GET_SUBTARGETINFO_ENUM
34 #include "ARMGenSubtargetInfo.inc"
3532
3633 using namespace llvm;
3734
6969 ///
7070 /// { ARM::CCRRegClassID, 0|(1<
7171 ///
72 /// And this maps to one MCOperand with the regsiter kind of ARM::CPSR.
73 #define GET_INSTRINFO_MC_DESC
74 #include "ARMGenInstrInfo.inc"
72
73 namespace llvm {
74 extern const MCInstrDesc ARMInsts[];
75 }
7576
7677 using namespace llvm;
7778
2222 #define GET_INSTRINFO_MC_DESC
2323 #include "ARMGenInstrInfo.inc"
2424
25 #define GET_SUBTARGETINFO_ENUM
2625 #define GET_SUBTARGETINFO_MC_DESC
2726 #include "ARMGenSubtargetInfo.inc"
2827
4545 #define GET_INSTRINFO_ENUM
4646 #include "ARMGenInstrInfo.inc"
4747
48 #define GET_SUBTARGETINFO_ENUM
49 #include "ARMGenSubtargetInfo.inc"
50
4851 #endif
1414 #ifndef TARGET_ALPHA_H
1515 #define TARGET_ALPHA_H
1616
17 #include "MCTargetDesc/AlphaMCTargetDesc.h"
1718 #include "llvm/Target/TargetMachine.h"
1819
1920 namespace llvm {
3637 FunctionPass *createAlphaLLRPPass(AlphaTargetMachine &tm);
3738 FunctionPass *createAlphaBranchSelectionPass();
3839
39 extern Target TheAlphaTarget;
40
4140 } // end namespace llvm;
4241
43 // Defines symbolic names for Alpha registers. This defines a mapping from
44 // register name to register number.
45 //
46
47 #define GET_REGINFO_ENUM
48 #include "AlphaGenRegisterInfo.inc"
49
50 // Defines symbolic names for the Alpha instructions.
51 //
52 #define GET_INSTRINFO_ENUM
53 #include "AlphaGenInstrInfo.inc"
54
5542 #endif
2020 #include "llvm/ADT/SmallVector.h"
2121 #include "llvm/Support/ErrorHandling.h"
2222
23 #define GET_INSTRINFO_MC_DESC
2423 #define GET_INSTRINFO_CTOR
2524 #include "AlphaGenInstrInfo.inc"
2625 using namespace llvm;
381380 AlphaFI->setGlobalRetAddr(GlobalRetAddr);
382381 return GlobalRetAddr;
383382 }
384
385 MCInstrInfo *createAlphaMCInstrInfo() {
386 MCInstrInfo *X = new MCInstrInfo();
387 InitAlphaMCInstrInfo(X);
388 return X;
389 }
390
391 extern "C" void LLVMInitializeAlphaMCInstrInfo() {
392 TargetRegistry::RegisterMCInstrInfo(TheAlphaTarget, createAlphaMCInstrInfo);
393 }
3333 #include "llvm/ADT/STLExtras.h"
3434 #include
3535
36 #define GET_REGINFO_MC_DESC
3736 #define GET_REGINFO_TARGET_DESC
3837 #include "AlphaGenRegisterInfo.inc"
3938
1414 #include "Alpha.h"
1515 #include "llvm/Target/TargetRegistry.h"
1616
17 #define GET_SUBTARGETINFO_ENUM
18 #define GET_SUBTARGETINFO_MC_DESC
1917 #define GET_SUBTARGETINFO_TARGET_DESC
2018 #define GET_SUBTARGETINFO_CTOR
2119 #include "AlphaGenSubtargetInfo.inc"
3533 // Initialize scheduling itinerary for the specified CPU.
3634 InstrItins = getInstrItineraryForCPU(CPUName);
3735 }
38
39 MCSubtargetInfo *createAlphaMCSubtargetInfo(StringRef TT, StringRef CPU,
40 StringRef FS) {
41 MCSubtargetInfo *X = new MCSubtargetInfo();
42 InitAlphaMCSubtargetInfo(X, TT, CPU, FS);
43 return X;
44 }
45
46 extern "C" void LLVMInitializeAlphaMCSubtargetInfo() {
47 TargetRegistry::RegisterMCSubtargetInfo(TheAlphaTarget,
48 createAlphaMCSubtargetInfo);
49 }
2222 )
2323
2424 add_subdirectory(TargetInfo)
25 add_subdirectory(MCTargetDesc)
0 //===-- AlphaMCTargetDesc.cpp - Alpha Target Descriptions -------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Alpha specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "AlphaMCTargetDesc.h"
14 #include "llvm/MC/MCInstrInfo.h"
15 #include "llvm/MC/MCRegisterInfo.h"
16 #include "llvm/MC/MCSubtargetInfo.h"
17 #include "llvm/Target/TargetRegistry.h"
18
19 #define GET_INSTRINFO_MC_DESC
20 #include "AlphaGenInstrInfo.inc"
21
22 #define GET_SUBTARGETINFO_MC_DESC
23 #include "AlphaGenSubtargetInfo.inc"
24
25 #define GET_REGINFO_MC_DESC
26 #include "AlphaGenRegisterInfo.inc"
27
28 using namespace llvm;
29
30
31 MCInstrInfo *createAlphaMCInstrInfo() {
32 MCInstrInfo *X = new MCInstrInfo();
33 InitAlphaMCInstrInfo(X);
34 return X;
35 }
36
37 extern "C" void LLVMInitializeAlphaMCInstrInfo() {
38 TargetRegistry::RegisterMCInstrInfo(TheAlphaTarget, createAlphaMCInstrInfo);
39 }
40
41
42 MCSubtargetInfo *createAlphaMCSubtargetInfo(StringRef TT, StringRef CPU,
43 StringRef FS) {
44 MCSubtargetInfo *X = new MCSubtargetInfo();
45 InitAlphaMCSubtargetInfo(X, TT, CPU, FS);
46 return X;
47 }
48
49 extern "C" void LLVMInitializeAlphaMCSubtargetInfo() {
50 TargetRegistry::RegisterMCSubtargetInfo(TheAlphaTarget,
51 createAlphaMCSubtargetInfo);
52 }
0 //===-- AlphaMCTargetDesc.h - Alpha Target Descriptions ---------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Alpha specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef ALPHAMCTARGETDESC_H
14 #define ALPHAMCTARGETDESC_H
15
16 namespace llvm {
17 class MCSubtargetInfo;
18 class Target;
19 class StringRef;
20
21 extern Target TheAlphaTarget;
22
23 } // End llvm namespace
24
25 // Defines symbolic names for Alpha registers. This defines a mapping from
26 // register name to register number.
27 //
28 #define GET_REGINFO_ENUM
29 #include "AlphaGenRegisterInfo.inc"
30
31 // Defines symbolic names for the Alpha instructions.
32 //
33 #define GET_INSTRINFO_ENUM
34 #include "AlphaGenInstrInfo.inc"
35
36 #define GET_SUBTARGETINFO_ENUM
37 #include "AlphaGenSubtargetInfo.inc"
38
39 #endif
0 add_llvm_library(LLVMAlphaDesc AlphaMCTargetDesc.cpp)
0 ##===- lib/Target/Alpha/TargetDesc/Makefile ----------------*- Makefile -*-===##
1 #
2 # The LLVM Compiler Infrastructure
3 #
4 # This file is distributed under the University of Illinois Open Source
5 # License. See LICENSE.TXT for details.
6 #
7 ##===----------------------------------------------------------------------===##
8
9 LEVEL = ../../../..
10 LIBRARYNAME = LLVMAlphaDesc
11
12 # Hack: we need to include 'main' target directory to grab private headers
13 CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
14
15 include $(LEVEL)/Makefile.common
1515 AlphaGenAsmWriter.inc AlphaGenDAGISel.inc \
1616 AlphaGenCallingConv.inc AlphaGenSubtargetInfo.inc
1717
18 DIRS = TargetInfo
18 DIRS = TargetInfo MCTargetDesc
1919
2020 include $(LEVEL)/Makefile.common
1414 #ifndef TARGET_BLACKFIN_H
1515 #define TARGET_BLACKFIN_H
1616
17 #include "MCTargetDesc/BlackfinMCTargetDesc.h"
1718 #include "llvm/Target/TargetMachine.h"
1819
1920 namespace llvm {
2324
2425 FunctionPass *createBlackfinISelDag(BlackfinTargetMachine &TM,
2526 CodeGenOpt::Level OptLevel);
26 extern Target TheBlackfinTarget;
2727
2828 } // end namespace llvm
2929
30 // Defines symbolic names for Blackfin registers. This defines a mapping from
31 // register name to register number.
32 #define GET_REGINFO_ENUM
33 #include "BlackfinGenRegisterInfo.inc"
34
35 // Defines symbolic names for the Blackfin instructions.
36 #define GET_INSTRINFO_ENUM
37 #include "BlackfinGenInstrInfo.inc"
38
3930 #endif
2121 #include "llvm/Support/ErrorHandling.h"
2222
2323 #define GET_INSTRINFO_CTOR
24 #define GET_INSTRINFO_MC_DESC
2524 #include "BlackfinGenInstrInfo.inc"
2625
2726 using namespace llvm;
254253 SmallVectorImpl &NewMIs) const {
255254 llvm_unreachable("loadRegFromAddr not implemented");
256255 }
257
258 MCInstrInfo *createBlackfinMCInstrInfo() {
259 MCInstrInfo *X = new MCInstrInfo();
260 InitBlackfinMCInstrInfo(X);
261 return X;
262 }
263
264 extern "C" void LLVMInitializeBlackfinMCInstrInfo() {
265 TargetRegistry::RegisterMCInstrInfo(TheBlackfinTarget,
266 createBlackfinMCInstrInfo);
267 }
2929 #include "llvm/ADT/BitVector.h"
3030 #include "llvm/ADT/STLExtras.h"
3131
32 #define GET_REGINFO_MC_DESC
3332 #define GET_REGINFO_TARGET_DESC
3433 #include "BlackfinGenRegisterInfo.inc"
3534
1414 #include "Blackfin.h"
1515 #include "llvm/Target/TargetRegistry.h"
1616
17 #define GET_SUBTARGETINFO_ENUM
18 #define GET_SUBTARGETINFO_MC_DESC
1917 #define GET_SUBTARGETINFO_TARGET_DESC
2018 #define GET_SUBTARGETINFO_CTOR
2119 #include "BlackfinGenSubtargetInfo.inc"
4341 // Parse features string.
4442 ParseSubtargetFeatures(CPUName, FS);
4543 }
46
47 MCSubtargetInfo *createBlackfinMCSubtargetInfo(StringRef TT, StringRef CPU,
48 StringRef FS) {
49 MCSubtargetInfo *X = new MCSubtargetInfo();
50 InitBlackfinMCSubtargetInfo(X, TT, CPU, FS);
51 return X;
52 }
53
54 extern "C" void LLVMInitializeBlackfinMCSubtargetInfo() {
55 TargetRegistry::RegisterMCSubtargetInfo(TheBlackfinTarget,
56 createBlackfinMCSubtargetInfo);
57 }
2222 )
2323
2424 add_subdirectory(TargetInfo)
25 add_subdirectory(MCTargetDesc)
0 //===-- BlackfinMCTargetDesc.cpp - Blackfin Target Descriptions -*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Blackfin specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "BlackfinMCTargetDesc.h"
14 #include "llvm/MC/MCInstrInfo.h"
15 #include "llvm/MC/MCRegisterInfo.h"
16 #include "llvm/MC/MCSubtargetInfo.h"
17 #include "llvm/Target/TargetRegistry.h"
18
19 #define GET_INSTRINFO_MC_DESC
20 #include "BlackfinGenInstrInfo.inc"
21
22 #define GET_SUBTARGETINFO_MC_DESC
23 #include "BlackfinGenSubtargetInfo.inc"
24
25 #define GET_REGINFO_MC_DESC
26 #include "BlackfinGenRegisterInfo.inc"
27
28 using namespace llvm;
29
30
31 MCInstrInfo *createBlackfinMCInstrInfo() {
32 MCInstrInfo *X = new MCInstrInfo();
33 InitBlackfinMCInstrInfo(X);
34 return X;
35 }
36
37 extern "C" void LLVMInitializeBlackfinMCInstrInfo() {
38 TargetRegistry::RegisterMCInstrInfo(TheBlackfinTarget,
39 createBlackfinMCInstrInfo);
40 }
41
42
43 MCSubtargetInfo *createBlackfinMCSubtargetInfo(StringRef TT, StringRef CPU,
44 StringRef FS) {
45 MCSubtargetInfo *X = new MCSubtargetInfo();
46 InitBlackfinMCSubtargetInfo(X, TT, CPU, FS);
47 return X;
48 }
49
50 extern "C" void LLVMInitializeBlackfinMCSubtargetInfo() {
51 TargetRegistry::RegisterMCSubtargetInfo(TheBlackfinTarget,
52 createBlackfinMCSubtargetInfo);
53 }
0 //===-- BlackfinMCTargetDesc.h - Blackfin Target Descriptions ---*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Blackfin specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef BLACKFINMCTARGETDESC_H
14 #define BLACKFINMCTARGETDESC_H
15
16 namespace llvm {
17 class MCSubtargetInfo;
18 class Target;
19 class StringRef;
20
21 extern Target TheBlackfinTarget;
22
23 } // End llvm namespace
24
25 // Defines symbolic names for Blackfin registers. This defines a mapping from
26 // register name to register number.
27 #define GET_REGINFO_ENUM
28 #include "BlackfinGenRegisterInfo.inc"
29
30 // Defines symbolic names for the Blackfin instructions.
31 #define GET_INSTRINFO_ENUM
32 #include "BlackfinGenInstrInfo.inc"
33
34 #define GET_SUBTARGETINFO_ENUM
35 #include "BlackfinGenSubtargetInfo.inc"
36
37 #endif
0 add_llvm_library(LLVMBlackfinDesc BlackfinMCTargetDesc.cpp)
0 ##===- lib/Target/Blackfin/TargetDesc/Makefile -------------*- Makefile -*-===##
1 #
2 # The LLVM Compiler Infrastructure
3 #
4 # This file is distributed under the University of Illinois Open Source
5 # License. See LICENSE.TXT for details.
6 #
7 ##===----------------------------------------------------------------------===##
8
9 LEVEL = ../../../..
10 LIBRARYNAME = LLVMBlackfinDesc
11
12 # Hack: we need to include 'main' target directory to grab private headers
13 CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
14
15 include $(LEVEL)/Makefile.common
1616 BlackfinGenDAGISel.inc BlackfinGenSubtargetInfo.inc \
1717 BlackfinGenCallingConv.inc BlackfinGenIntrinsics.inc
1818
19 DIRS = TargetInfo
19 DIRS = TargetInfo MCTargetDesc
2020
2121 include $(LEVEL)/Makefile.common
2222
2323 )
2424
2525 add_subdirectory(TargetInfo)
26 add_subdirectory(MCTargetDesc)
0 add_llvm_library(LLVMCellSPUDesc SPUMCTargetDesc.cpp)
0 ##===- lib/Target/CellSPU/TargetDesc/Makefile --------------*- Makefile -*-===##
1 #
2 # The LLVM Compiler Infrastructure
3 #
4 # This file is distributed under the University of Illinois Open Source
5 # License. See LICENSE.TXT for details.
6 #
7 ##===----------------------------------------------------------------------===##
8
9 LEVEL = ../../../..
10 LIBRARYNAME = LLVMCellSPUDesc
11
12 # Hack: we need to include 'main' target directory to grab private headers
13 CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
14
15 include $(LEVEL)/Makefile.common
0 //===-- SPUMCTargetDesc.cpp - Cell SPU Target Descriptions -----*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Cell SPU specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "SPUMCTargetDesc.h"
14 #include "llvm/MC/MCInstrInfo.h"
15 #include "llvm/MC/MCRegisterInfo.h"
16 #include "llvm/MC/MCSubtargetInfo.h"
17 #include "llvm/Target/TargetRegistry.h"
18
19 #define GET_INSTRINFO_MC_DESC
20 #include "SPUGenInstrInfo.inc"
21
22 #define GET_SUBTARGETINFO_MC_DESC
23 #include "SPUGenSubtargetInfo.inc"
24
25 #define GET_REGINFO_MC_DESC
26 #include "SPUGenRegisterInfo.inc"
27
28 using namespace llvm;
29
30 MCInstrInfo *createSPUMCInstrInfo() {
31 MCInstrInfo *X = new MCInstrInfo();
32 InitSPUMCInstrInfo(X);
33 return X;
34 }
35
36 extern "C" void LLVMInitializeCellSPUMCInstrInfo() {
37 TargetRegistry::RegisterMCInstrInfo(TheCellSPUTarget, createSPUMCInstrInfo);
38 }
39
40 MCSubtargetInfo *createSPUMCSubtargetInfo(StringRef TT, StringRef CPU,
41 StringRef FS) {
42 MCSubtargetInfo *X = new MCSubtargetInfo();
43 InitSPUMCSubtargetInfo(X, TT, CPU, FS);
44 return X;
45 }
46
47 extern "C" void LLVMInitializeCellSPUMCSubtargetInfo() {
48 TargetRegistry::RegisterMCSubtargetInfo(TheCellSPUTarget,
49 createSPUMCSubtargetInfo);
50 }
0 //===-- SPUMCTargetDesc.h - Alpha Target Descriptions ---------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Alpha specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef SPUMCTARGETDESC_H
14 #define SPUMCTARGETDESC_H
15
16 namespace llvm {
17 class MCSubtargetInfo;
18 class Target;
19 class StringRef;
20
21 extern Target TheCellSPUTarget;
22
23 } // End llvm namespace
24
25 // Define symbolic names for Cell registers. This defines a mapping from
26 // register name to register number.
27 //
28 #define GET_REGINFO_ENUM
29 #include "SPUGenRegisterInfo.inc"
30
31 // Defines symbolic names for the SPU instructions.
32 //
33 #define GET_INSTRINFO_ENUM
34 #include "SPUGenInstrInfo.inc"
35
36 #define GET_SUBTARGETINFO_ENUM
37 #include "SPUGenSubtargetInfo.inc"
38
39 #endif
1414 SPUGenDAGISel.inc \
1515 SPUGenSubtargetInfo.inc SPUGenCallingConv.inc
1616
17 DIRS = TargetInfo
17 DIRS = TargetInfo MCTargetDesc
1818
1919 include $(LEVEL)/Makefile.common
1414 #ifndef LLVM_TARGET_IBMCELLSPU_H
1515 #define LLVM_TARGET_IBMCELLSPU_H
1616
17 #include "MCTargetDesc/SPUMCTargetDesc.h"
1718 #include "llvm/Target/TargetMachine.h"
1819
1920 namespace llvm {
2425 FunctionPass *createSPUISelDag(SPUTargetMachine &TM);
2526 FunctionPass *createSPUNopFillerPass(SPUTargetMachine &tm);
2627
27 extern Target TheCellSPUTarget;
2828 }
2929
30 // Defines symbolic names for the SPU instructions.
31 //
32 #define GET_INSTRINFO_ENUM
33 #include "SPUGenInstrInfo.inc"
34
3530 #endif /* LLVM_TARGET_IBMCELLSPU_H */
1212
1313 #include "SPU.h"
1414 #include "SPUFrameLowering.h"
15 #include "SPURegisterNames.h"
1615 #include "SPUInstrBuilder.h"
1716 #include "SPUInstrInfo.h"
1817 #include "llvm/Function.h"
1515 #include "SPUTargetMachine.h"
1616 #include "SPUHazardRecognizers.h"
1717 #include "SPUFrameLowering.h"
18 #include "SPURegisterNames.h"
1918 #include "SPUTargetMachine.h"
2019 #include "llvm/CodeGen/MachineConstantPool.h"
2120 #include "llvm/CodeGen/MachineInstrBuilder.h"
99 //
1010 //===----------------------------------------------------------------------===//
1111
12 #include "SPURegisterNames.h"
1312 #include "SPUISelLowering.h"
1413 #include "SPUTargetMachine.h"
1514 #include "SPUFrameLowering.h"
1010 //
1111 //===----------------------------------------------------------------------===//
1212
13 #include "SPURegisterNames.h"
1413 #include "SPUInstrInfo.h"
1514 #include "SPUInstrBuilder.h"
1615 #include "SPUTargetMachine.h"
2322 #include "llvm/Support/raw_ostream.h"
2423
2524 #define GET_INSTRINFO_CTOR
26 #define GET_INSTRINFO_MC_DESC
2725 #include "SPUGenInstrInfo.inc"
2826
2927 using namespace llvm;
450448
451449 return true;
452450 }
453
454 MCInstrInfo *createSPUMCInstrInfo() {
455 MCInstrInfo *X = new MCInstrInfo();
456 InitSPUMCInstrInfo(X);
457 return X;
458 }
459
460 extern "C" void LLVMInitializeCellSPUMCInstrInfo() {
461 TargetRegistry::RegisterMCInstrInfo(TheCellSPUTarget, createSPUMCInstrInfo);
462 }
1313 #define DEBUG_TYPE "reginfo"
1414 #include "SPU.h"
1515 #include "SPURegisterInfo.h"
16 #include "SPURegisterNames.h"
1716 #include "SPUInstrBuilder.h"
1817 #include "SPUSubtarget.h"
1918 #include "SPUMachineFunction.h"
4241 #include "llvm/ADT/STLExtras.h"
4342 #include
4443
45 #define GET_REGINFO_MC_DESC
4644 #define GET_REGINFO_TARGET_DESC
4745 #include "SPUGenRegisterInfo.inc"
4846
1616 #include "llvm/Target/TargetRegistry.h"
1717 #include "llvm/ADT/SmallVector.h"
1818
19 #define GET_SUBTARGETINFO_ENUM
20 #define GET_SUBTARGETINFO_MC_DESC
2119 #define GET_SUBTARGETINFO_TARGET_DESC
2220 #define GET_SUBTARGETINFO_CTOR
2321 #include "SPUGenSubtargetInfo.inc"
6563 CriticalPathRCs.push_back(&SPU::VECREGRegClass);
6664 return OptLevel >= CodeGenOpt::Default;
6765 }
68
69 MCSubtargetInfo *createSPUMCSubtargetInfo(StringRef TT, StringRef CPU,
70 StringRef FS) {
71 MCSubtargetInfo *X = new MCSubtargetInfo();
72 InitSPUMCSubtargetInfo(X, TT, CPU, FS);
73 return X;
74 }
75
76 extern "C" void LLVMInitializeCellSPUMCSubtargetInfo() {
77 TargetRegistry::RegisterMCSubtargetInfo(TheCellSPUTarget,
78 createSPUMCSubtargetInfo);
79 }
1111 //===----------------------------------------------------------------------===//
1212
1313 #include "SPU.h"
14 #include "SPURegisterNames.h"
1514 #include "SPUMCAsmInfo.h"
1615 #include "SPUTargetMachine.h"
1716 #include "llvm/PassManager.h"
3434 add_subdirectory(Disassembler)
3535 add_subdirectory(InstPrinter)
3636 add_subdirectory(TargetInfo)
37 add_subdirectory(MCTargetDesc)
2626
2727 // #include "MBlazeGenDecoderTables.inc"
2828 // #include "MBlazeGenRegisterNames.inc"
29 #define GET_INSTRINFO_MC_DESC
30 #include "MBlazeGenInstrInfo.inc"
3129 #include "MBlazeGenEDInfo.inc"
30
31 namespace llvm {
32 extern const MCInstrDesc MBlazeInsts[];
33 }
3234
3335 using namespace llvm;
3436
1414 #ifndef TARGET_MBLAZE_H
1515 #define TARGET_MBLAZE_H
1616
17 #include "MCTargetDesc/MBlazeMCTargetDesc.h"
1718 #include "llvm/Target/TargetMachine.h"
1819
1920 namespace llvm {
3536 FunctionPass *createMBlazeISelDag(MBlazeTargetMachine &TM);
3637 FunctionPass *createMBlazeDelaySlotFillerPass(MBlazeTargetMachine &TM);
3738
38 extern Target TheMBlazeTarget;
3939 } // end namespace llvm;
4040
41 // Defines symbolic names for MBlaze registers. This defines a mapping from
42 // register name to register number.
43 #define GET_REGINFO_ENUM
44 #include "MBlazeGenRegisterInfo.inc"
45
46 // Defines symbolic names for the MBlaze instructions.
47 #define GET_INSTRINFO_ENUM
48 #include "MBlazeGenInstrInfo.inc"
49
5041 #endif
2222 #include "llvm/ADT/STLExtras.h"
2323
2424 #define GET_INSTRINFO_CTOR
25 #define GET_INSTRINFO_MC_DESC
2625 #include "MBlazeGenInstrInfo.inc"
2726
2827 using namespace llvm;
294293 MBlazeFI->setGlobalBaseReg(GlobalBaseReg);
295294 return GlobalBaseReg;
296295 }
297
298 MCInstrInfo *createMBlazeMCInstrInfo() {
299 MCInstrInfo *X = new MCInstrInfo();
300 InitMBlazeMCInstrInfo(X);
301 return X;
302 }
303
304 extern "C" void LLVMInitializeMBlazeMCInstrInfo() {
305 TargetRegistry::RegisterMCInstrInfo(TheMBlazeTarget, createMBlazeMCInstrInfo);
306 }
3636 #include "llvm/ADT/BitVector.h"
3737 #include "llvm/ADT/STLExtras.h"
3838
39 #define GET_REGINFO_MC_DESC
4039 #define GET_REGINFO_TARGET_DESC
4140 #include "MBlazeGenRegisterInfo.inc"
4241
1616 #include "llvm/Support/CommandLine.h"
1717 #include "llvm/Target/TargetRegistry.h"
1818
19 #define GET_SUBTARGETINFO_ENUM
20 #define GET_SUBTARGETINFO_MC_DESC
2119 #define GET_SUBTARGETINFO_TARGET_DESC
2220 #define GET_SUBTARGETINFO_CTOR
2321 #include "MBlazeGenSubtargetInfo.inc"
6260 CriticalPathRCs.push_back(&MBlaze::GPRRegClass);
6361 return HasItin && OptLevel >= CodeGenOpt::Default;
6462 }
65
66 MCSubtargetInfo *createMBlazeMCSubtargetInfo(StringRef TT, StringRef CPU,
67 StringRef FS) {
68 MCSubtargetInfo *X = new MCSubtargetInfo();
69 InitMBlazeMCSubtargetInfo(X, TT, CPU, FS);
70 return X;
71 }
72
73 extern "C" void LLVMInitializeMBlazeMCSubtargetInfo() {
74 TargetRegistry::RegisterMCSubtargetInfo(TheMBlazeTarget,
75 createMBlazeMCSubtargetInfo);
76 }
0 add_llvm_library(LLVMMBlazeDesc MBlazeMCTargetDesc.cpp)
0 //===-- MBlazeMCTargetDesc.cpp - MBlaze Target Descriptions -----*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides MBlaze specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "MBlazeMCTargetDesc.h"
14 #include "llvm/MC/MCInstrInfo.h"
15 #include "llvm/MC/MCRegisterInfo.h"
16 #include "llvm/MC/MCSubtargetInfo.h"
17 #include "llvm/Target/TargetRegistry.h"
18
19 #define GET_INSTRINFO_MC_DESC
20 #include "MBlazeGenInstrInfo.inc"
21
22 #define GET_SUBTARGETINFO_MC_DESC
23 #include "MBlazeGenSubtargetInfo.inc"
24
25 #define GET_REGINFO_MC_DESC
26 #include "MBlazeGenRegisterInfo.inc"
27
28 using namespace llvm;
29
30
31 MCInstrInfo *createMBlazeMCInstrInfo() {
32 MCInstrInfo *X = new MCInstrInfo();
33 InitMBlazeMCInstrInfo(X);
34 return X;
35 }
36
37 extern "C" void LLVMInitializeMBlazeMCInstrInfo() {
38 TargetRegistry::RegisterMCInstrInfo(TheMBlazeTarget, createMBlazeMCInstrInfo);
39 }
40
41 MCSubtargetInfo *createMBlazeMCSubtargetInfo(StringRef TT, StringRef CPU,
42 StringRef FS) {
43 MCSubtargetInfo *X = new MCSubtargetInfo();
44 InitMBlazeMCSubtargetInfo(X, TT, CPU, FS);
45 return X;
46 }
47
48 extern "C" void LLVMInitializeMBlazeMCSubtargetInfo() {
49 TargetRegistry::RegisterMCSubtargetInfo(TheMBlazeTarget,
50 createMBlazeMCSubtargetInfo);
51 }
0 //===-- MBlazeMCTargetDesc.h - MBlaze Target Descriptions -------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides MBlaze specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef MBLAZEMCTARGETDESC_H
14 #define MBLAZEMCTARGETDESC_H
15
16 namespace llvm {
17 class MCSubtargetInfo;
18 class Target;
19 class StringRef;
20
21 extern Target TheMBlazeTarget;
22
23 } // End llvm namespace
24
25 // Defines symbolic names for MBlaze registers. This defines a mapping from
26 // register name to register number.
27 #define GET_REGINFO_ENUM
28 #include "MBlazeGenRegisterInfo.inc"
29
30 // Defines symbolic names for the MBlaze instructions.
31 #define GET_INSTRINFO_ENUM
32 #include "MBlazeGenInstrInfo.inc"
33
34 #define GET_SUBTARGETINFO_ENUM
35 #include "MBlazeGenSubtargetInfo.inc"
36
37 #endif
0 ##===- lib/Target/MBlaze/TargetDesc/Makefile ---------------*- Makefile -*-===##
1 #
2 # The LLVM Compiler Infrastructure
3 #
4 # This file is distributed under the University of Illinois Open Source
5 # License. See LICENSE.TXT for details.
6 #
7 ##===----------------------------------------------------------------------===##
8
9 LEVEL = ../../../..
10 LIBRARYNAME = LLVMMBlazeDesc
11
12 # Hack: we need to include 'main' target directory to grab private headers
13 CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
14
15 include $(LEVEL)/Makefile.common
1717 MBlazeGenSubtargetInfo.inc MBlazeGenIntrinsics.inc \
1818 MBlazeGenEDInfo.inc
1919
20 DIRS = InstPrinter AsmParser Disassembler TargetInfo
20 DIRS = InstPrinter AsmParser Disassembler TargetInfo MCTargetDesc
2121
2222 include $(LEVEL)/Makefile.common
2323
2323
2424 add_subdirectory(InstPrinter)
2525 add_subdirectory(TargetInfo)
26 add_subdirectory(MCTargetDesc)
0 add_llvm_library(LLVMMSP430Desc MSP430MCTargetDesc.cpp)
0 //===-- MSP430MCTargetDesc.cpp - MSP430 Target Descriptions -----*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides MSP430 specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "MSP430MCTargetDesc.h"
14 #include "llvm/MC/MCInstrInfo.h"
15 #include "llvm/MC/MCRegisterInfo.h"
16 #include "llvm/MC/MCSubtargetInfo.h"
17 #include "llvm/Target/TargetRegistry.h"
18
19 #define GET_INSTRINFO_MC_DESC
20 #include "MSP430GenInstrInfo.inc"
21
22 #define GET_SUBTARGETINFO_MC_DESC
23 #include "MSP430GenSubtargetInfo.inc"
24
25 #define GET_REGINFO_MC_DESC
26 #include "MSP430GenRegisterInfo.inc"
27
28 using namespace llvm;
29
30
31 MCInstrInfo *createMSP430MCInstrInfo() {
32 MCInstrInfo *X = new MCInstrInfo();
33 InitMSP430MCInstrInfo(X);
34 return X;
35 }
36
37 extern "C" void LLVMInitializeMSP430MCInstrInfo() {
38 TargetRegistry::RegisterMCInstrInfo(TheMSP430Target, createMSP430MCInstrInfo);
39 }
40
41
42 MCSubtargetInfo *createMSP430MCSubtargetInfo(StringRef TT, StringRef CPU,
43 StringRef FS) {
44 MCSubtargetInfo *X = new MCSubtargetInfo();
45 InitMSP430MCSubtargetInfo(X, TT, CPU, FS);
46 return X;
47 }
48
49 extern "C" void LLVMInitializeMSP430MCSubtargetInfo() {
50 TargetRegistry::RegisterMCSubtargetInfo(TheMSP430Target,
51 createMSP430MCSubtargetInfo);
52 }
0 //===-- MSP430MCTargetDesc.h - MSP430 Target Descriptions -------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides MSP430 specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef ALPHAMCTARGETDESC_H
14 #define ALPHAMCTARGETDESC_H
15
16 namespace llvm {
17 class MCSubtargetInfo;
18 class Target;
19 class StringRef;
20
21 extern Target TheMSP430Target;
22
23 } // End llvm namespace
24
25 // Defines symbolic names for MSP430 registers.
26 // This defines a mapping from register name to register number.
27 #define GET_REGINFO_ENUM
28 #include "MSP430GenRegisterInfo.inc"
29
30 // Defines symbolic names for the MSP430 instructions.
31 #define GET_INSTRINFO_ENUM
32 #include "MSP430GenInstrInfo.inc"
33
34 #define GET_SUBTARGETINFO_ENUM
35 #include "MSP430GenSubtargetInfo.inc"
36
37 #endif
0 ##===- lib/Target/MSP430/TargetDesc/Makefile ---------------*- Makefile -*-===##
1 #
2 # The LLVM Compiler Infrastructure
3 #
4 # This file is distributed under the University of Illinois Open Source
5 # License. See LICENSE.TXT for details.
6 #
7 ##===----------------------------------------------------------------------===##
8
9 LEVEL = ../../../..
10 LIBRARYNAME = LLVMMSP430Desc
11
12 # Hack: we need to include 'main' target directory to grab private headers
13 CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
14
15 include $(LEVEL)/Makefile.common
1414 #ifndef LLVM_TARGET_MSP430_H
1515 #define LLVM_TARGET_MSP430_H
1616
17 #include "MCTargetDesc/MSP430MCTargetDesc.h"
1718 #include "llvm/Target/TargetMachine.h"
1819
1920 namespace MSP430CC {
4041
4142 FunctionPass *createMSP430BranchSelectionPass();
4243
43 extern Target TheMSP430Target;
44
4544 } // end namespace llvm;
4645
47 // Defines symbolic names for MSP430 registers.
48 // This defines a mapping from register name to register number.
49 #define GET_REGINFO_ENUM
50 #include "MSP430GenRegisterInfo.inc"
51
52 // Defines symbolic names for the MSP430 instructions.
53 #define GET_INSTRINFO_ENUM
54 #include "MSP430GenInstrInfo.inc"
55
5646 #endif
2323 #include "llvm/Support/ErrorHandling.h"
2424
2525 #define GET_INSTRINFO_CTOR
26 #define GET_INSTRINFO_MC_DESC
2726 #include "MSP430GenInstrInfo.inc"
2827
2928 using namespace llvm;
334333
335334 return 6;
336335 }
337
338 MCInstrInfo *createMSP430MCInstrInfo() {
339 MCInstrInfo *X = new MCInstrInfo();
340 InitMSP430MCInstrInfo(X);
341 return X;
342 }
343
344 extern "C" void LLVMInitializeMSP430MCInstrInfo() {
345 TargetRegistry::RegisterMCInstrInfo(TheMSP430Target, createMSP430MCInstrInfo);
346 }
2525 #include "llvm/ADT/BitVector.h"
2626 #include "llvm/Support/ErrorHandling.h"
2727
28 #define GET_REGINFO_MC_DESC
2928 #define GET_REGINFO_TARGET_DESC
3029 #include "MSP430GenRegisterInfo.inc"
3130
1414 #include "MSP430.h"
1515 #include "llvm/Target/TargetRegistry.h"
1616
17 #define GET_SUBTARGETINFO_ENUM
18 #define GET_SUBTARGETINFO_MC_DESC
1917 #define GET_SUBTARGETINFO_TARGET_DESC
2018 #define GET_SUBTARGETINFO_CTOR
2119 #include "MSP430GenSubtargetInfo.inc"
3129 // Parse features string.
3230 ParseSubtargetFeatures(CPUName, FS);
3331 }
34
35 MCSubtargetInfo *createMSP430MCSubtargetInfo(StringRef TT, StringRef CPU,
36 StringRef FS) {
37 MCSubtargetInfo *X = new MCSubtargetInfo();
38 InitMSP430MCSubtargetInfo(X, TT, CPU, FS);
39 return X;
40 }
41
42 extern "C" void LLVMInitializeMSP430MCSubtargetInfo() {
43 TargetRegistry::RegisterMCSubtargetInfo(TheMSP430Target,
44 createMSP430MCSubtargetInfo);
45 }
1616 MSP430GenDAGISel.inc MSP430GenCallingConv.inc \
1717 MSP430GenSubtargetInfo.inc
1818
19 DIRS = InstPrinter TargetInfo
19 DIRS = InstPrinter TargetInfo MCTargetDesc
2020
2121 include $(LEVEL)/Makefile.common
2222
2727
2828 add_subdirectory(InstPrinter)
2929 add_subdirectory(TargetInfo)
30 add_subdirectory(MCTargetDesc)
0 add_llvm_library(LLVMMipsDesc MipsMCTargetDesc.cpp)
0 ##===- lib/Target/Mips/TargetDesc/Makefile -----------------*- Makefile -*-===##
1 #
2 # The LLVM Compiler Infrastructure
3 #
4 # This file is distributed under the University of Illinois Open Source
5 # License. See LICENSE.TXT for details.
6 #
7 ##===----------------------------------------------------------------------===##
8
9 LEVEL = ../../../..
10 LIBRARYNAME = LLVMMipsDesc
11
12 # Hack: we need to include 'main' target directory to grab private headers
13 CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
14
15 include $(LEVEL)/Makefile.common
0 //===-- MipsMCTargetDesc.cpp - Mips Target Descriptions ---------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Mips specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "MipsMCTargetDesc.h"
14 #include "llvm/MC/MCInstrInfo.h"
15 #include "llvm/MC/MCRegisterInfo.h"
16 #include "llvm/MC/MCSubtargetInfo.h"
17 #include "llvm/Target/TargetRegistry.h"
18
19 #define GET_INSTRINFO_MC_DESC
20 #include "MipsGenInstrInfo.inc"
21
22 #define GET_SUBTARGETINFO_MC_DESC
23 #include "MipsGenSubtargetInfo.inc"
24
25 #define GET_REGINFO_MC_DESC
26 #include "MipsGenRegisterInfo.inc"
27
28 using namespace llvm;
29
30 MCInstrInfo *createMipsMCInstrInfo() {
31 MCInstrInfo *X = new MCInstrInfo();
32 InitMipsMCInstrInfo(X);
33 return X;
34 }
35
36 extern "C" void LLVMInitializeMipsMCInstrInfo() {
37 TargetRegistry::RegisterMCInstrInfo(TheMipsTarget, createMipsMCInstrInfo);
38 }
39
40
41 MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU,
42 StringRef FS) {
43 MCSubtargetInfo *X = new MCSubtargetInfo();
44 InitMipsMCSubtargetInfo(X, TT, CPU, FS);
45 return X;
46 }
47
48 extern "C" void LLVMInitializeMipsMCSubtargetInfo() {
49 TargetRegistry::RegisterMCSubtargetInfo(TheMipsTarget,
50 createMipsMCSubtargetInfo);
51 }
0 //===-- AlphaMCTargetDesc.h - Alpha Target Descriptions ---------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Alpha specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef ALPHAMCTARGETDESC_H
14 #define ALPHAMCTARGETDESC_H
15
16 namespace llvm {
17 class MCSubtargetInfo;
18 class Target;
19 class StringRef;
20
21 extern Target TheMipsTarget;
22 extern Target TheMipselTarget;
23
24 } // End llvm namespace
25
26 // Defines symbolic names for Mips registers. This defines a mapping from
27 // register name to register number.
28 #define GET_REGINFO_ENUM
29 #include "MipsGenRegisterInfo.inc"
30
31 // Defines symbolic names for the Mips instructions.
32 #define GET_INSTRINFO_ENUM
33 #include "MipsGenInstrInfo.inc"
34
35 #define GET_SUBTARGETINFO_ENUM
36 #include "MipsGenSubtargetInfo.inc"
37
38 #endif
1616 MipsGenDAGISel.inc MipsGenCallingConv.inc \
1717 MipsGenSubtargetInfo.inc
1818
19 DIRS = InstPrinter TargetInfo
19 DIRS = InstPrinter TargetInfo MCTargetDesc
2020
2121 include $(LEVEL)/Makefile.common
2222
1414 #ifndef TARGET_MIPS_H
1515 #define TARGET_MIPS_H
1616
17 #include "MCTargetDesc/MipsMCTargetDesc.h"
1718 #include "llvm/Target/TargetMachine.h"
1819
1920 namespace llvm {
2728 FunctionPass *createMipsExpandPseudoPass(MipsTargetMachine &TM);
2829 FunctionPass *createMipsEmitGPRestorePass(MipsTargetMachine &TM);
2930
30 extern Target TheMipsTarget;
31 extern Target TheMipselTarget;
32
3331 } // end namespace llvm;
3432
35 // Defines symbolic names for Mips registers. This defines a mapping from
36 // register name to register number.
37 #define GET_REGINFO_ENUM
38 #include "MipsGenRegisterInfo.inc"
39
40 // Defines symbolic names for the Mips instructions.
41 #define GET_INSTRINFO_ENUM
42 #include "MipsGenInstrInfo.inc"
43
4433 #endif
2121 #include "llvm/ADT/STLExtras.h"
2222
2323 #define GET_INSTRINFO_CTOR
24 #define GET_INSTRINFO_MC_DESC
2524 #include "MipsGenInstrInfo.inc"
2625
2726 using namespace llvm;
459458 MipsFI->setGlobalBaseReg(GlobalBaseReg);
460459 return GlobalBaseReg;
461460 }
462
463 MCInstrInfo *createMipsMCInstrInfo() {
464 MCInstrInfo *X = new MCInstrInfo();
465 InitMipsMCInstrInfo(X);
466 return X;
467 }
468
469 extern "C" void LLVMInitializeMipsMCInstrInfo() {
470 TargetRegistry::RegisterMCInstrInfo(TheMipsTarget, createMipsMCInstrInfo);
471 }
3636 #include "llvm/ADT/STLExtras.h"
3737 #include "llvm/Analysis/DebugInfo.h"
3838
39 #define GET_REGINFO_MC_DESC
4039 #define GET_REGINFO_TARGET_DESC
4140 #include "MipsGenRegisterInfo.inc"
4241
1414 #include "Mips.h"
1515 #include "llvm/Target/TargetRegistry.h"
1616
17 #define GET_SUBTARGETINFO_ENUM
18 #define GET_SUBTARGETINFO_MC_DESC
1917 #define GET_SUBTARGETINFO_TARGET_DESC
2018 #define GET_SUBTARGETINFO_CTOR
2119 #include "MipsGenSubtargetInfo.inc"
6159 HasCondMov = true;
6260 }
6361 }
64
65 MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU,
66 StringRef FS) {
67 MCSubtargetInfo *X = new MCSubtargetInfo();
68 InitMipsMCSubtargetInfo(X, TT, CPU, FS);
69 return X;
70 }
71
72 extern "C" void LLVMInitializeMipsMCSubtargetInfo() {
73 TargetRegistry::RegisterMCSubtargetInfo(TheMipsTarget,
74 createMipsMCSubtargetInfo);
75 }
2121 )
2222
2323 add_subdirectory(TargetInfo)
24 add_subdirectory(MCTargetDesc)
0 add_llvm_library(LLVMPTXDesc PTXMCTargetDesc.cpp)
0 ##===- lib/Target/PTX/TargetDesc/Makefile ------------------*- Makefile -*-===##
1 #
2 # The LLVM Compiler Infrastructure
3 #
4 # This file is distributed under the University of Illinois Open Source
5 # License. See LICENSE.TXT for details.
6 #
7 ##===----------------------------------------------------------------------===##
8
9 LEVEL = ../../../..
10 LIBRARYNAME = LLVMPTXDesc
11
12 # Hack: we need to include 'main' target directory to grab private headers
13 CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
14
15 include $(LEVEL)/Makefile.common
0 //===-- PTXMCTargetDesc.cpp - PTX Target Descriptions -----------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides PTX specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "PTXMCTargetDesc.h"
14 #include "llvm/MC/MCInstrInfo.h"
15 #include "llvm/MC/MCRegisterInfo.h"
16 #include "llvm/MC/MCSubtargetInfo.h"
17 #include "llvm/Target/TargetRegistry.h"
18
19 #define GET_INSTRINFO_MC_DESC
20 #include "PTXGenInstrInfo.inc"
21
22 #define GET_SUBTARGETINFO_MC_DESC
23 #include "PTXGenSubtargetInfo.inc"
24
25 #define GET_REGINFO_MC_DESC
26 #include "PTXGenRegisterInfo.inc"
27
28 using namespace llvm;
29
30 MCInstrInfo *createPTXMCInstrInfo() {
31 MCInstrInfo *X = new MCInstrInfo();
32 InitPTXMCInstrInfo(X);
33 return X;
34 }
35
36 extern "C" void LLVMInitializePTXMCInstrInfo() {
37 TargetRegistry::RegisterMCInstrInfo(ThePTX32Target, createPTXMCInstrInfo);
38 TargetRegistry::RegisterMCInstrInfo(ThePTX64Target, createPTXMCInstrInfo);
39 }
40
41 MCSubtargetInfo *createPTXMCSubtargetInfo(StringRef TT, StringRef CPU,
42 StringRef FS) {
43 MCSubtargetInfo *X = new MCSubtargetInfo();
44 InitPTXMCSubtargetInfo(X, TT, CPU, FS);
45 return X;
46 }
47
48 extern "C" void LLVMInitializePTXMCSubtargetInfo() {
49 TargetRegistry::RegisterMCSubtargetInfo(ThePTX32Target,
50 createPTXMCSubtargetInfo);
51 TargetRegistry::RegisterMCSubtargetInfo(ThePTX64Target,
52 createPTXMCSubtargetInfo);
53 }
0 //===-- PTXMCTargetDesc.h - PTX Target Descriptions ------------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides PTX specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef PTXMCTARGETDESC_H
14 #define PTXMCTARGETDESC_H
15
16 namespace llvm {
17 class MCSubtargetInfo;
18 class Target;
19 class StringRef;
20
21 extern Target ThePTX32Target;
22 extern Target ThePTX64Target;
23
24 } // End llvm namespace
25
26 // Defines symbolic names for PTX registers.
27 #define GET_REGINFO_ENUM
28 #include "PTXGenRegisterInfo.inc"
29
30 // Defines symbolic names for the PTX instructions.
31 #define GET_INSTRINFO_ENUM
32 #include "PTXGenInstrInfo.inc"
33
34 #define GET_SUBTARGETINFO_ENUM
35 #include "PTXGenSubtargetInfo.inc"
36
37 #endif
1818 PTXGenRegisterInfo.inc \
1919 PTXGenSubtargetInfo.inc
2020
21 DIRS = TargetInfo
21 DIRS = TargetInfo MCTargetDesc
2222
2323 include $(LEVEL)/Makefile.common
1414 #ifndef PTX_H
1515 #define PTX_H
1616
17 #include "MCTargetDesc/PTXMCTargetDesc.h"
1718 #include "llvm/Target/TargetMachine.h"
1819
1920 namespace llvm {
4142 FunctionPass *createPTXMFInfoExtract(PTXTargetMachine &TM,
4243 CodeGenOpt::Level OptLevel);
4344
44 extern Target ThePTX32Target;
45 extern Target ThePTX64Target;
4645 } // namespace llvm;
4746
48 // Defines symbolic names for PTX registers.
49 #define GET_REGINFO_ENUM
50 #include "PTXGenRegisterInfo.inc"
51
52 // Defines symbolic names for the PTX instructions.
53 #define GET_INSTRINFO_ENUM
54 #include "PTXGenInstrInfo.inc"
55
5647 #endif // PTX_H
2222 #include "llvm/Support/raw_ostream.h"
2323
2424 #define GET_INSTRINFO_CTOR
25 #define GET_INSTRINFO_MC_DESC
2625 #include "PTXGenInstrInfo.inc"
2726
2827 using namespace llvm;
408407 assert(target.isMBB() && "FIXME: detect branch target operand");
409408 return target.getMBB();
410409 }
411
412 MCInstrInfo *createPTXMCInstrInfo() {
413 MCInstrInfo *X = new MCInstrInfo();
414 InitPTXMCInstrInfo(X);
415 return X;
416 }
417
418 extern "C" void LLVMInitializePTXMCInstrInfo() {
419 TargetRegistry::RegisterMCInstrInfo(ThePTX32Target, createPTXMCInstrInfo);
420 TargetRegistry::RegisterMCInstrInfo(ThePTX64Target, createPTXMCInstrInfo);
421 }
1616 #include "llvm/Support/Debug.h"
1717 #include "llvm/Support/raw_ostream.h"
1818
19 #define GET_REGINFO_MC_DESC
2019 #define GET_REGINFO_TARGET_DESC
2120 #include "PTXGenRegisterInfo.inc"
2221
1515 #include "llvm/Support/ErrorHandling.h"
1616 #include "llvm/Target/TargetRegistry.h"
1717
18 #define GET_SUBTARGETINFO_ENUM
19 #define GET_SUBTARGETINFO_MC_DESC
2018 #define GET_SUBTARGETINFO_TARGET_DESC
2119 #define GET_SUBTARGETINFO_CTOR
2220 #include "PTXGenSubtargetInfo.inc"
6563 case PTX_VERSION_2_3: return "2.3";
6664 }
6765 }
68
69
70 MCSubtargetInfo *createPTXMCSubtargetInfo(StringRef TT, StringRef CPU,
71 StringRef FS) {
72 MCSubtargetInfo *X = new MCSubtargetInfo();
73 InitPTXMCSubtargetInfo(X, TT, CPU, FS);
74 return X;
75 }
76
77 extern "C" void LLVMInitializePTXMCSubtargetInfo() {
78 TargetRegistry::RegisterMCSubtargetInfo(ThePTX32Target,
79 createPTXMCSubtargetInfo);
80 TargetRegistry::RegisterMCSubtargetInfo(ThePTX64Target,
81 createPTXMCSubtargetInfo);
82 }
3131
3232 add_subdirectory(InstPrinter)
3333 add_subdirectory(TargetInfo)
34 add_subdirectory(MCTargetDesc)
0 add_llvm_library(LLVMPowerPCDesc PPCMCTargetDesc.cpp)
0 ##===- lib/Target/PowerPC/TargetDesc/Makefile --------------*- Makefile -*-===##
1 #
2 # The LLVM Compiler Infrastructure
3 #
4 # This file is distributed under the University of Illinois Open Source
5 # License. See LICENSE.TXT for details.
6 #
7 ##===----------------------------------------------------------------------===##
8
9 LEVEL = ../../../..
10 LIBRARYNAME = LLVMPowerPCDesc
11
12 # Hack: we need to include 'main' target directory to grab private headers
13 CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
14
15 include $(LEVEL)/Makefile.common
0 //===-- PPCMCTargetDesc.cpp - PowerPC Target Descriptions -------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides PowerPC specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "PPCMCTargetDesc.h"
14 #include "llvm/MC/MCInstrInfo.h"
15 #include "llvm/MC/MCRegisterInfo.h"
16 #include "llvm/MC/MCSubtargetInfo.h"
17 #include "llvm/Target/TargetRegistry.h"
18
19 #define GET_INSTRINFO_MC_DESC
20 #include "PPCGenInstrInfo.inc"
21
22 #define GET_SUBTARGETINFO_MC_DESC
23 #include "PPCGenSubtargetInfo.inc"
24
25 #define GET_REGINFO_MC_DESC
26 #include "PPCGenRegisterInfo.inc"
27
28 using namespace llvm;
29
30 MCInstrInfo *createPPCMCInstrInfo() {
31 MCInstrInfo *X = new MCInstrInfo();
32 InitPPCMCInstrInfo(X);
33 return X;
34 }
35
36 extern "C" void LLVMInitializePowerPCMCInstrInfo() {
37 TargetRegistry::RegisterMCInstrInfo(ThePPC32Target, createPPCMCInstrInfo);
38 TargetRegistry::RegisterMCInstrInfo(ThePPC64Target, createPPCMCInstrInfo);
39 }
40
41
42 MCSubtargetInfo *createPPCMCSubtargetInfo(StringRef TT, StringRef CPU,
43 StringRef FS) {
44 MCSubtargetInfo *X = new MCSubtargetInfo();
45 InitPPCMCSubtargetInfo(X, TT, CPU, FS);
46 return X;
47 }
48
49 extern "C" void LLVMInitializePowerPCMCSubtargetInfo() {
50 TargetRegistry::RegisterMCSubtargetInfo(ThePPC32Target,
51 createPPCMCSubtargetInfo);
52 TargetRegistry::RegisterMCSubtargetInfo(ThePPC64Target,
53 createPPCMCSubtargetInfo);
54 }
0 //===-- PPCMCTargetDesc.h - PowerPC Target Descriptions ---------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides PowerPC specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef PPCMCTARGETDESC_H
14 #define PPCMCTARGETDESC_H
15
16 namespace llvm {
17 class MCSubtargetInfo;
18 class Target;
19 class StringRef;
20
21 extern Target ThePPC32Target;
22 extern Target ThePPC64Target;
23
24 } // End llvm namespace
25
26 // Defines symbolic names for PowerPC registers. This defines a mapping from
27 // register name to register number.
28 //
29 #define GET_REGINFO_ENUM
30 #include "PPCGenRegisterInfo.inc"
31
32 // Defines symbolic names for the PowerPC instructions.
33 //
34 #define GET_INSTRINFO_ENUM
35 #include "PPCGenInstrInfo.inc"
36
37 #define GET_SUBTARGETINFO_ENUM
38 #include "PPCGenSubtargetInfo.inc"
39
40 #endif
1717 PPCGenSubtargetInfo.inc PPCGenCallingConv.inc \
1818 PPCGenMCCodeEmitter.inc
1919
20 DIRS = InstPrinter TargetInfo
20 DIRS = InstPrinter TargetInfo MCTargetDesc
2121
2222 include $(LEVEL)/Makefile.common
1414 #ifndef LLVM_TARGET_POWERPC_H
1515 #define LLVM_TARGET_POWERPC_H
1616
17 #include "MCTargetDesc/PPCMCTargetDesc.h"
1718 #include
1819
1920 // GCC #defines PPC on Linux but we use it as our namespace name
4647
4748 void LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
4849 AsmPrinter &AP, bool isDarwin);
49
50 extern Target ThePPC32Target;
51 extern Target ThePPC64Target;
5250
5351 namespace PPCII {
5452
8381
8482 } // end namespace llvm;
8583
86 // Defines symbolic names for PowerPC registers. This defines a mapping from
87 // register name to register number.
88 //
89 #define GET_REGINFO_ENUM
90 #include "PPCGenRegisterInfo.inc"
91
92 // Defines symbolic names for the PowerPC instructions.
93 //
94 #define GET_INSTRINFO_ENUM
95 #include "PPCGenInstrInfo.inc"
96
9784 #endif
3030 #include "llvm/ADT/STLExtras.h"
3131
3232 #define GET_INSTRINFO_CTOR
33 #define GET_INSTRINFO_MC_DESC
3433 #include "PPCGenInstrInfo.inc"
3534
3635 namespace llvm {
653652 return 4; // PowerPC instructions are all 4 bytes
654653 }
655654 }
656
657 MCInstrInfo *createPPCMCInstrInfo() {
658 MCInstrInfo *X = new MCInstrInfo();
659 InitPPCMCInstrInfo(X);
660 return X;
661 }
662
663 extern "C" void LLVMInitializePowerPCMCInstrInfo() {
664 TargetRegistry::RegisterMCInstrInfo(ThePPC32Target, createPPCMCInstrInfo);
665 TargetRegistry::RegisterMCInstrInfo(ThePPC64Target, createPPCMCInstrInfo);
666 }
4343 #include "llvm/ADT/STLExtras.h"
4444 #include
4545
46 #define GET_REGINFO_MC_DESC
4746 #define GET_REGINFO_TARGET_DESC
4847 #include "PPCGenRegisterInfo.inc"
4948
1717 #include "llvm/Target/TargetRegistry.h"
1818 #include
1919
20 #define GET_SUBTARGETINFO_ENUM
21 #define GET_SUBTARGETINFO_MC_DESC
2220 #define GET_SUBTARGETINFO_TARGET_DESC
2321 #define GET_SUBTARGETINFO_CTOR
2422 #include "PPCGenSubtargetInfo.inc"
140138 return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
141139 GV->hasCommonLinkage() || isDecl;
142140 }
143
144 MCSubtargetInfo *createPPCMCSubtargetInfo(StringRef TT, StringRef CPU,
145 StringRef FS) {
146 MCSubtargetInfo *X = new MCSubtargetInfo();
147 InitPPCMCSubtargetInfo(X, TT, CPU, FS);
148 return X;
149 }
150
151 extern "C" void LLVMInitializePowerPCMCSubtargetInfo() {
152 TargetRegistry::RegisterMCSubtargetInfo(ThePPC32Target,
153 createPPCMCSubtargetInfo);
154 TargetRegistry::RegisterMCSubtargetInfo(ThePPC64Target,
155 createPPCMCSubtargetInfo);
156 }
2222 )
2323
2424 add_subdirectory(TargetInfo)
25 add_subdirectory(MCTargetDesc)
0 add_llvm_library(LLVMSparcDesc SparcMCTargetDesc.cpp)
0 ##===- lib/Target/Sparc/TargetDesc/Makefile ----------------*- Makefile -*-===##
1 #
2 # The LLVM Compiler Infrastructure
3 #
4 # This file is distributed under the University of Illinois Open Source
5 # License. See LICENSE.TXT for details.
6 #
7 ##===----------------------------------------------------------------------===##
8
9 LEVEL = ../../../..
10 LIBRARYNAME = LLVMSparcDesc
11
12 # Hack: we need to include 'main' target directory to grab private headers
13 CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
14
15 include $(LEVEL)/Makefile.common
0 //===-- SparcMCTargetDesc.cpp - Sparc Target Descriptions --------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Sparc specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "SparcMCTargetDesc.h"
14 #include "llvm/MC/MCInstrInfo.h"
15 #include "llvm/MC/MCRegisterInfo.h"
16 #include "llvm/MC/MCSubtargetInfo.h"
17 #include "llvm/Target/TargetRegistry.h"
18
19 #define GET_INSTRINFO_MC_DESC
20 #include "SparcGenInstrInfo.inc"
21
22 #define GET_SUBTARGETINFO_MC_DESC
23 #include "SparcGenSubtargetInfo.inc"
24
25 #define GET_REGINFO_MC_DESC
26 #include "SparcGenRegisterInfo.inc"
27
28 using namespace llvm;
29
30 MCInstrInfo *createSparcMCInstrInfo() {
31 MCInstrInfo *X = new MCInstrInfo();
32 InitSparcMCInstrInfo(X);
33 return X;
34 }
35
36 extern "C" void LLVMInitializeSparcMCInstrInfo() {
37 TargetRegistry::RegisterMCInstrInfo(TheSparcTarget, createSparcMCInstrInfo);
38 }
39
40 MCSubtargetInfo *createSparcMCSubtargetInfo(StringRef TT, StringRef CPU,
41 StringRef FS) {
42 MCSubtargetInfo *X = new MCSubtargetInfo();
43 InitSparcMCSubtargetInfo(X, TT, CPU, FS);
44 return X;
45 }
46
47 extern "C" void LLVMInitializeSparcMCSubtargetInfo() {
48 TargetRegistry::RegisterMCSubtargetInfo(TheSparcTarget,
49 createSparcMCSubtargetInfo);
50 }
0 //===-- SparcMCTargetDesc.h - Sparc Target Descriptions ---------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Sparc specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef SPARCMCTARGETDESC_H
14 #define SPARCMCTARGETDESC_H
15
16 namespace llvm {
17 class MCSubtargetInfo;
18 class Target;
19 class StringRef;
20
21 extern Target TheSparcTarget;
22 extern Target TheSparcV9Target;
23
24 } // End llvm namespace
25
26 // Defines symbolic names for Sparc registers. This defines a mapping from
27 // register name to register number.
28 //
29 #define GET_REGINFO_ENUM
30 #include "SparcGenRegisterInfo.inc"
31
32 // Defines symbolic names for the Sparc instructions.
33 //
34 #define GET_INSTRINFO_ENUM
35 #include "SparcGenInstrInfo.inc"
36
37 #define GET_SUBTARGETINFO_ENUM
38 #include "SparcGenSubtargetInfo.inc"
39
40 #endif
1515 SparcGenAsmWriter.inc SparcGenDAGISel.inc \
1616 SparcGenSubtargetInfo.inc SparcGenCallingConv.inc
1717
18 DIRS = TargetInfo
18 DIRS = TargetInfo MCTargetDesc
1919
2020 include $(LEVEL)/Makefile.common
2121
1414 #ifndef TARGET_SPARC_H
1515 #define TARGET_SPARC_H
1616
17 #include "MCTargetDesc/SparcMCTargetDesc.h"
1718 #include "llvm/Support/ErrorHandling.h"
1819 #include "llvm/Target/TargetMachine.h"
1920 #include
2728 FunctionPass *createSparcDelaySlotFillerPass(TargetMachine &TM);
2829 FunctionPass *createSparcFPMoverPass(TargetMachine &TM);
2930
30 extern Target TheSparcTarget;
31 extern Target TheSparcV9Target;
32
3331 } // end namespace llvm;
34
35 // Defines symbolic names for Sparc registers. This defines a mapping from
36 // register name to register number.
37 //
38 #define GET_REGINFO_ENUM
39 #include "SparcGenRegisterInfo.inc"
40
41 // Defines symbolic names for the Sparc instructions.
42 //
43 #define GET_INSTRINFO_ENUM
44 #include "SparcGenInstrInfo.inc"
45
4632
4733 namespace llvm {
4834 // Enums corresponding to Sparc condition codes, both icc's and fcc's. These
2222 #include "llvm/ADT/SmallVector.h"
2323
2424 #define GET_INSTRINFO_CTOR
25 #define GET_INSTRINFO_MC_DESC
2625 #include "SparcGenInstrInfo.inc"
2726
2827 using namespace llvm;
344343 SparcFI->setGlobalBaseReg(GlobalBaseReg);
345344 return GlobalBaseReg;
346345 }
347
348 MCInstrInfo *createSparcMCInstrInfo() {
349 MCInstrInfo *X = new MCInstrInfo();
350 InitSparcMCInstrInfo(X);
351 return X;
352 }
353
354 extern "C" void LLVMInitializeSparcMCInstrInfo() {
355 TargetRegistry::RegisterMCInstrInfo(TheSparcTarget, createSparcMCInstrInfo);
356 }
2323 #include "llvm/ADT/BitVector.h"
2424 #include "llvm/ADT/STLExtras.h"
2525
26 #define GET_REGINFO_MC_DESC
2726 #define GET_REGINFO_TARGET_DESC
2827 #include "SparcGenRegisterInfo.inc"
2928
1414 #include "Sparc.h"
1515 #include "llvm/Target/TargetRegistry.h"
1616
17 #define GET_SUBTARGETINFO_ENUM
18 #define GET_SUBTARGETINFO_MC_DESC
1917 #define GET_SUBTARGETINFO_TARGET_DESC
2018 #define GET_SUBTARGETINFO_CTOR
2119 #include "SparcGenSubtargetInfo.inc"
4341 // Parse features string.
4442 ParseSubtargetFeatures(CPUName, FS);
4543 }
46
47 MCSubtargetInfo *createSparcMCSubtargetInfo(StringRef TT, StringRef CPU,
48 StringRef FS) {
49 MCSubtargetInfo *X = new MCSubtargetInfo();
50 InitSparcMCSubtargetInfo(X, TT, CPU, FS);
51 return X;
52 }
53
54 extern "C" void LLVMInitializeSparcMCSubtargetInfo() {
55 TargetRegistry::RegisterMCSubtargetInfo(TheSparcTarget,
56 createSparcMCSubtargetInfo);
57 }
2020 )
2121
2222 add_subdirectory(TargetInfo)
23 add_subdirectory(MCTargetDesc)
0 add_llvm_library(LLVMSystemZDesc SystemZMCTargetDesc.cpp)
0 ##===- lib/Target/SystemZ/TargetDesc/Makefile --------------*- Makefile -*-===##
1 #
2 # The LLVM Compiler Infrastructure
3 #
4 # This file is distributed under the University of Illinois Open Source
5 # License. See LICENSE.TXT for details.
6 #
7 ##===----------------------------------------------------------------------===##
8
9 LEVEL = ../../../..
10 LIBRARYNAME = LLVMSystemZDesc
11
12 # Hack: we need to include 'main' target directory to grab private headers
13 CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
14
15 include $(LEVEL)/Makefile.common
0 //===-- SystemZMCTargetDesc.cpp - SystemZ Target Descriptions ---*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides SystemZ specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "SystemZMCTargetDesc.h"
14 #include "llvm/MC/MCInstrInfo.h"
15 #include "llvm/MC/MCRegisterInfo.h"
16 #include "llvm/MC/MCSubtargetInfo.h"
17 #include "llvm/Target/TargetRegistry.h"
18
19 #define GET_INSTRINFO_MC_DESC
20 #include "SystemZGenInstrInfo.inc"
21
22 #define GET_SUBTARGETINFO_MC_DESC
23 #include "SystemZGenSubtargetInfo.inc"
24
25 #define GET_REGINFO_MC_DESC
26 #include "SystemZGenRegisterInfo.inc"
27
28 using namespace llvm;
29
30 MCInstrInfo *createSystemZMCInstrInfo() {
31 MCInstrInfo *X = new MCInstrInfo();
32 InitSystemZMCInstrInfo(X);
33 return X;
34 }
35
36 extern "C" void LLVMInitializeSystemZMCInstrInfo() {
37 TargetRegistry::RegisterMCInstrInfo(TheSystemZTarget,
38 createSystemZMCInstrInfo);
39 }
40
41 MCSubtargetInfo *createSystemZMCSubtargetInfo(StringRef TT, StringRef CPU,
42 StringRef FS) {
43 MCSubtargetInfo *X = new MCSubtargetInfo();
44 InitSystemZMCSubtargetInfo(X, TT, CPU, FS);
45 return X;
46 }
47
48 extern "C" void LLVMInitializeSystemZMCSubtargetInfo() {
49 TargetRegistry::RegisterMCSubtargetInfo(TheSystemZTarget,
50 createSystemZMCSubtargetInfo);
51 }
0 //===-- SystemZMCTargetDesc.h - SystemZ Target Descriptions -----*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides SystemZ specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef SYSTEMZMCTARGETDESC_H
14 #define SYSTEMZMCTARGETDESC_H
15
16 namespace llvm {
17 class MCSubtargetInfo;
18 class Target;
19 class StringRef;
20
21 extern Target TheSystemZTarget;
22
23 } // End llvm namespace
24
25 // Defines symbolic names for SystemZ registers.
26 // This defines a mapping from register name to register number.
27 #define GET_REGINFO_ENUM
28 #include "SystemZGenRegisterInfo.inc"
29
30 // Defines symbolic names for the SystemZ instructions.
31 #define GET_INSTRINFO_ENUM
32 #include "SystemZGenInstrInfo.inc"
33
34 #define GET_SUBTARGETINFO_ENUM
35 #include "SystemZGenSubtargetInfo.inc"
36
37 #endif
1515 SystemZGenAsmWriter.inc SystemZGenDAGISel.inc \
1616 SystemZGenSubtargetInfo.inc SystemZGenCallingConv.inc
1717
18 DIRS = TargetInfo
18 DIRS = TargetInfo MCTargetDesc
1919
2020 include $(LEVEL)/Makefile.common
2121
1414 #ifndef LLVM_TARGET_SystemZ_H
1515 #define LLVM_TARGET_SystemZ_H
1616
17 #include "MCTargetDesc/SystemZMCTargetDesc.h"
1718 #include "llvm/Target/TargetMachine.h"
1819
1920 namespace llvm {
4647 FunctionPass *createSystemZISelDag(SystemZTargetMachine &TM,
4748 CodeGenOpt::Level OptLevel);
4849
49 extern Target TheSystemZTarget;
50
5150 } // end namespace llvm;
52
53 // Defines symbolic names for SystemZ registers.
54 // This defines a mapping from register name to register number.
55 #define GET_REGINFO_ENUM
56 #include "SystemZGenRegisterInfo.inc"
57
58 // Defines symbolic names for the SystemZ instructions.
59 #define GET_INSTRINFO_ENUM
60 #include "SystemZGenInstrInfo.inc"
61
6251 #endif
2424 #include "llvm/Support/ErrorHandling.h"
2525
2626 #define GET_INSTRINFO_CTOR
27 #define GET_INSTRINFO_MC_DESC
2827 #include "SystemZGenInstrInfo.inc"
2928
3029 using namespace llvm;
437436 case SystemZ::MOV64Prm: return get(SystemZ::MOV64Prmy);
438437 }
439438 }
440
441 MCInstrInfo *createSystemZMCInstrInfo() {
442 MCInstrInfo *X = new MCInstrInfo();
443 InitSystemZMCInstrInfo(X);
444 return X;
445 }
446
447 extern "C" void LLVMInitializeSystemZMCInstrInfo() {
448 TargetRegistry::RegisterMCInstrInfo(TheSystemZTarget,
449 createSystemZMCInstrInfo);
450 }
2525 #include "llvm/Target/TargetOptions.h"
2626 #include "llvm/ADT/BitVector.h"
2727
28 #define GET_REGINFO_MC_DESC
2928 #define GET_REGINFO_TARGET_DESC
3029 #include "SystemZGenRegisterInfo.inc"
3130
1616 #include "llvm/Target/TargetMachine.h"
1717 #include "llvm/Target/TargetRegistry.h"
1818
19 #define GET_SUBTARGETINFO_ENUM
20 #define GET_SUBTARGETINFO_MC_DESC
2119 #define GET_SUBTARGETINFO_TARGET_DESC
2220 #define GET_SUBTARGETINFO_CTOR
2321 #include "SystemZGenSubtargetInfo.inc"
5351
5452 return false;
5553 }
56
57 MCSubtargetInfo *createSystemZMCSubtargetInfo(StringRef TT, StringRef CPU,
58 StringRef FS) {
59 MCSubtargetInfo *X = new MCSubtargetInfo();
60 InitSystemZMCSubtargetInfo(X, TT, CPU, FS);
61 return X;
62 }
63
64 extern "C" void LLVMInitializeSystemZMCSubtargetInfo() {
65 TargetRegistry::RegisterMCSubtargetInfo(TheSystemZTarget,
66 createSystemZMCSubtargetInfo);
67 }
2626 #include "llvm/ADT/Twine.h"
2727 #include "llvm/Support/SourceMgr.h"
2828 #include "llvm/Support/raw_ostream.h"
29
30 #define GET_SUBTARGETINFO_ENUM
31 #include "X86GenSubtargetInfo.inc"
3229
3330 using namespace llvm;
3431
2424 #define GET_INSTRINFO_MC_DESC
2525 #include "X86GenInstrInfo.inc"
2626
27 #define GET_SUBTARGETINFO_ENUM
2827 #define GET_SUBTARGETINFO_MC_DESC
2928 #include "X86GenSubtargetInfo.inc"
3029
5353 #define GET_INSTRINFO_ENUM
5454 #include "X86GenInstrInfo.inc"
5555
56 #define GET_SUBTARGETINFO_ENUM
57 #include "X86GenSubtargetInfo.inc"
58
5659 #endif
3535 #include
3636
3737 #define GET_INSTRINFO_CTOR
38 #define GET_INSTRINFO_MC_DESC
3938 #include "X86GenInstrInfo.inc"
4039
4140 using namespace llvm;
2020 #include "llvm/MC/MCSubtargetInfo.h"
2121 #include "llvm/MC/MCSymbol.h"
2222 #include "llvm/Support/raw_ostream.h"
23
24 #define GET_SUBTARGETINFO_ENUM
25 #include "X86GenSubtargetInfo.inc"
2623
2724 using namespace llvm;
2825
3939 #include "llvm/Support/ErrorHandling.h"
4040 #include "llvm/Support/CommandLine.h"
4141
42 #define GET_REGINFO_MC_DESC
4342 #define GET_REGINFO_TARGET_DESC
4443 #include "X86GenRegisterInfo.inc"
4544
2020 #include "llvm/Target/TargetMachine.h"
2121 #include "llvm/ADT/SmallVector.h"
2222
23 #define GET_SUBTARGETINFO_ENUM
24 #define GET_SUBTARGETINFO_MC_DESC
2523 #define GET_SUBTARGETINFO_TARGET_DESC
2624 #define GET_SUBTARGETINFO_CTOR
2725 #include "X86GenSubtargetInfo.inc"
2121 )
2222
2323 add_subdirectory(TargetInfo)
24 add_subdirectory(MCTargetDesc)
0 add_llvm_library(LLVMXCoreDesc XCoreMCTargetDesc.cpp)
0 ##===- lib/Target/XCore/TargetDesc/Makefile ----------------*- Makefile -*-===##
1 #
2 # The LLVM Compiler Infrastructure
3 #
4 # This file is distributed under the University of Illinois Open Source
5 # License. See LICENSE.TXT for details.
6 #
7 ##===----------------------------------------------------------------------===##
8
9 LEVEL = ../../../..
10 LIBRARYNAME = LLVMXCoreDesc
11
12 # Hack: we need to include 'main' target directory to grab private headers
13 CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
14
15 include $(LEVEL)/Makefile.common
0 //===-- XCoreMCTargetDesc.cpp - XCore Target Descriptions -------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides XCore specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "XCoreMCTargetDesc.h"
14 #include "llvm/MC/MCInstrInfo.h"
15 #include "llvm/MC/MCRegisterInfo.h"
16 #include "llvm/MC/MCSubtargetInfo.h"
17 #include "llvm/Target/TargetRegistry.h"
18
19 #define GET_INSTRINFO_MC_DESC
20 #include "XCoreGenInstrInfo.inc"
21
22 #define GET_SUBTARGETINFO_MC_DESC
23 #include "XCoreGenSubtargetInfo.inc"
24
25 #define GET_REGINFO_MC_DESC
26 #include "XCoreGenRegisterInfo.inc"
27
28 using namespace llvm;
29
30 MCInstrInfo *createXCoreMCInstrInfo() {
31 MCInstrInfo *X = new MCInstrInfo();
32 InitXCoreMCInstrInfo(X);
33 return X;
34 }
35
36 extern "C" void LLVMInitializeXCoreMCInstrInfo() {
37 TargetRegistry::RegisterMCInstrInfo(TheXCoreTarget, createXCoreMCInstrInfo);
38 }
39
40 MCSubtargetInfo *createXCoreMCSubtargetInfo(StringRef TT, StringRef CPU,
41 StringRef FS) {
42 MCSubtargetInfo *X = new MCSubtargetInfo();
43 InitXCoreMCSubtargetInfo(X, TT, CPU, FS);
44 return X;
45 }
46
47 extern "C" void LLVMInitializeXCoreMCSubtargetInfo() {
48 TargetRegistry::RegisterMCSubtargetInfo(TheXCoreTarget,
49 createXCoreMCSubtargetInfo);
50 }
0 //===-- XCoreMCTargetDesc.h - XCore Target Descriptions ---------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides XCore specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef XCOREMCTARGETDESC_H
14 #define XCOREMCTARGETDESC_H
15
16 namespace llvm {
17 class MCSubtargetInfo;
18 class Target;
19 class StringRef;
20
21 extern Target TheXCoreTarget;
22
23 } // End llvm namespace
24
25 // Defines symbolic names for XCore registers. This defines a mapping from
26 // register name to register number.
27 //
28 #define GET_REGINFO_ENUM
29 #include "XCoreGenRegisterInfo.inc"
30
31 // Defines symbolic names for the XCore instructions.
32 //
33 #define GET_INSTRINFO_ENUM
34 #include "XCoreGenInstrInfo.inc"
35
36 #define GET_SUBTARGETINFO_ENUM
37 #include "XCoreGenSubtargetInfo.inc"
38
39 #endif
1616 XCoreGenDAGISel.inc XCoreGenCallingConv.inc \
1717 XCoreGenSubtargetInfo.inc
1818
19 DIRS = TargetInfo
19 DIRS = TargetInfo MCTargetDesc
2020
2121 include $(LEVEL)/Makefile.common
2222
1414 #ifndef TARGET_XCORE_H
1515 #define TARGET_XCORE_H
1616
17 #include "MCTargetDesc/XCoreMCTargetDesc.h"
1718 #include "llvm/Target/TargetMachine.h"
1819
1920 namespace llvm {
2425
2526 FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM);
2627
27 extern Target TheXCoreTarget;
28
2928 } // end namespace llvm;
3029
31 // Defines symbolic names for XCore registers. This defines a mapping from
32 // register name to register number.
33 //
34 #define GET_REGINFO_ENUM
35 #include "XCoreGenRegisterInfo.inc"
36
37 // Defines symbolic names for the XCore instructions.
38 //
39 #define GET_INSTRINFO_ENUM
40 #include "XCoreGenInstrInfo.inc"
41
4230 #endif
2323 #include "llvm/Support/ErrorHandling.h"
2424
2525 #define GET_INSTRINFO_CTOR
26 #define GET_INSTRINFO_MC_DESC
2726 #include "XCoreGenInstrInfo.inc"
2827
2928 namespace llvm {
396395 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm()));
397396 return false;
398397 }
399
400 MCInstrInfo *createXCoreMCInstrInfo() {
401 MCInstrInfo *X = new MCInstrInfo();
402 InitXCoreMCInstrInfo(X);
403 return X;
404 }
405
406 extern "C" void LLVMInitializeXCoreMCInstrInfo() {
407 TargetRegistry::RegisterMCInstrInfo(TheXCoreTarget, createXCoreMCInstrInfo);
408 }
3232 #include "llvm/Support/ErrorHandling.h"
3333 #include "llvm/Support/raw_ostream.h"
3434
35 #define GET_REGINFO_MC_DESC
3635 #define GET_REGINFO_TARGET_DESC
3736 #include "XCoreGenRegisterInfo.inc"
3837
1414 #include "XCore.h"
1515 #include "llvm/Target/TargetRegistry.h"
1616
17 #define GET_SUBTARGETINFO_ENUM
18 #define GET_SUBTARGETINFO_MC_DESC
1917 #define GET_SUBTARGETINFO_TARGET_DESC
2018 #define GET_SUBTARGETINFO_CTOR
2119 #include "XCoreGenSubtargetInfo.inc"
2725 : XCoreGenSubtargetInfo(TT, CPU, FS)
2826 {
2927 }
30
31
32 MCSubtargetInfo *createXCoreMCSubtargetInfo(StringRef TT, StringRef CPU,
33 StringRef FS) {
34 MCSubtargetInfo *X = new MCSubtargetInfo();
35 InitXCoreMCSubtargetInfo(X, TT, CPU, FS);
36 return X;
37 }
38
39 extern "C" void LLVMInitializeXCoreMCSubtargetInfo() {
40 TargetRegistry::RegisterMCSubtargetInfo(TheXCoreTarget,
41 createXCoreMCSubtargetInfo);
42 }
197197
198198 // Emit all of the MCInstrDesc records in their ENUM ordering.
199199 //
200 OS << "\nstatic const MCInstrDesc " << TargetName
201 << "Insts[] = {\n";
200 OS << "\nMCInstrDesc " << TargetName << "Insts[] = {\n";
202201 const std::vector &NumberedInstructions =
203202 Target.getInstructionsByEnumValue();
204203
234233 OS << "#undef GET_INSTRINFO_CTOR\n";
235234
236235 OS << "namespace llvm {\n";
236 OS << "extern const MCInstrDesc " << TargetName << "Insts[];\n";
237237 OS << ClassName << "::" << ClassName << "(int SO, int DO)\n"
238238 << " : TargetInstrInfoImpl(SO, DO) {\n"
239239 << " InitMCInstrInfo(" << TargetName << "Insts, "
161161 OS << getQualifiedName(SR[j]->TheDef) << ", ";
162162 OS << "0 };\n";
163163 }
164
165 OS << "\n const MCRegisterDesc " << TargetName
164 OS << "}\n"; // End of anonymous namespace...
165
166 OS << "\nMCRegisterDesc " << TargetName
166167 << "RegDesc[] = { // Descriptors\n";
167 OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
168 OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
168169
169170 // Now that register alias and sub-registers sets have been emitted, emit the
170171 // register descriptors now.
171172 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
172173 const CodeGenRegister &Reg = *Regs[i];
173 OS << " { \"";
174 OS << " { \"";
174175 OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
175176 if (!Reg.getSubRegs().empty())
176177 OS << Reg.getName() << "_SubRegsSet,\t";
182183 OS << "Empty_SuperRegsSet";
183184 OS << " },\n";
184185 }
185 OS << " };\n"; // End of register descriptors...
186
187 OS << "}\n\n"; // End of anonymous namespace...
186 OS << "};\n\n"; // End of register descriptors...
188187
189188 // MCRegisterInfo initialization routine.
190189 OS << "static inline void Init" << TargetName
544543 OS << " &" << getQualifiedName(RegisterClasses[i].TheDef)
545544 << "RegClass,\n";
546545 OS << " };\n";
546 OS << "}\n"; // End of anonymous namespace...
547547
548548 // Emit extra information about registers.
549549 const std::string &TargetName = Target.getName();
568568
569569 // Emit SubRegIndex names, skipping 0
570570 const std::vector &SubRegIndices = RegBank.getSubRegIndices();
571 OS << "\n const char *const SubRegIndexTable[] = { \"";
571 OS << "\n static const char *const " << TargetName
572 << "SubRegIndexTable[] = { \"";
572573 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
573574 OS << SubRegIndices[i]->getName();
574575 if (i+1 != e)
586587 }
587588 OS << "\n };\n\n";
588589 }
589 OS << "}\n\n"; // End of anonymous namespace...
590 OS << "\n";
590591
591592 std::string ClassName = Target.getName() + "GenRegisterInfo";
592593
657658 OS << " }\n}\n\n";
658659
659660 // Emit the constructor of the class...
661 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
662
660663 OS << ClassName << "::" << ClassName
661664 << "()\n"
662665 << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
663666 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
664 << " SubRegIndexTable) {\n"
667 << " " << TargetName << "SubRegIndexTable) {\n"
665668 << " InitMCRegisterInfo(" << TargetName << "RegDesc, "
666669 << Regs.size()+1 << ");\n"
667670 << "}\n\n";
8080
8181 // Begin feature table
8282 OS << "// Sorted (by key) array of values for CPU features.\n"
83 << "static const llvm::SubtargetFeatureKV "
84 << Target << "FeatureKV[] = {\n";
83 << "llvm::SubtargetFeatureKV " << Target << "FeatureKV[] = {\n";
8584
8685 // For each feature
8786 unsigned NumFeatures = 0;
140139
141140 // Begin processor table
142141 OS << "// Sorted (by key) array of values for CPU subtype.\n"
143 << "static const llvm::SubtargetFeatureKV "
144 << Target << "SubTypeKV[] = {\n";
142 << "llvm::SubtargetFeatureKV " << Target << "SubTypeKV[] = {\n";
145143
146144 // For each processor
147145 for (unsigned i = 0, N = ProcessorList.size(); i < N;) {
328326 OS << "\n// Pipeline forwarding pathes for itineraries \"" << Name
329327 << "\"\n" << "namespace " << Name << "Bypass {\n";
330328
331 OS << " const unsigned NoBypass = 0;\n";
329 OS << " unsigned NoBypass = 0;\n";
332330 for (unsigned j = 0, BPN = BPs.size(); j < BPN; ++j)
333 OS << " const unsigned " << BPs[j]->getName()
331 OS << " unsigned " << BPs[j]->getName()
334332 << " = 1 << " << j << ";\n";
335333
336334 OS << "}\n";
338336 }
339337
340338 // Begin stages table
341 std::string StageTable = "\nstatic const llvm::InstrStage " + Target +
342 "Stages[] = {\n";
339 std::string StageTable = "\nllvm::InstrStage " + Target + "Stages[] = {\n";
343340 StageTable += " { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary\n";
344341
345342 // Begin operand cycle table
346 std::string OperandCycleTable = "static const unsigned " + Target +
343 std::string OperandCycleTable = "unsigned " + Target +
347344 "OperandCycles[] = {\n";
348345 OperandCycleTable += " 0, // No itinerary\n";
349346
350347 // Begin pipeline bypass table
351 std::string BypassTable = "static const unsigned " + Target +
348 std::string BypassTable = "unsigned " + Target +
352349 "ForwardingPathes[] = {\n";
353350 BypassTable += " 0, // No itinerary\n";
354351
490487
491488 // Begin processor itinerary table
492489 OS << "\n";
493 OS << "static const llvm::InstrItinerary " << Name << "[] = {\n";
490 OS << "llvm::InstrItinerary " << Name << "[] = {\n";
494491
495492 // For each itinerary class
496493 std::vector &ItinList = *ProcListIter++;
532529 // Begin processor table
533530 OS << "\n";
534531 OS << "// Sorted (by key) array of itineraries for CPU subtype.\n"
535 << "static const llvm::SubtargetInfoKV "
532 << "llvm::SubtargetInfoKV "
536533 << Target << "ProcItinKV[] = {\n";
537534
538535 // For each processor
656653 OS << "#undef GET_SUBTARGETINFO_MC_DESC\n";
657654
658655 OS << "namespace llvm {\n";
656 #if 0
657 OS << "namespace {\n";
658 #endif
659659 unsigned NumFeatures = FeatureKeyValues(OS);
660 OS<<"\n";
660 OS << "\n";
661661 unsigned NumProcs = CPUKeyValues(OS);
662 OS<<"\n";
662 OS << "\n";
663663 EmitData(OS);
664 OS<<"\n";
664 OS << "\n";
665 #if 0
666 OS << "}\n";
667 #endif
665668
666669 // MCInstrInfo initialization routine.
667670 OS << "static inline void Init" << Target
716719 OS << "#undef GET_SUBTARGETINFO_CTOR\n";
717720
718721 OS << "namespace llvm {\n";
722 OS << "extern const llvm::SubtargetFeatureKV " << Target << "FeatureKV[];\n";
723 OS << "extern const llvm::SubtargetFeatureKV " << Target << "SubTypeKV[];\n";
724 if (HasItineraries) {
725 OS << "extern const llvm::SubtargetInfoKV " << Target << "ProcItinKV[];\n";
726 OS << "extern const llvm::InstrStage " << Target << "Stages[];\n";
727 OS << "extern const unsigned " << Target << "OperandCycles[];\n";
728 OS << "extern const unsigned " << Target << "ForwardingPathes[];\n";
729 }
730
719731 OS << ClassName << "::" << ClassName << "(StringRef TT, StringRef CPU, "
720732 << "StringRef FS)\n"
721733 << " : TargetSubtargetInfo() {\n"